US Patent Application 17841510. STEP-STACKED NANOWIRE CMOS STRUCTURE FOR LOW POWER LOGIC DEVICE AND METHOD OF MANUFACTURING THE SAME simplified abstract
STEP-STACKED NANOWIRE CMOS STRUCTURE FOR LOW POWER LOGIC DEVICE AND METHOD OF MANUFACTURING THE SAME
Organization Name
Inventor(s)
Byounghak Hong of Latham NY (US)
Seungchan Yun of Waterford NY (US)
Kang-ill Seo of Albany NY (US)
STEP-STACKED NANOWIRE CMOS STRUCTURE FOR LOW POWER LOGIC DEVICE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 17841510 Titled 'STEP-STACKED NANOWIRE CMOS STRUCTURE FOR LOW POWER LOGIC DEVICE AND METHOD OF MANUFACTURING THE SAME'
Simplified Explanation
The abstract describes a CMOS device, which is a type of integrated circuit technology commonly used in electronic devices. This device includes a substrate with a shallow trench isolation region, which helps to isolate different components on the substrate. It also includes an nFET (n-channel field-effect transistor) and a pFET (p-channel field-effect transistor).
The nFET consists of a source region, a drain region, and a channel region. The channel region is made up of a series of nanowires that extend from the source region to the drain region. Surrounding these nanowires is a gate region. The nanowires are organized into two columns - a first column and a second column adjacent to the first column.
The pFET also has a source region, a drain region, and a channel region. The channel region extends from the source region to the drain region, and it has a gate region on top.
Overall, this CMOS device is designed to perform electronic functions using both nFET and pFET components, with the nFET utilizing nanowires in its channel region.
Original Abstract Submitted
A CMOS device including a substrate comprising a shallow trench isolation region, an nFET on the substrate above the shallow trench isolation region, and a pFET. The nFET includes a source region, a drain region, a channel region including a series of nanowires extending from the source region to the drain region, and a gate region around the series of nanowires of the channel region. The nanowires include a first series of nanowires in a first column and a second series of nanowires in a second column adjacent to the first column. The pFET includes a source region, a drain region, a channel region extending from the source region to the drain region, and a gate region on the channel region.
