US Patent Application 17829324. MEMORY DEVICE WITH BACK-GATE TRANSISTOR AND METHOD OF FORMING THE SAME simplified abstract

MEMORY DEVICE WITH BACK-GATE TRANSISTOR AND METHOD OF FORMING THE SAME

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor(s)

MENG-HAN Lin of HSINCHU (TW)

CHIA-EN Huang of HSINCHU COUNTY (TW)

YA-YUN Cheng of TAICHUNG CITY (TW)

PENG-CHUN Liou of TAINAN CITY (TW)

MEMORY DEVICE WITH BACK-GATE TRANSISTOR AND METHOD OF FORMING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17829324 titled 'MEMORY DEVICE WITH BACK-GATE TRANSISTOR AND METHOD OF FORMING THE SAME

Simplified Explanation

The patent application describes a method for forming an interconnect structure over a substrate, which includes a memory device with a transistor.

• The method involves forming a first metallization layer and a second metallization layer over the first layer.
• A gate region of the transistor is formed in either the first or second metallization layer.
• A trench is etched in the second metallization layer to expose the gate region.
• A gate dielectric layer is deposited in the trench over the gate region.
• A channel layer is deposited in the trench over the gate dielectric layer.
• Two source/drain regions of the transistor are formed over the channel layer on opposite sides of the trench.
• The gate region and/or the channel layer may include two parallel first segments extending in the trench.

Original Abstract Submitted

A method includes: forming an interconnect structure over a substrate, the forming of the interconnect structure includes forming a memory device including a transistor. The forming of the interconnect structure includes: forming a first metallization layer and a second metallization layer over the first metallization layer; forming a gate region of the transistor in at least one of the first and second metallization layers; etching a trench disposed in the second metallization layer and exposing the gate region; depositing a gate dielectric layer in the trench over the gate region; depositing a channel layer in the trench over the gate dielectric layer; and forming two source/drain regions of the transistor over the channel layer on opposite sides of the trench. At least one of the gate region and the channel layer includes two first segments extending in the trench, wherein the first segments are parallel with each other.