US Patent Application 17827562. SYSTEMS AND METHODS OF CORRECTING ERRORS IN UNMATCHED MEMORY DEVICES simplified abstract

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SYSTEMS AND METHODS OF CORRECTING ERRORS IN UNMATCHED MEMORY DEVICES

Organization Name

SanDisk Technologies LLC

Inventor(s)

Venkatesh Prasad Ramachandra of San Jose CA (US)

Jang Woo Lee of San Ramon CA (US)

Srinivas Rajendra of San Jose CA (US)

Anil Pai of San Jose CA (US)

SYSTEMS AND METHODS OF CORRECTING ERRORS IN UNMATCHED MEMORY DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17827562 titled 'SYSTEMS AND METHODS OF CORRECTING ERRORS IN UNMATCHED MEMORY DEVICES

Simplified Explanation

- The patent application describes systems and methods for correcting errors in unmatched memory devices. - The embodiments train a memory interface to determine a duty cycle timing for a clock signal in a data window formed by a data signal in a memory cell. - The duty cycle timing identifies an initial trained timing in the data window where the setup portion and hold portion of the data window are approximately equal in length. - An event is identified that shifts the duty cycle timing away from the initial trained timing. - A retraining of the memory interface is triggered based on a determination that at least one of two points defined about the initial trained timing fails a two-point sampling.


Original Abstract Submitted

Systems and methods are provided for correcting errors in unmatched memory devices. Various embodiments herein train a memory interface to determine a duty cycle timing for a clock signal in a data window formed by a data signal in a memory cell. The duty cycle timing identifies an initial trained timing in the data window at which a setup portion and a hold portion of the data window are approximately equal in length when the trigger signal is received at the initial trained timing. The embodiments herein also identify an event that shifts the duty cycle timing away from the initial trained timing, and triggers a retraining of the memory interface based on a determination that at least one of two points defined about the initial trained timing fails a two-point sampling.