US Patent Application 17825337. NON-VOLATILE MEMORY WITH INTER-DIE CONNECTION simplified abstract
Contents
NON-VOLATILE MEMORY WITH INTER-DIE CONNECTION
Organization Name
Inventor(s)
Shiqian Shao of Fremont CA (US)
Fumiaki Toyama of Cupertino CA (US)
NON-VOLATILE MEMORY WITH INTER-DIE CONNECTION - A simplified explanation of the abstract
This abstract first appeared for US patent application 17825337 titled 'NON-VOLATILE MEMORY WITH INTER-DIE CONNECTION
Simplified Explanation
The patent application describes a non-volatile memory apparatus that consists of a stack of integrated memory assemblies.
- Each integrated memory assembly includes a memory die and a control die, which are connected by a set of power pads and metal lines.
- The memory dies have a non-volatile memory structure and a top metal layer for transmitting power signals.
- The control dies have a control circuit for performing memory operations and a set of metal layers.
- The substrate of the control dies has conductive vias that connect to the top metal layer of the memory die in the adjacent assembly, allowing signals to be routed between the integrated memory assemblies.
Original Abstract Submitted
A non-volatile memory apparatus comprises a stack of integrated memory assemblies. Each integrated memory assembly includes a memory die bonded to a control die and a set of power pads connected to metal lines in the respective memory die and control die. The memory dies comprise a non-volatile memory structure and a top metal layer for transmitting power signals above the memory structure. The control dies comprise a substrate, a control circuit positioned on the substrate for performing memory operations on a corresponding memory structure and a set of metals layers above the control circuit. The substrate comprises a set of conductive vias through the substrate that connect at one end to the top metal layer of the memory die of an adjacent integrated memory assembly and connect at a second end to the set of metals layers above the control circuit for routing signals between integrated memory assemblies.
