US Patent Application 17824669. SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE simplified abstract

SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==

[[Category:Hung-Yu Yen of Hsinchu (TW)]]

[[Category:Wei-Ting Yeh of Hsinchu (TW)]]

[[Category:Ko-Feng Chen of Hsinchu (TW)]]

[[Category:Keng-Chu Lin of Hsinchu (TW)]]

SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17824669 titled 'SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE

Simplified Explanation

- The patent application describes a method for forming a semiconductor device. - The method involves forming a fin feature on a semiconductor substrate and a dummy gate feature over the fin feature. - The fin feature includes a sacrificial portion and a fin portion. - The dummy gate feature is connected to the fin feature and the semiconductor substrate. - The sacrificial portion is then removed to create a gap between the semiconductor substrate and the fin portion. - A dielectric isolation layer is formed to fill the gap and electrically isolate the fin portion from the semiconductor substrate. - Source/drain features are subsequently formed over the dielectric isolation layer. - The dummy gate feature is processed to form a gate electrode feature on the fin portion.

Original Abstract Submitted

A method is provided for forming a semiconductor device. A fin feature is formed on a semiconductor substrate, and a dummy gate feature is formed over the fin feature. The fin feature includes a sacrificial portion disposed over the semiconductor substrate, and a fin portion disposed over the sacrificial portion. The dummy gate feature is connected to the fin feature and the semiconductor substrate. Then, the sacrificial portion is removed to form a gap between the semiconductor substrate and the fin portion. A dielectric isolation layer is formed to fill the gap for electrically isolating the fin portion from the semiconductor substrate. Subsequently, source/drain features are formed over the dielectric isolation layer, and the dummy gate feature is processed to form a gate electrode feature on the fin portion.