US Patent Application 17816438. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract

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SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Organization Name

CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor(s)

YOUMING Liu of Hefei City (CN)

Deyuan Xiao of Hefei City (CN)

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 17816438 titled 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Simplified Explanation

The present disclosure describes a semiconductor structure and a manufacturing method for semiconductors.

  • The structure includes a substrate and a first stacked structure that contains a memory cell array.
  • The first stacked structure also includes a plurality of word lines (WLs) that are electrically connected to the memory cell array.
  • Additionally, there are a plurality of bit lines (BLs) that are located beside the first stacked structure and are also electrically connected to the memory cell array.
  • Each BL has a step at one end away from the memory cell array and consists of a first core layer and a first conductive layer covering the core layer.
  • The structure also includes a plurality of BL plugs, with each BL plug being in contact with the first conductive layer of one of the BLs.


Original Abstract Submitted

The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors, including: a substrate, a first stacked structure is disposed on the substrate, and the first stacked structure includes a memory cell array; a plurality of word lines (WLs), where the WL is disposed in the first stacked structure and is electrically connected to the memory cell array; a plurality of bit lines (BLs), the BL is disposed beside the first stacked structure, and is electrically connected to the memory cell array; and one end of each BL away from the memory cell array forms a step, and the BL includes a first core layer and a first conductive layer covering the first core layer; and a plurality of BL plugs, each BL plug is in corresponding contact with the first conductive layer of one of the BLs.

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