US Patent Application 17816436. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract

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SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Organization Name

CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor(s)

YOUMING Liu of Hefei City (CN)

Deyuan Xiao of Hefei City (CN)

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 17816436 titled 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Simplified Explanation

The present disclosure is about a semiconductor structure and its manufacturing method in the field of semiconductors.

  • The semiconductor structure includes a substrate and a memory cell array located on the substrate.
  • The memory cell array consists of multiple transistor units, each having a first transistor and a second transistor connected to each other.
  • The first and second transistors extend along a first direction parallel to the substrate.
  • There is a first bit line that goes through the memory cell array and is connected to the first transistor.
  • Similarly, there is a second bit line that goes through the memory cell array and is connected to the second transistor.
  • The structure also includes a first word line connected to the first transistor and a second word line connected to the second transistor.

The patent application describes a semiconductor structure that simplifies the memory cell array and improves its functionality.


Original Abstract Submitted

The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a memory cell array, located on the substrate, the memory cell array includes a plurality of transistor units, each of the transistor units includes a first transistor and a second transistor extending along a first direction and electrically connected to each other, and the first direction is parallel to the substrate; a first bit line, penetrating the memory cell array and electrically connected to the first transistor; a second bit line, penetrating the memory cell array and electrically connected to the second transistor; a first word line, electrically connected to the first transistor; and a second word line, electrically connected to the second transistor.

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