US Patent Application 17752461. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES simplified abstract

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.==Inventor(s)==

[[Category:Yung-Hsiang Chan of Taichung (TW)]]

[[Category:An-Hung Tai of Hsinchu (TW)]]

[[Category:Hui-Chi Chen of Zhudong Township (TW)]]

[[Category:J.F. Chueh of Hsinchu City (TW)]]

[[Category:Yen-Ta Lin of Taipei City (TW)]]

[[Category:Ming-Chi Huang of Zhubei City (TW)]]

[[Category:Cheng-Chieh Tu of Hsinchu (TW)]]

[[Category:Jian-Hao Chen of Hsinchu City (TW)]]

[[Category:Kuo-Feng Yu of Zhudong Township (TW)]]

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17752461 titled 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES

Simplified Explanation

The patent application describes a method of manufacturing a semiconductor device.

• A sacrificial gate electrode is removed to create a gate space over a channel region.
• A first gate dielectric layer is formed over the channel region in the gate space.
• A second gate dielectric layer is formed over the first gate dielectric layer.
• One or more conductive layers are formed on top of the second gate dielectric layer.
• The second gate dielectric layer and the conductive layers are recessed.
• An annealing operation is performed to diffuse an element of the second gate dielectric layer into the first gate dielectric layer.
• One or more metal layers are formed in the gate space.

Original Abstract Submitted

In a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode formed over a channel region, a first gate dielectric layer is formed over the channel region in the gate space, a second gate dielectric layer is formed over the first gate dielectric layer, one or more conductive layers is formed on the second gate dielectric layer, the second gate dielectric layer and the one or more conductive layers are recessed, an annealing operation is performed to diffuse an element of the second gate dielectric layer into the first gate dielectric layer, and one or more metal layers are formed in the gate space.