US Patent Application 17727324. DYNAMIC SHIFT IN OUTPUTS OF SERIAL AND PARALLEL SCRAMBLERS AND DESCRAMBLERS simplified abstract

DYNAMIC SHIFT IN OUTPUTS OF SERIAL AND PARALLEL SCRAMBLERS AND DESCRAMBLERS

Organization Name

Microsoft Technology Licensing, LLC

Inventor(s)

Asaf Levy of Hod Hasharon (IL)

DYNAMIC SHIFT IN OUTPUTS OF SERIAL AND PARALLEL SCRAMBLERS AND DESCRAMBLERS - A simplified explanation of the abstract

• This abstract for appeared for US patent application number 17727324 Titled 'DYNAMIC SHIFT IN OUTPUTS OF SERIAL AND PARALLEL SCRAMBLERS AND DESCRAMBLERS'

Simplified Explanation

This abstract describes methods and systems for reconfiguring the position of a tap in a descrambler circuit after it has been trained and synchronized with a corresponding scrambler circuit. The reconfiguration, known as the "lock-shift" operation, involves bypassing certain logic elements in the data path to reduce delay in the descrambler circuit. The tap position change can be communicated to the scrambler circuit through a mode manager, either directly or indirectly. The indirect method involves in-band transmissions between two integrated circuits (ICs) that have self-synchronizing scrambler/descrambler pairs. The reconfiguration in the scrambler circuit is based on monitored receiver signals that indicate synchronization or the presence of descrambled data in the descrambler circuit's output.

Original Abstract Submitted

Methods, systems are provided for reconfiguring the position of a first tap in a descrambler circuit LFSR after the LFSR has been trained and synchronized with a corresponding scrambler circuit LFSR. A data path from the second tap position to the descrambler output by-passes logic elements located in the data path from the first tap to the descrambler output, thereby reducing delay in the descrambler circuit after the reconfiguration (i.e., the “lock-shift” operation). The tap position change may be communicated by a mode manager to a corresponding scrambler circuit, for applying a matching reconfiguration in the scrambler circuit, either directly via an I/O line or indirectly. The indirect route includes in-band transmissions between two ICs with two sets of self-synchronizing scrambler/descrambler pairs, and is based on monitored receiver LFSR output signals that indicate when a scrambler/descrambler pair is synchronized or whether the output of a descrambler circuit comprises descrambled data.