TEXAS INSTRUMENTS INCORPORATED patent applications on March 6th, 2025
Patent Applications by TEXAS INSTRUMENTS INCORPORATED on March 6th, 2025
TEXAS INSTRUMENTS INCORPORATED: 44 patent applications
TEXAS INSTRUMENTS INCORPORATED has applied for patents in the areas of H01L23/00 (8), H01L23/31 (7), H01L21/56 (6), H01L23/495 (4), H03K17/687 (3) B24B41/068 (1), H03M1/785 (1), H03K3/017 (1), H03K3/35625 (1), H03K5/01 (1)
With keywords such as: terminal, coupled, circuit, control, device, surface, having, transistor, die, and output in patent application abstracts.
Patent Applications by TEXAS INSTRUMENTS INCORPORATED
20250073845. WAFER BACKGRINDING_simplified_abstract_(texas instruments incorporated)
Inventor(s): GAIL EDSELLE REYES of ANGELES CITY (PH) for texas instruments incorporated, CONNIE ESTERON of MABALACAT (PH) for texas instruments incorporated
IPC Code(s): B24B41/06, B24B7/22, H01L21/304, H01L21/683, H01L21/78
CPC Code(s): B24B41/068
Abstract: a device for a grinding table includes a shim with a cross section shaped to mirror a cross section of a step gap formed at an edge of grinding tape adhered to a first side of a wafer that covers solder balls, such that the shim and the grinding tape form a planer surface on a grinding table for the wafer.
20250074765. HIGH RELIABILITY SENSOR_simplified_abstract_(texas instruments incorporated)
Inventor(s): Daiki Komatsu of BEPPU-SHI OITA-KEN (JP) for texas instruments incorporated, Masamitsu Matsuura of BEPPU-SHI OITA-KEN (JP) for texas instruments incorporated, Mao Sugeno of BEPPU-SHI OITA-KEN (JP) for texas instruments incorporated
IPC Code(s): B81B7/00, B81C1/00
CPC Code(s): B81B7/0048
Abstract: an electronic device includes first and second semiconductor dies, the first semiconductor die having: a side extending in a first plane of orthogonal first and second directions; a sensor circuit along the side; and a conductive terminal extending outward from the side along an orthogonal third direction, and the second semiconductor die bonded to the first semiconductor die and having: a bottom side; a lateral side; and an insulation layer, the bottom side spaced apart from and facing the side of the first semiconductor die to form a protected chamber for the sensor circuit, the lateral side of the second semiconductor die spaced apart from the conductive terminal along the first direction, the insulation layer extending along the lateral side of the second semiconductor die, and the insulation layer spaced apart from and facing the conductive terminal along the first direction.
Inventor(s): Sebastian MEIER of Munich (DE) for texas instruments incorporated, Rujuta MUNJE of McKinney TX (US) for texas instruments incorporated, Tobias Bernhard FRITZ of Mainburg (DE) for texas instruments incorporated, Sreenivasan Kalyani KODURI of Dallas TX (US) for texas instruments incorporated
IPC Code(s): G01F1/64, G01F1/002
CPC Code(s): G01F1/64
Abstract: in examples, a sensing device comprises a semiconductor die including a device side and a fluid sensor in the device side. the device comprises a metal ring forming an opening over the fluid sensor, the metal ring having a top surface, a bottom surface, and an inner surface extending between the top surface and the bottom surface, and the bottom surface being on the device side. at least a portion of the inner surface abuts the device side being plated with a noble metal. the device includes a mold compound covering the semiconductor die and a first portion of the metal ring, in which a second portion of the metal ring having the top surface protrudes out of the mold compound and provides at least one of a cartridge interface or a tube interface.
Inventor(s): Jeronimo Segovia Fernandez of San Jose CA (US) for texas instruments incorporated, Bichoy Bahr of Allen TX (US) for texas instruments incorporated, Hassan Omar Ali of Murphy TX (US) for texas instruments incorporated, Benjamin Stassen Cook of Los Gatos CA (US) for texas instruments incorporated
IPC Code(s): G01N21/3504, B81B3/00, G01J5/08, G01N21/27, G01N21/61
CPC Code(s): G01N21/3504
Abstract: in some examples, an apparatus comprises a chopper, a first microelectromechanical system (mems) device, a second mems device, and a processing circuit. the chopper configured is to repeatedly switch states to enable and disable provision of a light signal. the first mems device is configured to provide first and second irradiance signals when the chopper is in, respectively, first and second states the second mems device is configured to provide first and second reference signals when the chopper is in, respectively, the first and second states. the processing circuit is configured to generate a first signal based on the first irradiance signal and the first reference signal, generate a second signal based on the second irradiance signal and the second reference signal, and provide a third signal at the processing output representing an irradiance measurement of the light source based on a difference between the first and second signals.
20250076348. OPTO-EMULATOR_simplified_abstract_(texas instruments incorporated)
Inventor(s): Kashyap BAROT of Bengaluru (IN) for texas instruments incorporated, Arvind GUPTA of New Delhi (IN) for texas instruments incorporated, Avinash SHAH of Jharsuguda (IN) for texas instruments incorporated, Sreeram Nasum S of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): G01R19/00
CPC Code(s): G01R19/0038
Abstract: an opto-emulator transmitter includes: a current controller; an oscillator circuit; and receiver replica circuitry. the current controller has a first terminal, a second terminal, and a third terminal. the oscillator circuit has a first terminal, a second terminal, and a third terminal. the first terminal of the oscillator circuit is coupled to the second terminal of the current controller. the receiver replica circuitry has a first terminal, a second terminal, and a third terminal. the first terminal of the receiver replica circuitry is coupled to the second terminal of the oscillator circuit. the second terminal of the receiver replica circuitry is coupled to the third terminal of the oscillator circuit. the third terminal of the receiver replica circuitry is coupled to the third terminal of the current controller.
Inventor(s): Qunying LI of Allen TX (US) for texas instruments incorporated, Shanmuganand CHELLAMUTHU of Richardson TX (US) for texas instruments incorporated, Harish KUMAR of Frisco TX (US) for texas instruments incorporated
IPC Code(s): G01R35/00, G01D5/244, G01D5/245, G01R33/09
CPC Code(s): G01R35/005
Abstract: a circuit includes an anisotropic magnetoresistance (amr) sensor; an operational amplifier; and a calibration circuit. the amr sensor has a first terminal, a second terminal, a third terminal, and a fourth terminal. the operational amplifier has a first terminal, a second terminal, a third terminal, and a fourth terminal. the first terminal of the operational amplifier is coupled to the second terminal of the amr sensor. the second terminal of the operational amplifier is coupled to the third terminal of the amr sensor. the calibration circuit is coupled to the first terminal of the operational amplifier. the calibration circuit is configured to provide an adjustable offset trim voltage at the first terminal of the operational amplifier to cancel out an offset voltage generated by the amr sensor.
Inventor(s): Venkatesh Guduri of Bangalore (IN) for texas instruments incorporated, Ganapathi Shankar of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G05F1/575, G05F3/26, H03K17/082, H03K17/10, H03K17/687
CPC Code(s): G05F1/575
Abstract: a load current sensing circuit includes a sense leg including a sense transistor with a gate coupled to the output of a high-side gate driver, a feedback transistor, and a sense resistor coupled in series between a power supply and ground. an amplifier has differential inputs coupled to the sense leg and to an output, and an output coupled to the feedback transistor gate. a bias circuit has a first transistor coupled between the power supply voltage and the first bias voltage terminal, and a gate receiving, from a first leg, a first differential from the output voltage. a second leg in the amplifier bias circuit generates a gate voltage, for a second transistor coupled between ground and a second bias voltage terminal, that is at a second differential from a voltage at the first bias voltage terminal. the amplifier is biased between the first and second bias voltages.
Inventor(s): Rajat Chauhan of Bangalore (IN) for texas instruments incorporated, Divya Kaur of Delhi (IN) for texas instruments incorporated
IPC Code(s): G05F3/26, G01R35/00
CPC Code(s): G05F3/262
Abstract: in described examples, a circuit includes a current mirror circuit. a first stage is coupled to the current mirror circuit. a second stage is coupled to the current mirror circuit and to the first stage. a voltage divider network is coupled to the second stage. the circuit includes an output transistor having first and second terminals, in which the first terminal of the output transistor is coupled to the first stage, and the second terminal of the output transistor is coupled to the voltage divider network.
Inventor(s): Atul Ramakant LELE of Bengaluru (IN) for texas instruments incorporated, Paul John PATCHEN of Arlington TX (US) for texas instruments incorporated, Ryan Alexander SMITH of Lucas TX (US) for texas instruments incorporated, Bernd Hannes SCHNEIDER of Freising (DE) for texas instruments incorporated
IPC Code(s): G06F1/12, H03K21/02
CPC Code(s): G06F1/12
Abstract: an electronic circuit includes an oscillator circuit, a first divider circuit, a synchronization control circuit, and a peripheral circuit. the oscillator circuit is configured to generate a base frequency clock. the first divider circuit is configured to divide the base frequency clock by a first selectable divisor to generate a divided clock. the synchronization control circuit is configured to generate a synchronization pulse that controls a change of the first selectable divisor in the first divider circuit from a first value to a second value. a pulse width of the synchronization pulse is based on the first value of the first selectable divisor. the peripheral circuit is coupled to the first divider circuit and the synchronization control circuit. the peripheral circuit includes a second divider circuit. the second divider circuit divides the divided clock by a second selectable divisor, and change the second selectable divisor responsive to the synchronization pulse.
Inventor(s): Ruchi Shankar of Bengaluru (IN) for texas instruments incorporated, Robin O. Hoel of Olso (NO) for texas instruments incorporated, Patrick Seem of Oslo (NO) for texas instruments incorporated, Oddgeir Fikstvedt of Oslo (NO) for texas instruments incorporated, Jan-Tore Marienborg of Oslo (NO) for texas instruments incorporated
IPC Code(s): G06F1/26, G06F1/3203, H03K3/356, H03K19/0185
CPC Code(s): G06F1/263
Abstract: embodiments disclosed herein relate to split rail architecture for power supplies in a system, and more particularly, to providing isolation and control of a power supply. in an example, an integrated circuit device is provided that includes a device voltage supply, an input/output (i/o) voltage supply coupled to the device voltage supply, and a level shifter circuit coupled to the i/o voltage supply. the level shifter circuit includes a pair of cross-coupled p-type metal-oxide semiconductor field effect transistors (pmos transistors), a pair of n-type transistors (nmos transistors) coupled between the pair of cross-coupled pmos transistors and a ground connection, and an inverter circuit coupled to the device voltage supply and the level shifter circuit. the level shifter circuit further includes a capacitor coupled to the pair of cross-coupled pmos transistors and the ground connection and is in parallel with respect to a first one of the pair of nmos transistors.
Inventor(s): Atul Lele of Bangalore (IN) for texas instruments incorporated, Mahesh Mehendale of Garland TX (US) for texas instruments incorporated, Uri Weinrib of Mazkeret Batya (IL) for texas instruments incorporated, Anurag Choudhury of Faridabad (IN) for texas instruments incorporated
IPC Code(s): G06F9/30, G06F9/38
CPC Code(s): G06F9/30145
Abstract: disclosed herein are improvements to instructions and hardware for performing neural network operations. in an embodiment, a processing device includes instruction fetch circuitry, decoder circuitry, and neural network operation circuitry. the instruction fetch circuitry is configured to fetch a neural network instruction from memory that specifies an operation and a set of values that enable sub-circuits of the neural network operation circuitry for use with one or more of the operations of the group of operations and provide the neural network instruction to the decoder circuitry. the decoder circuitry is configured to cause the neural network operation circuitry to perform, based on the operation, a convolution operation using a first sub-circuit of the neural network operation circuitry and a first subset of the set of values or a batch normalization operation using a second sub-circuit of the neural network operation circuitry and a second subset of the set of values.
Inventor(s): Jian WANG of Sugar Land TX (US) for texas instruments incorporated
IPC Code(s): G06F13/42, G06F15/78
CPC Code(s): G06F13/4295
Abstract: a system timer bus used by the processor elements in systems, such as an arm-based system on a chip (soc), is driven using a precision time measurement (ptm) value. this allows the processor elements to be synchronized to the pcie ports that use ptm. when two socs are connected using pcie links, this example allows the processor elements in both socs to be synchronized. as the processor elements are synchronized, associated tasks on the two socs are synchronized, so that overall operations are synchronized.
Inventor(s): Makoto SHIBUYA of Tokyo (JP) for texas instruments incorporated, Shoichi IRIGUCHI of Beppu-Shi Oita-Ken (JP) for texas instruments incorporated, Hideaki MATSUNAGA of Beppu-Shi Oita-Ken (JP) for texas instruments incorporated
IPC Code(s): H01L23/31, H01L21/56, H01L23/00, H01L23/495
CPC Code(s): H01L23/3107
Abstract: in examples, a semiconductor package comprises a semiconductor die having a device side in which circuitry is formed, and a conductive terminal coupled to the device side of the semiconductor die. the package also comprises a mold compound covering the semiconductor die and at least part of the conductive terminal, where the conductive terminal is exposed to an exterior of the mold compound. the mold compound has top and bottom surfaces and a lateral side extending between the top and bottom surfaces. the lateral side includes a first surface contacting the top surface and extending vertically from the top surface toward the bottom surface. the lateral side also includes a second surface contacting the first surface and extending horizontally away from the semiconductor die. the lateral side also includes a third surface contacting the second surface and extending from the second surface to contact the bottom surface. the third surface has physical marks resulting from a singulation process. the first and second surfaces lack physical marks resulting from the singulation process.
Inventor(s): Woochan KIM of San Jose CA (US) for texas instruments incorporated, Ashok PRABHU of San Jose CA (US) for texas instruments incorporated
IPC Code(s): H01L23/373, H01L23/00, H01L25/065
CPC Code(s): H01L23/3735
Abstract: in examples, a package comprises a substrate including a conductive member coupled to a conductive terminal, with the conductive terminal exposed to an exterior of the package. the package also includes a first semiconductor die having first device and first non-device sides, with the first device side coupled to the substrate and the first non-device side opposing the first device side, and with the first device side having circuitry formed therein. the package also includes a second semiconductor die having second device and second non-device sides, with the second device side coupled to the substrate and the second non-device side opposing the second device side, and with the second device side having circuitry formed therein. the package also includes first and second adhesive layers contacting the first and second non-device sides, respectively. the package also includes a passivation overcoat (po) layer contacting the first and second adhesive layers, and a semiconductor layer contacting the po layer and exposed to an exterior of the package.
Inventor(s): Makoto Shibuya of Tokyo (JP) for texas instruments incorporated, Kwang-Soo Kim of Sunnyvale CA (US) for texas instruments incorporated, Woochan Kim of San Jose CA (US) for texas instruments incorporated
IPC Code(s): H01L23/495, H01L21/56, H01L23/00, H01L23/31
CPC Code(s): H01L23/49524
Abstract: an electronic device includes a first semiconductor die attached to a first conductive die attach pad and having a first electronic component, a second semiconductor die attached to a second conductive die attach pad and having a second electronic component, a first package structure that encloses the first semiconductor die and a portion of the first die attach pad, a second package structure that encloses the second semiconductor die and a portion of the second die attach pad, and a conductive metal structure that is electrically connected to the first and second electronic components and extends between the first and second package structures, the conductive metal structure exposed outside the first and second package structures.
Inventor(s): John Carlo C. Molina of Limay (PH) for texas instruments incorporated, Connie Esteron of Mabalacat (PH) for texas instruments incorporated, Cesar Bucasas of Tarlac (PH) for texas instruments incorporated
IPC Code(s): H01L23/495, H01L21/56, H01L23/00, H01L23/31
CPC Code(s): H01L23/49575
Abstract: a back side exposed semiconductor die package with a plurality of leads around a perimeter of the semiconductor die package, a semiconductor die electrically coupled to a plurality of the leads, a plurality of mold compound flash suppression trenches on the back side of the semiconductor die and a back side mold compound free zone are described. the plurality of mold compound flash suppression trenches on the back side of the semiconductor die act as a reservoir to prevent mold compound from encroaching on the mold compound free zone on the back side of the semiconductor die. after formation of the semiconductor die package on the lead frame, individual semiconductor die are singulated, and components such as a head sink may subsequently be attached to the mold compound free zone of the semiconductor die.
Inventor(s): John Carlo C. MOLINA of Limay (PH) for texas instruments incorporated, Ruby Ann M. CAMENFORTE of Pampamga (PH) for texas instruments incorporated
IPC Code(s): H01L23/498, H01L21/48, H01L21/56, H01L23/31
CPC Code(s): H01L23/49822
Abstract: in examples, a package comprises a semiconductor die having a device side including circuitry formed therein. the package comprises a substrate facing and coupled to the device side. the substrate includes first and second metal layers. the first metal layer is positioned closer to the device side than the second metal layer and is coupled to the second metal layer by way of a via. at least one of the first and second metal layers has a top surface facing the semiconductor die. the top surface includes a notch etched therein. the substrate also includes a dielectric contacting the notch and at least part of the first and second metal layers and the via. the package includes a mold compound covering the semiconductor die and the substrate. the package includes a lateral surface approximately perpendicular to the first and second metal layers of the substrate. the mold compound, the dielectric, and the second metal layer are exposed to the lateral surface. a segment of the dielectric is positioned between the first metal layer and the lateral surface. the segment of the dielectric contacts the mold compound at the lateral surface.
Inventor(s): Scott Robert Summerfelt of Garland TX (US) for texas instruments incorporated, Thomas Dyer Bonifield of Dallas TX (US) for texas instruments incorporated, Sreeram Subramanyam Nasum of Bangalore (IN) for texas instruments incorporated, Peter Smeys of San Jose CA (US) for texas instruments incorporated, Benjamin Stassen Cook of Los Gatos CA (US) for texas instruments incorporated
IPC Code(s): H01L23/00, H01L21/762, H01L21/78, H01L23/29, H01L23/31, H01L23/64
CPC Code(s): H01L23/564
Abstract: in some examples, a semiconductor device comprises a substrate, a trench, and a layer of a dielectric material. the substrate includes a semiconductor material and has opposing first and second surfaces. the trench extends between the first surface and the second surface, the trench having the dielectric material. the layer of the dielectric material is on the second surface of the substrate and is contiguous with the dielectric material in the trench.
Inventor(s): JOHN CARLO CRUZ MOLINA of Bataan (PH) for texas instruments incorporated, ANICETO RABILAS, JR. of ANGELES (PH) for texas instruments incorporated, RAY FREDRIC DE ASIS of MABALACAT (PH) for texas instruments incorporated
IPC Code(s): H01L23/00, H01L21/56, H01L23/31
CPC Code(s): H01L24/48
Abstract: an electronic device includes a substrate and a die having an active surface disposed on the substrate. bond pads are disposed on the active surface of the die and includes a recess defined in a top surface of the bond pads. ball bonds are disposed in the recess of the bond pads and wire bonds are attached to the ball bonds and to the substrate. a mold compound encapsulates the die, the bond pads, the ball bonds, and the wire bonds. the mold compound covers all but one surface of the substrate, where the one surface not covered faces away from the die.
Inventor(s): Rongwei ZHANG of Plano TX (US) for texas instruments incorporated, Thomas KRONENBERG of Dallas TX (US) for texas instruments incorporated, Jie CHEN of Plano TX (US) for texas instruments incorporated
IPC Code(s): H01L25/065, H01L21/3065, H01L21/56, H01L21/822, H01L23/00, H01L23/31, H01L23/60
CPC Code(s): H01L25/0655
Abstract: in examples, a package comprises first and second dies including first and second diodes, respectively. the package comprises first and second metal contacts coupled to bottom surfaces of the first and second dies, respectively, with the first and second metal contacts exposed to a bottom surface of the package. the package also comprises an isolation layer between the first and second dies and between the first and second metal contacts and a metal layer coupled to top surfaces of the first and second dies. the package also comprises a mold compound covering the first and second dies and the metal layer.
Inventor(s): Giulio Albini of Draper UT (US) for texas instruments incorporated, Jonathan Lane of Sandy UT (US) for texas instruments incorporated
IPC Code(s): H01L25/16, G11C16/08, H01L29/423, H01L29/66, H01L29/788, H10B41/30
CPC Code(s): H01L25/16
Abstract: an integrated circuit (ic) including flash memory and cmos logic circuitry and a method of fabrication thereof is disclosed. the ic comprises a substrate including a first region and a second region, where a flash memory cell gate stack is formed in the first region, a first transistor is formed in the first region and operable at a first voltage level, the first transistor including a gate formed over a first gate oxide layer exclusive of nitridation, and one or more sets of second transistors are formed in the second region, each set operable at a corresponding second voltage level different than the first voltage level and including a corresponding second gate oxide layer having nitridation.
Inventor(s): Shailesh GHOTGALKAR of Bengaluru (IN) for texas instruments incorporated, Mihir Narendra MODY of Bengaluru (IN) for texas instruments incorporated, Ashish VANJARI of Sugar Land TX (US) for texas instruments incorporated, Aravindhan KARUPPIAH of Bengaluru (IN) for texas instruments incorporated, Mohd FAROOQUI of Bengaluru (IN) for texas instruments incorporated, Biju MG of Bengaluru (IN) for texas instruments incorporated, Daniel WU of Plano TX (US) for texas instruments incorporated
IPC Code(s): H02M1/00, H02M1/088, H02M3/00, H02M3/335
CPC Code(s): H02M1/0025
Abstract: a circuit includes a microcontroller having a first terminal and a second terminal. the microcontroller is configured to: receive a signal associated with operation of a power converter at the first terminal; adjust a switch control signal at the second terminal responsive to the signal; measure a frequency of the switch control signal; compare the measured frequency responsive to at least one envelope of a set of envelopes to obtain monitoring results; and perform control operations responsive to the monitoring results.
Inventor(s): Kae WONG of Allen TX (US) for texas instruments incorporated, Rida ASSAAD of Murphy TX (US) for texas instruments incorporated
IPC Code(s): H02M3/158, H02M1/00
CPC Code(s): H02M3/158
Abstract: a circuit includes a sense circuit and a comparator having a first input and a second input, the first input coupled to the sense circuit. the circuit also includes a first transistor having a control terminal and a current terminal, the current terminal coupled to the second input of the comparator and an amplifier having an input and an output, the input coupled too the control terminal of the first transistor. additionally, the circuit includes a second transistor having a control terminal and a current terminal, the control terminal coupled to the output of the amplifier and a capacitor having a terminal coupled to the current terminal of the second transistor and to the input of the amplifier.
Inventor(s): Prathamesh PILANKAR of Mumbai (IN) for texas instruments incorporated, Akhila GUNDAVARAPU of Bangalore (IN) for texas instruments incorporated, Dipankar MANDAL of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03B5/04
CPC Code(s): H03B5/04
Abstract: in an example, a system includes a first transistor having a first terminal coupled to a current mirror and a control terminal coupled to a first current source and a resistor. the system includes a second transistor having a first terminal coupled to the current mirror, a second terminal coupled to a second terminal of the first transistor, and a control terminal coupled to the resistor and a second current source. the system includes a third transistor having a first terminal coupled to a voltage terminal, a second terminal coupled to the control terminal of the second transistor, and a control terminal coupled to the first terminal of the second transistor. the system includes a fourth transistor having a control terminal coupled to the current mirror, first and second terminals coupled to one another and to the second terminal of the first transistor.
Inventor(s): Debapriya Sahu of Bangalore (IN) for texas instruments incorporated, Radhika Juluri of Bangalore (IN) for texas instruments incorporated, Meghna Agrawal of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03F3/24, H03F1/08, H04B1/04
CPC Code(s): H03F3/245
Abstract: embodiments disclosed herein relate to impedance matching for outputting wide-band signals in radio frequency applications. in an example, a circuit including a low-noise amplifier (lna) sub-circuit and a tuning sub-circuit is provided. the lna sub-circuit is configured to couple to an antenna and includes a transistor that includes a gate, a source, and a drain, a first inductor that includes a first terminal configured to couple to the antenna and includes a second terminal, a second inductor that includes a first terminal coupled to the first terminal of the first inductor and includes a second terminal coupled to the gate of the transistor, and a third inductor that includes a first terminal coupled to the source of the transistor and includes a second terminal. the tuning sub-circuit is coupled to the source of the transistor.
Inventor(s): Sreenath Puthumana of Bangalore (IN) for texas instruments incorporated, Ganapathi Shankar of Bangalore (IN) for texas instruments incorporated, Venkata Naresh Kotikelapudi of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03K3/017, H01F7/06
CPC Code(s): H03K3/017
Abstract: a circuit includes an amplifier having a first input, a reference input, and an output. a pulse width modulator (pwm) controller has an input coupled to the output of the amplifier. a first switch has a control terminal coupled to an output of the pwm controller. a second switch has a second terminal coupled to the second terminal of the first switch, and has a control terminal coupled to the output of the pwm controller. an input of a current sensor is coupled to the second terminal of the first switch and is coupled to a second terminal of the second switch. an output of the current sensor is coupled to the first input of the amplifier. a duty cycle monitoring and reference signal adjustment circuit has an input coupled to the output of the pwm controller and has an output coupled to the reference input of the amplifier.
20250080093. SYNCHRONIZER FLIP-FLOP CIRCUIT_simplified_abstract_(texas instruments incorporated)
Inventor(s): Arnab Khawas of Bangalore (IN) for texas instruments incorporated, Gokul Sabada of Bangalore (IN) for texas instruments incorporated, Badarish Subbannavar of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03K3/3562, H03K3/012, H03K3/037
CPC Code(s): H03K3/35625
Abstract: embodiments disclosed herein relate to synchronizing signals across multiple independent clock domains. in an example, a synchronizer flip-flop circuit is provided. the synchronizer flip-flop circuit includes a first latch sub-circuit coupled to receive an input and a second latch sub-circuit coupled to the first latch sub-circuit. the first latch sub-circuit includes a first group of inverters, a first diode-connected transistor coupled in parallel to each inverter of the first group of inverters and configured to provide a first bias voltage to each inverter of the first group of inverters, and a second diode-connected transistor coupled in parallel to each inverter of the first group of inverters and configured to provide a second bias voltage to each inverter of the first group of inverters.
Inventor(s): Sovan Ghosh of Bengaluru (IN) for texas instruments incorporated, Visvesvaraya Appala Pentakota of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03K5/01, H03M1/12
CPC Code(s): H03K5/01
Abstract: an example apparatus includes programmable circuitry configured to: provide a sample signal, a time amplification (ta) signal, and a kick signal to sample and conversion circuitry; sample a differential signal for a first amount of time-based on the sample signal; charge a first capacitor for a second amount of time-based on the first kick signal; after the first amount of time and the second amount of time, charge a second capacitor, the charging based on the first ta signal, the charging to cause a falling edge in a first delay signal; and generating, a rising edge in the delay signal based on the falling edge of o_rst signal.
Inventor(s): Michael Lueders of Freising (DE) for texas instruments incorporated, Jerrin James of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03K17/06, H03K17/10
CPC Code(s): H03K17/063
Abstract: an apparatus includes a first transistor having a first transistor control terminal and coupled between a power terminal and a switching terminal. the apparatus further includes a second transistor having a second transistor control terminal and coupled between the switching terminal and a ground terminal. the apparatus further includes a first switch coupled between the power terminal and the second transistor control terminal, the first switch having a first switch control terminal; the apparatus further includes a second switch coupled between the second control terminal and the ground terminal, the second switch having a second switch control terminal. the apparatus also includes a controller having a control input, a first control output, and a second control output, the control input coupled to the second transistor control terminal, the first control output coupled to the first switch control terminal, and the second control output coupled to the second switch control terminal.
20250080102. POWER TRANSISTOR CLAMP CIRCUIT_simplified_abstract_(texas instruments incorporated)
Inventor(s): Taisuke Kazama of Plano TX (US) for texas instruments incorporated, Mustapha El-Markhi of Richardson TX (US) for texas instruments incorporated, Avadhut Junnarkar of McKinney TX (US) for texas instruments incorporated
IPC Code(s): H03K17/082, H02H9/04, H02M1/14, H02M3/156, H03K17/687
CPC Code(s): H03K17/0822
Abstract: described embodiments include a voltage clamping circuit having a threshold-setting circuit with a threshold input and a threshold output. a switch has a first terminal coupled to the threshold input, a second switch terminal, and a switch control terminal. a first transistor is coupled between the threshold output and the switch control terminal, and has a first control terminal. a second transistor is coupled between the first control terminal and ground, and has a second control terminal. a first driver circuit has a first driver input and a first driver output. a second driver circuit has a second driver input coupled to the first driver input, and a second driver output. a third transistor is coupled between the threshold input and ground, and has a third control terminal that is coupled to the second control terminal and the second switch terminal.
20250080108. High Voltage Converter Power Stage_simplified_abstract_(texas instruments incorporated)
Inventor(s): Ahmed Essam Hashim of GILBERT AZ (US) for texas instruments incorporated, Kevin Scoones of SAN JOSE CA (US) for texas instruments incorporated
IPC Code(s): H03K17/687, H02M3/158, H03K17/22
CPC Code(s): H03K17/687
Abstract: described embodiments include a power driver circuit having a first transistor coupled between an input voltage terminal and an intermediate terminal, and having a first control terminal. a second transistor is coupled between the intermediate terminal and a switching terminal, and has a second control terminal coupled to an output of a gate drive circuit. a first diode has a first anode coupled to the input voltage terminal, and a first cathode coupled to the first control terminal through a resistor. a first voltage clamp circuit is coupled between the first control terminal and the intermediate terminal. a second voltage clamp circuit is coupled between the first control terminal and the switching terminal. a second diode is coupled between the first control terminal and a voltage supply terminal.
Inventor(s): Robert Taft of Munich (DE) for texas instruments incorporated, Alexander Bodem of Freising (DE) for texas instruments incorporated, Filip Savic of Munich (DE) for texas instruments incorporated, Paul Kramer of Timnath CO (US) for texas instruments incorporated, Vineethraj Rajappan Nair of Freising (DE) for texas instruments incorporated
IPC Code(s): H03K21/00, H03K19/20
CPC Code(s): H03K21/00
Abstract: an example apparatus includes: first through eighth gated inverters each having inputs and outputs; a first and second inverter each having an input and an output, the output of the first inverter coupled to the input of the second gated inverter, the output of the second inverter coupled to the input of the third gated inverter; the fifth gated inverter coupled to the input of the first gated inverter and the input of the first inverter; the sixth gated inverter coupled to the input of the second inverter and the input of the fourth gated inverter; the seventh gated inverter coupled to the output of the first gated inverter and the output of the third gated inverter; the eighth gated inverter coupled to the output of the second gated inverter and the output of the fourth gated inverter; and a bus-holder circuit between the seventh and eighth gated inverter inputs.
Inventor(s): Marius Moe of Oslo (NO) for texas instruments incorporated, Tarjei Aaberge of Oslo (NO) for texas instruments incorporated
IPC Code(s): H03L7/085, G04F10/00, H03K3/03, H03K5/00, H03K5/14, H03L7/081
CPC Code(s): H03L7/085
Abstract: in described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. the timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. the circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. the phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.
Inventor(s): Deepak Kumar Meher of Bangalore (IN) for texas instruments incorporated, Gautam Salil Nandi of Bangalore (IN) for texas instruments incorporated, Tanmay Neema of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03M1/78, H02M1/08
CPC Code(s): H03M1/785
Abstract: in described examples, an r2r digital-to-analog converter includes multiple arms and a voltage regulator. respective arms include an arm switch with a p-channel mosfet (pfet) switch and an n-channel mosfet (nfet) switch. the voltage regulator includes a differential amplifier, a p-ladder that includes n cascade-coupled pfets and has first and second ends, an n-ladder that includes y�n cascade-coupled nfets and has first and second ends, a first resistor (resistance r), and a second resistor (resistance y�r). the first p-ladder end is coupled to a first terminal of the first resistor. the second terminal of the first resistor is coupled to an input of the differential amplifier and a first terminal of the second resistor. a second terminal of the second resistor is coupled to the first n-ladder end. an output of the differential amplifier is coupled to the second n-ladder end and provides a gate voltage of the nfet switch.
Inventor(s): Christopher BROADHURST of Carp (CA) for texas instruments incorporated, Lucas WEAVER of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H04N5/262, H04N7/18, H04N23/80
CPC Code(s): H04N5/2624
Abstract: a circuit includes a first processor core, a second processor core, and a video processing circuit. the first processor core is configured to program the video processing circuit to: provide a rear view image processing path, and to transfer a rear view image from the rear view image processing path to a surround view image processing path. the second processor core is configured to program the video processing circuit to provide the surround view image processing path, to receive the rear view image from the rear view image processing path, and to provide a surround view image based on the rear view image.
Inventor(s): Mangesh Devidas Sadafale of Nagpur (IN) for texas instruments incorporated
IPC Code(s): H04N19/86, H04N19/117, H04N19/134, H04N19/176, H04N19/186
CPC Code(s): H04N19/86
Abstract: several systems, methods and integrated circuits capable of reducing blocking artifacts in video data are disclosed. in an embodiment, a system for reducing blocking artifacts in video data includes a processing module and a deblocking module. the deblocking module comprises a luma deblocking filter and a chroma deblocking filter configured to filter an edge between adjacent blocks associated with the video data, where a block of the adjacent blocks corresponds to one of a prediction block and a transform block. the processing module is communicatively associated with the deblocking module and is operable to configure at least one filter coefficient corresponding to the chroma deblocking filter based on one or more filter coefficients corresponding to the luma deblocking filter. the processing module is further configured to cause the chroma deblocking filter to filter the edge between the adjacent blocks based on the configured at least one filter coefficient.
Inventor(s): Gang HUA of Katy TX (US) for texas instruments incorporated, Rajasekhar Reddy ALLU of Plano TX (US) for texas instruments incorporated, Mihir Narendra MODY of Bengaluru (IN) for texas instruments incorporated, Niraj NANDAN of Plano TX (US) for texas instruments incorporated, Mayank MANGLA of Allen TX (US) for texas instruments incorporated, Pandy KALIMUTHU of Plano TX (US) for texas instruments incorporated
IPC Code(s): H04N25/611, G06T1/60, G06T3/4015, H04N25/13
CPC Code(s): H04N25/611
Abstract: in an advanced driver-assistance system (adas), raw sensor image processing for a machine vision (mv) application is important. due to different color, e.g., red/green/blue (rgb), color components, being focused by the lens at different locations in image plane, the lateral chromatic aberration phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede mv applications. disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (cac) components. an in-pipeline cac design may be used to perform on-the-fly cac without any out-of-pipeline memory traffic; enable use of wide dynamic range (wdr) sensors; uses bicubic interpolation; support vertical and horizontal chromatic aberration color channel offsets, reduce cac line memory requirements, and support flexible look-up table (lut) down-sampling factors to improve the spatial precision of correction and accommodate popular image sensor resolutions.
20250080918. PIEZOELECTRIC AUDIO DEVICE_simplified_abstract_(texas instruments incorporated)
Inventor(s): Bichoy Bahr of Allen TX (US) for texas instruments incorporated, Udit Rawat of Allen TX (US) for texas instruments incorporated, Mohit Chawla of BANGALORE (IN) for texas instruments incorporated, Yogesh Ramadass of San Jose CA (US) for texas instruments incorporated
IPC Code(s): H04R17/02, H04R17/10, H10N30/063, H10N30/086, H10N30/20, H10N30/87
CPC Code(s): H04R17/02
Abstract: in one example, an apparatus comprises a substrate, a first piezoelectric flap, and a second piezoelectric flap. the substrate has an opening. the first piezoelectric flap has a first end on the substrate and has a first portion extending over a first part of the opening, the first piezoelectric flap including first electrodes, in which the first electrodes extend no more than half of a first length of the first portion. the second piezoelectric flap has a second end on the substrate and has a second portion extending over a second part of the opening, the second piezoelectric flap including second electrodes, in which the second electrodes extend no more than half of a second length of the second portion.
20250080920. PIEZOELECTRIC AUDIO DEVICE_simplified_abstract_(texas instruments incorporated)
Inventor(s): Bichoy Bahr of Allen TX (US) for texas instruments incorporated, Udit Rawat of Dallas TX (US) for texas instruments incorporated, Mohit Chawla of Bangalore (IN) for texas instruments incorporated, Yogesh Ramadass of San Jose CA (US) for texas instruments incorporated
IPC Code(s): H04R17/10, H04R3/04, H04R17/02, H04R29/00, H10N30/50, H10N30/87
CPC Code(s): H04R17/10
Abstract: in one example, an audio device includes a substrate, a first piezoelectric flap, a second piezoelectric flap, a transmit circuit, a first receive circuit, a switch circuit, and a second receive circuit. the substrate has an opening. the first piezoelectric flap has a first end on the substrate and extending over the opening, the first piezoelectric flap having first and second terminals. the second piezoelectric flap has a second end on the substrate and extending over the opening, the second piezoelectric flap spaced from the first piezoelectric flap, the second piezoelectric flap having third and fourth terminals. the transmit circuit has driver outputs. the first receive circuit has first receiver inputs. the switch circuit coupled to the driver outputs and the first receiver inputs, and the first and second terminals. the second receive circuit has second receiver inputs coupled to the third and fourth terminals.
20250080952. INTEGRATED WI-FI LOCATION_simplified_abstract_(texas instruments incorporated)
Inventor(s): Ian James SHERLOCK of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H04W4/029, G06F1/28, G06F9/4401, G06F9/54, H04W84/12
CPC Code(s): H04W4/029
Abstract: an apparatus includes an integrated circuit that includes a microprocessor and a microcontroller unit circuit (mcu) coupled to the microprocessor. the mcu includes a central processing unit (cpu) core and a network processor that implements a wireless interface. the mcu is configured to execute a location application that facilitates a determination of a physical location of the apparatus. the mcu may also be configured to support one or more management functions. the microprocessor sends data to the mcu for wireless transmission by the mcu's wireless interface.
Inventor(s): Arvind Kandhalu Raghu of Plano TX (US) for texas instruments incorporated, Antony James Cave of Syston (GB) for texas instruments incorporated, Ramanuja Vedantham of Allen TX (US) for texas instruments incorporated, Xiaoxi Bruce Zhang of Plano TX (US) for texas instruments incorporated
IPC Code(s): H04W72/12, H04L47/6275, H04L69/18, H04W4/80, H04W28/08, H04W72/0446, H04W72/1263, H04W72/566
CPC Code(s): H04W72/1215
Abstract: a method for concurrent execution of multiple protocols using a single radio of a wireless communication device is provided that includes receiving, in a radio command scheduler, a first radio command from a first protocol stack of a plurality of protocol states executing on the wireless communication device, determining a scheduling policy for the first radio command based on a current state of each protocol stack of the plurality of protocol stacks, and scheduling the first radio command in a radio command queue for the radio based on the scheduling policy, wherein the radio command scheduler uses the radio command queue to schedule radio commands received from the plurality of protocol stacks.
Inventor(s): Jack Qian of Plano TX (US) for texas instruments incorporated, Doug Weiser of Plano TX (US) for texas instruments incorporated, Tamer San of Plano TX (US) for texas instruments incorporated
IPC Code(s): H10B20/25, G11C17/16, G11C17/18
CPC Code(s): H10B20/25
Abstract: an electronic device with a non-volatile memory includes a non-volatile memory (nvm) cell selectively programmable to change a program state from a first state to a second state or to a third state, and may also include a write circuit configured to selectively program the nvm cell to change the program state from the first state to the second state by applying a programming voltage signal to a first source/drain region and to change the program state from the first state to the third state by applying the programming voltage signal to a second source/drain region. a read circuit is configured to identify the program state of the nvm memory cell as one of the first state, the second state, and the third state based on a cell voltage of the non-volatile memory cell.
Inventor(s): Hidetoshi Inoue of Oyama-shi (JP) for texas instruments incorporated, Kenji Otake of NAGANO (JP) for texas instruments incorporated, Sombuddha Chakraborty of Redwood City CA (US) for texas instruments incorporated, Taisuke Kazama of Plano TX (US) for texas instruments incorporated
IPC Code(s): H10N35/00, H01L23/00, H01L23/495, H01L25/065
CPC Code(s): H10D1/20
Abstract: a packaged integrated circuit (ic) includes a package substrate, an electronic device on the package substrate, and metal interconnects coupled between the electronic device and the package substrate. the packaged ic also includes an insulation material on the package substrate and encapsulating the electronic device. the insulation material surrounds the metal interconnects. an inductor is over the electronic device and is coupled to the package substrate. a magnetic material is on the insulation material and encapsulates the inductor. the magnetic material is different from the insulation material.
Inventor(s): Manoj Mehrotra of Plano TX (US) for texas instruments incorporated
IPC Code(s): H01L29/08, H01L21/8234, H01L27/088, H01L29/66
CPC Code(s): H10D62/151
Abstract: the present disclosure generally relates to a semiconductor device having a reduced height gate electrode layer. in an example, a semiconductor device includes a substrate, a gate dielectric layer, a gate electrode layer, a doped source/drain region, and a dielectric layer. the gate dielectric layer is on a surface of the substrate. the gate electrode layer is on the gate dielectric layer. the doped source/drain region is in the substrate and has a metallurgical junction parallel to a plane coplanar with the surface of the substrate. the metallurgical junction extends to a first vertical distance from the surface of the substrate. the gate electrode layer has a top surface that is a second vertical distance away from the surface of the substrate. the second vertical distance is equal to or less than half of the first vertical distance. the dielectric layer is over the substrate and the gate electrode layer.
TEXAS INSTRUMENTS INCORPORATED patent applications on March 6th, 2025
- TEXAS INSTRUMENTS INCORPORATED
- B24B41/06
- B24B7/22
- H01L21/304
- H01L21/683
- H01L21/78
- CPC B24B41/068
- Texas instruments incorporated
- B81B7/00
- B81C1/00
- CPC B81B7/0048
- G01F1/64
- G01F1/002
- CPC G01F1/64
- G01N21/3504
- B81B3/00
- G01J5/08
- G01N21/27
- G01N21/61
- CPC G01N21/3504
- G01R19/00
- CPC G01R19/0038
- G01R35/00
- G01D5/244
- G01D5/245
- G01R33/09
- CPC G01R35/005
- G05F1/575
- G05F3/26
- H03K17/082
- H03K17/10
- H03K17/687
- CPC G05F1/575
- CPC G05F3/262
- G06F1/12
- H03K21/02
- CPC G06F1/12
- G06F1/26
- G06F1/3203
- H03K3/356
- H03K19/0185
- CPC G06F1/263
- G06F9/30
- G06F9/38
- CPC G06F9/30145
- G06F13/42
- G06F15/78
- CPC G06F13/4295
- H01L23/31
- H01L21/56
- H01L23/00
- H01L23/495
- CPC H01L23/3107
- H01L23/373
- H01L25/065
- CPC H01L23/3735
- CPC H01L23/49524
- CPC H01L23/49575
- H01L23/498
- H01L21/48
- CPC H01L23/49822
- H01L21/762
- H01L23/29
- H01L23/64
- CPC H01L23/564
- CPC H01L24/48
- H01L21/3065
- H01L21/822
- H01L23/60
- CPC H01L25/0655
- H01L25/16
- G11C16/08
- H01L29/423
- H01L29/66
- H01L29/788
- H10B41/30
- CPC H01L25/16
- H02M1/00
- H02M1/088
- H02M3/00
- H02M3/335
- CPC H02M1/0025
- H02M3/158
- CPC H02M3/158
- H03B5/04
- CPC H03B5/04
- H03F3/24
- H03F1/08
- H04B1/04
- CPC H03F3/245
- H03K3/017
- H01F7/06
- CPC H03K3/017
- H03K3/3562
- H03K3/012
- H03K3/037
- CPC H03K3/35625
- H03K5/01
- H03M1/12
- CPC H03K5/01
- H03K17/06
- CPC H03K17/063
- H02H9/04
- H02M1/14
- H02M3/156
- CPC H03K17/0822
- H03K17/22
- CPC H03K17/687
- H03K21/00
- H03K19/20
- CPC H03K21/00
- H03L7/085
- G04F10/00
- H03K3/03
- H03K5/00
- H03K5/14
- H03L7/081
- CPC H03L7/085
- H03M1/78
- H02M1/08
- CPC H03M1/785
- H04N5/262
- H04N7/18
- H04N23/80
- CPC H04N5/2624
- H04N19/86
- H04N19/117
- H04N19/134
- H04N19/176
- H04N19/186
- CPC H04N19/86
- H04N25/611
- G06T1/60
- G06T3/4015
- H04N25/13
- CPC H04N25/611
- H04R17/02
- H04R17/10
- H10N30/063
- H10N30/086
- H10N30/20
- H10N30/87
- CPC H04R17/02
- H04R3/04
- H04R29/00
- H10N30/50
- CPC H04R17/10
- H04W4/029
- G06F1/28
- G06F9/4401
- G06F9/54
- H04W84/12
- CPC H04W4/029
- H04W72/12
- H04L47/6275
- H04L69/18
- H04W4/80
- H04W28/08
- H04W72/0446
- H04W72/1263
- H04W72/566
- CPC H04W72/1215
- H10B20/25
- G11C17/16
- G11C17/18
- CPC H10B20/25
- H10N35/00
- CPC H10D1/20
- H01L29/08
- H01L21/8234
- H01L27/088
- CPC H10D62/151
