Micron Technology, Inc. patent applications published on October 26th, 2023

Summary of the patent applications from Micron Technology, Inc. on October 26th, 2023

Micron Technology, Inc. has filed several recent patents related to various technologies and methods in the field of semiconductor devices and memory arrays. These patents involve the creation of apparatuses using different layers of conductive and dielectric materials, the formation of memory arrays with memory cell strings and vertical stacks, the stacking of layers of materials to form electronic devices, the use of cap oxide material in microelectronic devices, the formation of sense lines and cell contacts in semiconductor structures, the assembly of semiconductor devices with multiple layers of a substrate, the generation of physical unclonable functions (PUFs) in memory devices, the deposition of storage node materials in semiconductor structures, and the use of carbon nanofibers (CNFs) for heat dissipation in semiconductor device assemblies.

Notable applications of these patents include:

• Creating apparatuses with memory cell strings and dielectric structures of different widths.
• Organizing memory cells into laterally-spaced memory blocks with vertical stacks.
• Forming electronic devices by stacking layers of materials and adding additional layers on top.
• Using cap oxide material with a different etch rate in microelectronic devices.
• Forming sense lines and cell contacts in semiconductor structures using a combination of polysilicon materials.
• Assembling semiconductor devices with multiple layers of a substrate and exposed bond pads.
• Generating physical unclonable functions (PUFs) in memory devices with encrypted values.
• Depositing storage node materials in semiconductor structures by removing portions of nitride material and depositing silicate material.
• Using carbon nanofibers (CNFs) for heat dissipation in semiconductor device assemblies, with CNFs covered by a molding compound.

Overall, Micron Technology, Inc. has been actively filing patents for various technologies and methods related to semiconductor devices and memory arrays, showcasing their commitment to innovation in the industry.

Patent applications for Micron Technology, Inc. on October 26th, 2023

TRACKING A REFERENCE VOLTAGE AFTER BOOT-UP (17729813)

Main Inventor

Martin Brox

Brief explanation

This abstract describes methods, systems, and devices for tracking a reference voltage (V) after a device is turned on. It explains that a host device or a memory device can determine the temperature of the memory device and use this information to select a reference voltage offset value. This offset value is chosen based on a mapping of temperature values to reference voltage offset values. The reference voltage value associated with the memory device is then adjusted based on the selected offset value. The memory device is operated using this adjusted reference voltage value.

Abstract

Methods, systems, and devices for tracking a reference voltage (also referred to as V) after boot-up are described. For example, a host device or a memory device may determine a temperature value associated with the memory device. The host device or the memory device may select a reference voltage offset value for the memory device based on mapping the temperature value associated with the memory device to a relationship between reference voltage offset values and temperature differential values associated with the memory device. The host device or the memory device may adjust a reference voltage value associated with the memory device based on the reference voltage offset value. The host device, or the memory device, may operate the memory device in accordance with the reference voltage value based on adjusting the reference voltage value.

FAST MODE FOR A MEMORY DEVICE (17051113)

Main Inventor

Minjian Wu

Brief explanation

This abstract describes methods, systems, and devices for a fast mode in a memory device. During the system boot procedure, the memory device is initialized and can operate in multiple modes. The first mode has a set of capabilities, while the second mode includes the same capabilities as the first mode, along with additional capabilities. The memory device performs the initialization in the first mode, which involves delaying certain actions related to the additional capabilities. Once the system boot procedure is finished, the memory device switches to the second mode and can perform the previously delayed action.

Abstract

Methods, systems, and devices for fast mode for a memory device are described. In some examples, a memory device may be initialized during a system boot procedure. The memory device may support multiple modes of operation, including at least a first mode that includes a first set of capabilities, and a second made that includes the first set of capabilities, as well as one or more additional capabilities. The memory device may perform the initialization while operating the memory device according to the first mode, which may include delaying one or more actions associated with the one or more additional capabilities. After the system boot procedure is complete, the memory device may operate according to the second mode, which may include performing an action delayed during the system boot.

Self-Refresh Arbitration (17660192)

Main Inventor

Mark Kalei Hadrick

Brief explanation

The abstract describes a method and apparatus for managing self-refresh operations in a memory system with multiple memory components. An arbiter is used to receive self-refresh request signals from a memory controller and authorize the memory components to enter a self-refresh mode. The arbiter ensures that only a certain number of memory components enter the self-refresh mode at a time to prevent exceeding the power limit. This technology can be used in a Compute Express Link (CXL) memory module.

Abstract

Described apparatuses and methods relate to self-refresh arbitration. In a memory system with multiple memory components, an arbiter is configured to manage the occurrence of self-refresh operations. In aspects, the arbiter can receive one or more self-refresh request signals from at least one memory controller for authorization to command one or more memory components to enter a self-refresh mode. Upon receiving the one or more self-refresh request signals, the arbiter, based on a predetermined configuration, can transmit one or more self-refresh enable signals to the at least one memory controller with authorization to command the one or more memory components to enter the self-refresh mode. The configuration can ensure that fewer than all memory components simultaneously enter the self-refresh mode. In so doing, memory components can perform self-refresh operations without exceeding an instantaneous power threshold. The arbiter can be included in, for instance, a Compute Express Link™ (CXL™) memory module.

Self-Refresh Arbitration (17660195)

Main Inventor

Mark Kalei Hadrick

Brief explanation

The abstract describes a system for managing self-refresh operations in a memory system with multiple memory components. An arbiter is used to receive self-refresh request signals from a memory controller and authorize the memory components to enter a self-refresh mode. The arbiter ensures that not all memory components enter self-refresh mode simultaneously to prevent exceeding the power threshold. This system can be implemented in a Compute Express Link (CXL) memory module.

Abstract

Described apparatuses and methods relate to self-refresh arbitration. In a memory system with multiple memory components, an arbiter is configured to manage the occurrence of self-refresh operations. In aspects, the arbiter can receive one or more self-refresh request signals from at least one memory controller for authorization to command one or more memory components to enter a self-refresh mode. Upon receiving the one or more self-refresh request signals, the arbiter, based on a predetermined configuration, can transmit one or more self-refresh enable signals to the at least one memory controller with authorization to command the one or more memory components to enter the self-refresh mode. The configuration can ensure that fewer than all memory components simultaneously enter the self-refresh mode. In so doing, memory components can perform self-refresh operations without exceeding an instantaneous power threshold. The arbiter can be included in, for instance, a Compute Express Link™ (CXL™) memory module.

READING A MASTER BOOT RECORD FOR A NAMESPACE USING A REGULAR READ OPERATION (17726436)

Main Inventor

Alexei Frolikov

Brief explanation

This abstract describes a system for managing memory devices, specifically NAND flash memory in a solid-state drive. The memory is divided into different sections called namespaces, and one of these namespaces is allocated for use by a host device. The controller of the memory writes master boot record (MBR) data to a specific region assigned to the namespace. When the host device sends read commands for addresses within the namespace, the read circuitry can retrieve either user data or MBR data. This retrieval is done using a regular read operation by the controller, without triggering any hardware exceptions that would slow down the processing by the controller's firmware.

Abstract

Systems, methods, and apparatus related to memory devices. In one approach, a memory (e.g., NAND flash memory of a solid-state drive) is allocated to a namespace for use by a host device. Master boot record (MBR) data is written by a controller of the memory to an MBR region assigned to the namespace. Read circuitry is configured to read either of user data or MBR data in response to read commands received from the host device for addresses in the namespace. The user data or the MBR data is read using a regular read operation of the controller (e.g., without triggering any hardware exceptions that require significantly slower processing by firmware of the controller).

COMMAND BUS IN MEMORY (17700187)

Main Inventor

Frank F. Ross

Brief explanation

The present disclosure describes a system where a memory module can perform different operations in response to a common command. The memory module consists of multiple memory media types that can carry out these operations simultaneously. The system includes memory devices connected to a host through ports, with additional memory devices connected to the first set of memory devices through more ports. Each of these additional memory devices has a controller and can receive commands from the host to perform various operations concurrently.

Abstract

The present disclosure includes apparatuses and methods related to a command bus in memory. A memory module may be equipped with multiple memory media types that are responsive to perform various operations in response to a common command. The operations may be carried out during the same clock cycle in response to the command. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices each coupled to the first number of memory devices via a second number of ports, wherein the second number of memory devices each include a controller, and wherein the first number of memory devices and the second number of memory devices can receive a command from the host to perform the various (e.g., the same or different) operations, sometime concurrently.

TECHNIQUES FOR DATA TRANSFER OPERATIONS (17729837)

Main Inventor

Jotiba Koparde

Brief explanation

This abstract describes methods, systems, and devices for data transfer operations in a memory system. The memory system uses counters to select a source set of memory cells and a destination set of memory cells. The system prioritizes transferring data from a block or page with a lower quantity of read operations to a block or page with a lower quantity of access operations or a slower read duration, respectively. This approach aims to optimize data transfer efficiency within the memory system.

Abstract

Methods, systems, and devices for techniques for data transfer operations are described. A memory system may select a source set of memory cells and a destination set of memory cells using one or more counters corresponding to access operations for the source and the destination. For example, as part of a data transfer operation, the memory system may prioritize transferring data from a block with a lower quantity of read operations to a block with a lower quantity of access operations. In some cases, the memory system may prioritize transferring data from a page with a lower quantity of read operations to a page with a slower read duration.

UNMAP BACKLOG IN A MEMORY SYSTEM (17050334)

Main Inventor

Huachen Li

Brief explanation

The abstract describes methods, systems, and devices for managing unmap commands in a memory system. When a host system sends an unmap command, the memory system acknowledges it and proceeds with unmapping the associated addresses. The memory system may use an unmap backlog table to keep track of the addresses to be unmapped. It also supports prioritization between unmap operations and other access operations like read and write operations.

Abstract

Methods, systems, and devices for unmap backlog in a memory system are described. A memory system may be configured to support receiving an unmap command from a host system and signaling, to the host system, an indication that the unmap command has been processed (e.g., handled, acknowledged). In response to the unmap command, the memory system may proceed with various unmap operations, which may include unmapping at least some of the associated addresses after indicating that the unmap command has been processed. For example, a memory system may implement an unmap backlog table to identify sections of addresses that are to be unmapped (e.g., after indicating that the unmap command has been processed). In some examples, the memory system may support various aspects of prioritization between unmap operations (e.g., background unmap operations) and other access operations such as read operations, write operations, or other access operations.

ENHANCED WRITE PERFORMANCE UTILIZING PROGRAM INTERLEAVE (17727131)

Main Inventor

Daniel J. Hubbard

Brief explanation

The abstract describes a system that consists of a memory sub-system with different types of storage blocks. It includes a cache called single-level cell (SLC) cache, a first storage block called multiple level cell (XLC) storage with a first XLC block, and a second XLC storage with a second XLC block. 

In this system, data is written indirectly to the first XLC storage through the SLC cache in a mode called first XLC write mode. Additionally, data is directly written to the second XLC storage in a mode called second XLC write mode.

The system also includes a processing device that performs various operations. These operations involve receiving data from a host system, initiating a write operation to write the data to both the first and second XLC storages, and causing subsets of the data to be alternatively written to the first XLC block in the first XLC write mode and to the second XLC block in the second XLC write mode using page level interleave.

Abstract

A system includes a memory sub-system including a single-level cell (SLC) cache, a first multiple level cell (XLC) storage including a first XLC block, and a second XLC storage including a second XLC block. Data is indirectly written to the first XLC storage via the SLC cache in a first XLC write mode, and data is directly written to the second XLC storage in a second XLC write mode. The system further includes a processing device to perform operations including receiving data from a host system, in response to receiving the data, initiating a write operation to write the data to the first XLC storage and the second XLC storage, and causing subsets of the data to be alternatively written to the first XLC block in the first XLC write mode and to the second XLC block in the second XLC write mode using page level interleave.

GENERATING COMMAND SNAPSHOTS IN MEMORY DEVICES (18216115)

Main Inventor

Chandra M. Guda

Brief explanation

The abstract describes a system and method involving a processing device connected to a memory device. The processing device receives a command to access memory and, if certain conditions are met, records data related to multiple events that occur while processing the command. If the recorded data is present in a set of registers, write operations on the registers are disabled.

Abstract

Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command; responsive to detecting that the memory access command satisfies a trigger condition, recording, in a set of registers, data associated with a plurality of events performed by processing the memory access command; and responsive to detecting that the set of registers comprises the data, disabling write operations on the set of registers.

METHODS AND SYSTEMS FOR DEVICES WITH SELF-SELECTING BUS DECODER (17184372)

Main Inventor

Harold B Noyes

Brief explanation

The abstract describes a peripheral device that is connected to a controller device. This peripheral device allows the controller device to access memory. The peripheral device is also capable of determining and responding to requests from another device.

Abstract

Disclosed are devices and methods, among which is a device peripheral to a controller device that is used to provide memory access to the controller device. In some embodiments, the device may determine and provide a response of the device to requests from the separate device.

APPARATUSES AND METHODS INCLUDING DICE LATCHES IN A SEMICONDUCTOR DEVICE (18335385)

Main Inventor

Yoshiro Riho

Brief explanation

This abstract describes an apparatus that includes multiple dice latches, control logic, and data input logic. The dice latches store data and are connected in parallel. The control logic receives signals to load and reset the data, and it provides the necessary signals to the dice latches. The data input logic is connected to each dice latch and receives signals to precharge and input data. It then provides the data and its complement to the respective dice latch.

Abstract

According to one or more embodiments, an apparatus comprising a plurality of dice latches, dice latch control logic, and a plurality of data input logic is provided. The dice latches are coupled in parallel and latch respective data. The dice latch control logic receives a load control signal and a reset control signal, provides a reset signal and further provides first and second load signals to the dice latches. The reset signal is based on the reset control signal. The first and second load signals are based on the load control signal and the reset control signal. The data input logic each are coupled to a respective one of the dice latches. Each of the data input logic receives a precharge control signal and respective input data and further provides data and complementary data to the respective one of the dice latches.

Bank-Level Self-Refresh (17660201)

Main Inventor

John Christopher Sancon

Brief explanation

The abstract describes a method and apparatus for implementing a self-refresh operation in a memory device. This self-refresh operation is performed on a specific set of banks within the memory device, rather than all of the banks. By doing this, the peak current in the power distribution network of the memory device is limited, which reduces the complexity and cost of the power distribution network. This bank-level self-refresh can be used in memory expansion environments and can be implemented with different types of refresh operations.

Abstract

Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include a controller with logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

Bank-Level Self-Refresh (17660199)

Main Inventor

John Christopher Sancon

Brief explanation

The abstract describes a method and apparatus for implementing a self-refresh operation in a memory device. This self-refresh operation is performed on a specific set of banks within the memory device, rather than on all banks. By selectively choosing which banks to perform the self-refresh operation on, the peak current in the power distribution network of the memory device can be controlled. This allows for the use of a less complex power distribution network, reducing the cost of the memory device. The bank-level self-refresh can also be used in memory-expansion environments and can be implemented with different types of refresh operations.

Abstract

Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17727487)

Main Inventor

Jordan D. Greenlee

Brief explanation

The abstract describes a method for creating a memory array using a stack of memory cells. The stack is made up of alternating tiers, with a conductor tier containing silicon material at the bottom. The stack also includes memory-block regions and a through-array-via (TAV) region. The memory cells are made up of channel-material strings that pass through the tiers in the memory-block regions. The TAV region has openings that extend to the silicon material in the conductor tier. A metal halide is used to react with the silicon, depositing metal in the conductor tier. Then, conductive material is formed in the TAV openings, creating a TAV that consists of the conductive material and the deposited metal. The abstract also mentions that there are various structure embodiments of this method.

Abstract

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers directly above a conductor tier that comprises silicon-containing material. The stack comprises laterally-spaced memory-block regions and a through-array-via (TAV) region. The stack comprises channel-material strings that extend through the first tiers and the second tiers in the memory-block regions. The stack comprises TAV openings in the TAV region that extend to the silicon-containing material of the conductor tier. A metal halide is reacted with the silicon of the silicon-containing material to deposit the metal of the metal halide in the conductor tier. After depositing the metal, conductive material is formed in the TAV openings directly against the deposited metal and therefrom a TAV is formed in individual of the TAV openings that comprises the conductive material and the deposited metal. Structure embodiments are disclosed.

Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17727515)

Main Inventor

Alyssa N. Scarbrough

Brief explanation

The abstract describes a memory array that consists of strings of memory cells. These memory cells are organized into laterally-spaced memory blocks, each containing a vertical stack. The stack is made up of alternating insulative tiers and conductive tiers, with a conductor tier at the bottom. The memory cells are connected to the conductor material through channel-material strings that run through the insulative and conductive tiers. Below the stack, there is an insulating tier followed by a metal-material tier. Conductive rings pass through these tiers and connect to the conductor material. Each conductive ring corresponds to a specific horizontal location above which a channel-material string is located. The channel-material strings are electrically coupled to the conductor material through the insulating tier by the conductive rings. The abstract also mentions that there are other embodiments and methods disclosed.

Abstract

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. Below the stack, an insulating tier is directly above the conductor tier and a metal-material tier is directly above the insulating tier. Conductive rings extend through the metal-material tier and the insulating tier to conductor material of the conductor tier. The conductive rings individually are around individual horizontal locations directly above which are individual of the channel-material strings. The channel-material strings directly electrically couple to the conductor material of the conductor tier through the insulating tier by the conductive rings. Other embodiments, including method, are disclosed.

MEMORY DEVICE WEAR LEVELING (17659897)

Main Inventor

Rainer Frank BONITZ

Brief explanation

The abstract describes a method for managing the wear and tear of memory blocks in a memory device. The controller of the device monitors an endurance parameter associated with a group of memory blocks called the wear leveling pool. If the endurance parameter meets a certain threshold, the controller divides the memory blocks into two subsets. The first subset is used to store a portion of the data, while the second subset is used to store another portion of the data. This helps to evenly distribute the usage of memory blocks and prolong the overall lifespan of the memory device.

Abstract

A controller of a memory device may determine that an endurance parameter associated with a wear leveling pool of a memory of the memory device satisfies a threshold. The wear leveling pool includes a plurality of memory blocks of the memory. The controller may divide, based on determining that the endurance parameter satisfies the threshold, the plurality of memory blocks of the wear leveling pool into a first wear leveling pool subset that includes a first subset of the plurality of memory blocks and a second wear leveling pool subset that includes a second subset of the plurality of memory blocks. A first subset of a plurality of data partitions is stored in the first subset of the plurality of memory blocks, and a second subset of the plurality of data partitions is stored in the second subset of the plurality of memory blocks.

Burst Indicator Systems and Methods (17725025)

Main Inventor

Kai Wang

Brief explanation

The abstract describes systems and methods for filtering data signals. These systems and methods involve using a memory in a training mode to send a command to a decoder. The decoder then generates a command/address waveform in response to the command. Additionally, a burst indicator waveform is transmitted through a pin of the memory. This burst indicator waveform is generated by a burst indicator generator in the memory, based on the command/address waveform.

Abstract

Systems and methods for filtering data (DQ) signals are described herein. The systems and methods may involve operating a memory to enter a training mode and sending a command to a decoder while the memory is in the training mode. The decoder may generate a command/address waveform in response to the command. The systems and methods may involve transmitting a burst indicator waveform via a first pin of the memory. The burst indicator waveform may be generated by a burst indicator generator of the memory based on the command/address waveform.

INDICATING A BLOCKED REPAIR OPERATION (17726139)

Main Inventor

Seth A. Eichmeyer

Brief explanation

This abstract describes methods, systems, and devices that indicate whether a repair operation for a memory device is blocked or not. It involves storing an initial indication of the validity of a memory address. Then, a command to access the address is processed, and a second indication of the address's validity is obtained based on this processing. Using both the first and second indications, a decision is made on whether to proceed with or prevent the repair operation for that address. Finally, a third indication is stored to indicate whether the repair operation was actually performed or prevented.

Abstract

Methods, systems, and devices for indicating a blocked repair operation are described. A first indication of whether an address of a memory device is valid may be stored. After the first indication is stored, a command for accessing the address may be processed. Based on processing the command, a second indication of whether the address is valid may be obtained, and a determination of whether to perform or prevent a repair operation for repairing the address may be made based on the first indication and the second indication. A third indication of whether the repair operation was performed or prevented may be stored.

METHODS AND APPARATUS FOR INTEGRATING CARBON NANOFIBER INTO SEMICONDUCTOR DEVICES USING W2W FUSION BONDING (17728586)

Main Inventor

Wei Zhou

Brief explanation

The abstract describes a semiconductor device assembly that uses carbon nanofibers (CNFs) to dissipate heat. The CNFs are covered with a molding compound to create an encapsulated layer. The molding compound fills the spaces between the individual CNFs, but the upper edges of some CNFs are exposed on the top surface of the encapsulated layer. The top surface of the CNF layer can be easily removed and attached to a carrier wafer.

Abstract

A semiconductor device assembly that includes carbon nanofibers (CNFs) for heat dissipation has a CNF layer. Molding compound encapsulates the CNF layer to form an encapsulated CNF layer. The molding compound extends between individual adjacent CNFs within the encapsulated CNF layer, and upper edges of at least a portion of individual CNFs within the encapsulated CNF layer are exposed along an upper surface of the encapsulated CNF layer. The upper surface of the CNF layer is removably attached to a bottom surface of a carrier wafer.

METHODS AND APPARATUS FOR INTEGRATING CARBON NANOFIBER INTO SEMICONDUCTOR DEVICES USING W2W FUSION BONDING (17728625)

Main Inventor

Wei Zhou

Brief explanation

The abstract describes a semiconductor device assembly that uses carbon nanofibers (CNFs) to dissipate heat. The CNFs are covered with a molding compound to create an encapsulated layer. The molding compound fills the spaces between individual CNFs, but the upper edges of some CNFs are still visible on the surface. The CNF layer is attached to a carrier wafer.

Abstract

A semiconductor device assembly that includes carbon nanofibers (CNFs) for heat dissipation has a CNF layer. Molding compound encapsulates the CNF layer to form an encapsulated CNF layer. The molding compound extends between individual adjacent CNFs within the encapsulated CNF layer, and upper edges of at least a portion of individual CNFs within the encapsulated CNF layer are exposed along an upper surface of the encapsulated CNF layer. The upper surface of the CNF layer is removably attached to a bottom surface of a carrier wafer.

DEPOSITING A STORAGE NODE (17726965)

Main Inventor

Ryan L. Meyer

Brief explanation

The abstract describes methods, apparatuses, and systems for depositing a storage node material. It explains that a semiconductor structure is formed, consisting of various layers such as silicate and nitride materials. Portions of the second nitride material are then removed, and a third silicate material is deposited over the remaining layers. An opening is formed through the semiconductor structure, and a storage node material is deposited within this opening.

Abstract

Methods, apparatuses, and systems related to depositing a storage node material are described. An example method includes forming a semiconductor structure including a support structure having a first silicate material over a bottom nitride material, a first nitride material over the first silicate material, a second silicate material over the first nitride material, and a second nitride material over the second silicate material. The method further includes removing portions of the second nitride material. The method further includes depositing a third silicate material over the second nitride material and a portion of the second silicate material. The method further includes forming an opening through the semiconductor structure. The method further includes depositing a storage node material within the opening.

PHYSICAL UNCLONABLE FUNCTION FAILURE PROTECTION AND PREDICTION (17725178)

Main Inventor

Sourin SARKAR

Brief explanation

This abstract describes a method used by a memory device to generate a unique value called a physical unclonable function (PUF). The memory device stores a protection key for the PUF in a memory region that cannot be accessed by the host. The PUF value is then encrypted using the protection key, resulting in an encrypted PUF value. This encrypted value is stored in various locations within the non-host-addressable memory region.

Abstract

In some implementations, a memory device may generate a physical unclonable function (PUF) value. The memory device may access a PUF protection key stored in a non-host-addressable memory region. The memory device may encrypt the PUF value, using the PUF protection key, to generate an encrypted PUF value. The memory device may store the encrypted PUF value in scattered memory locations in the non-host-addressable memory region.

SURFACE MOUNT DEVICE BONDED TO AN INNER LAYER OF A MULTI-LAYER SUBSTRATE (18215711)

Main Inventor

Kelvin Tan Aik Boo

Brief explanation

The abstract describes an apparatus that consists of multiple layers of a substrate. The primary layer is the outermost layer, followed by a secondary layer with a hole that goes through it to the inner layer. The inner layer is sandwiched between the primary and secondary layers and contains bond pads for components. These bond pads are exposed through the hole in the secondary layer.

Abstract

An apparatus includes a primary layer of a substrate. The apparatus includes a secondary layer of the substrate having a first open area that extends through the secondary layer to an inner layer of the substrate. The apparatus includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes first component bond pads that are disposed on the inner layer and that are exposed via the first open area of the secondary layer.

SENSE LINE AND CELL CONTACT (17729450)

Main Inventor

Kuo-Chen Wang

Brief explanation

The abstract describes various methods, devices, and systems related to a sense line and cell contact in a semiconductor structure. One example device includes two source/drain regions separated by a channel, with a gate opposing the channel. A sense line material is connected to one of the source/drain regions through a cell contact, which is made from a combination of two types of polysilicon materials. Additionally, there is a storage node connected to the other source/drain region.

Abstract

Methods, apparatuses, and systems related to a sense line and cell contact for a semiconductor structure are described. An example apparatus includes a first source/drain region and a second source/drain region, where the first source/drain region and the second source/drain region are separated by a channel, a gate opposing the channel, a sense line material coupled to the first source/drain region by a cell contact, where the cell contact is made from a combination of a first polysilicon material and a second polysilicon material, and a storage node coupled to the second source/drain region.

MICROELECTRONIC DEVICES INCLUDING A SELECTIVELY REMOVABLE CAP DIELECTRIC MATERIAL, METHODS OF FORMING THE MICROELECTRONIC DEVICES, AND RELATED SYSTEMS (17660767)

Main Inventor

Frank Speetjens

Brief explanation

The abstract describes a microelectronic device that consists of layers of different materials, including dielectric and conductive materials. There is also a cap oxide material located above these layers. The device also includes pillars that extend vertically through the layers. The cap oxide material is designed to have a different etch rate compared to the oxide material in the layers. The abstract also mentions that there are other microelectronic devices, systems, and methods of forming such devices that are disclosed in the document.

Abstract

A microelectronic device includes tiers of alternating dielectric and conductive materials, a cap oxide material vertically adjacent to the tiers, and pillars extending vertically through the tiers. The cap oxide material is formulated to exhibit a different etch rate relative to an etch rate of the oxide material of the tiers. Additional microelectronic devices, microelectronic systems, and methods of forming a microelectronic device are also disclosed.

MEMORY APPARATUS AND METHODS INCLUDING MERGED PROCESS FOR MEMORY CELL PILLAR AND SOURCE STRUCTURE (17726968)

Main Inventor

Byeung Chul Kim

Brief explanation

The abstract describes various methods and apparatuses for forming electronic devices. These methods involve stacking layers of materials, creating openings in these layers, filling the openings with dielectric material, and then adding additional layers on top. The process also includes forming pillars, one for a memory cell string and another for a contact structure, which extend through the layers of materials and the openings.

Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the methods includes forming levels of materials one over another; forming a first opening and a second opening in the levels of materials; forming at least one dielectric material in the first and second openings; forming tiers of materials over the levels of materials and over the dielectric material in the first and second openings; forming a first pillar of a memory cell string, the first pillar extending through the tiers of materials and extending partially into a location of the first opening; and forming a second pillar of a contact structure, the second pillar extending through the tiers of materials and through a location of the second opening.

Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17728651)

Main Inventor

Yiping Wang

Brief explanation

The abstract describes a memory array that consists of strings of memory cells. These memory cells are organized into laterally-spaced memory blocks, each containing a vertical stack. The stack is made up of alternating insulative tiers and conductive tiers, with a conductor tier at the bottom. The memory cells are connected to the conductor tier through channel-material strings that pass through the insulative and conductive tiers. The insulative tier directly above the lowest conductive tier is in direct contact with the conductive material. This insulative material can be made of aluminum oxide, hafnium oxide, zirconium oxide, or carbon-doped insulative material. The abstract also mentions that there are other embodiments and methods disclosed.

Abstract

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conductive material of a lowest of the conductive tiers. Insulating material of the insulative tier that is immediately-directly above the lowest conductive tier is directly against a top of the conductive material of the lowest conductive tier. The insulating material comprises at least one of aluminum oxide, hafnium oxide, zirconium oxide, and carbon-doped insulative material. Other embodiments, including method, are disclosed.

MEMORY DEVICE INCLUDING DIFFERENT DIELECTRIC STRUCTURES BETWEEN BLOCKS (18209204)

Main Inventor

Paolo Tessariol

Brief explanation

The abstract describes a technology that involves the creation of apparatuses using different layers of conductive and dielectric materials. These apparatuses contain memory cell strings with pillars that extend through the layers. The apparatus also includes two separate dielectric structures that are formed in slits, which separate the layers and pillars into distinct portions. These dielectric structures have different widths.

Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.