Category:Zhenming Zhou of San Jose CA (US)
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Zhenming Zhou of San Jose CA (US)
Executive Summary
Zhenming Zhou of San Jose CA (US) is an inventor who has filed 21 patents. Their primary areas of innovation include Sensing or reading circuits; Data output circuits (7 patents), Programming or data input circuits (7 patents), Address circuits; Decoders; Word-line control circuits (6 patents), and they have worked with companies such as Micron Technology, Inc. (19 patents), MICRON TECHNOLOGY, INC. (2 patents). Their most frequent collaborators include (12 collaborations), (5 collaborations), (3 collaborations).
Patent Filing Activity
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Technology Areas
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List of Technology Areas
- G11C16/26 (Sensing or reading circuits; Data output circuits): 7 patents
- G11C16/102 (Programming or data input circuits): 7 patents
- G11C16/08 (Address circuits; Decoders; Word-line control circuits): 6 patents
- G11C16/0483 ({comprising cells having several storage transistors connected in series}): 5 patents
- G11C16/32 (Timing circuits): 4 patents
- G06F3/0679 ({Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}): 4 patents
- G06F3/0655 ({Replication mechanisms}): 3 patents
- G11C16/3459 ({Circuits or methods to verify correct programming of nonvolatile memory cells}): 3 patents
- G11C16/349 ({Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}): 3 patents
- G06F3/0604 (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}): 2 patents
- G06F3/0616 ({in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]}): 2 patents
- G11C29/52 (STATIC STORES (semiconductor memory devices): 2 patents
- G06F3/0619 ({in relation to data integrity, e.g. data losses, bit errors}): 2 patents
- G11C16/10 (Programming or data input circuits): 2 patents
- G06F3/0659 ({Command handling arrangements, e.g. command buffers, queues, command scheduling}): 2 patents
- G11C16/3418 (STATIC STORES (semiconductor memory devices): 2 patents
- G11C16/24 (Bit-line control circuits): 2 patents
- G06F3/064 ({Management of blocks}): 1 patents
- G06F3/0629 ({Configuration or reconfiguration of storage systems}): 1 patents
- G06F3/061 (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}): 1 patents
- G06F3/0614 ({Improving the reliability of storage systems}): 1 patents
- G06F3/0683 ({Plurality of storage devices}): 1 patents
- G06F11/3037 (Monitoring): 1 patents
- G11C7/1063 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
- G06F3/0644 ({Management of space entities, e.g. partitions, extents, pools}): 1 patents
- G06F3/0673 ({Single storage device}): 1 patents
- G11C16/12 (Programming voltage switching circuits): 1 patents
- G06F3/0653 ({Monitoring storage devices or systems}): 1 patents
- G11C11/5642 ({Sensing or reading circuits; Data output circuits}): 1 patents
- G11C16/3431 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C29/12005 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C16/3404 ({Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells}): 1 patents
Companies
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List of Companies
- Micron Technology, Inc.: 19 patents
- MICRON TECHNOLOGY, INC.: 2 patents
Collaborators
- Yu-Chung Lien of San Jose CA (US) (12 collaborations)
- Murong Lang of San Jose CA (US) (5 collaborations)
- Jun Wan of San Jose CA (US) (3 collaborations)
- Jiangli Zhu of San Jose CA (US) (3 collaborations)
- Tingjun Xie of Milpitas CA (US) (3 collaborations)
- Christina Papagianni of San Jose CA (US) (2 collaborations)
- Ting Luo of Santa Clara CA (US) (2 collaborations)
- Peng Zhang of Los Altos CA (US) (2 collaborations)
- Ying Yu Tai of Mountain View CA (US) (2 collaborations)
- Zhongguang Xu of San Jose CA (US) (2 collaborations)
- Daniel Zhang of Milpitas CA (US) (1 collaborations)
- Seungjune Jeon of Santa Clara CA (US) (1 collaborations)
- Shyam Sunder Raghunathan (1 collaborations)
- Aaron Lee of Sunnyvale CA (US) (1 collaborations)
- Jian Huang of Union City CA (US) (1 collaborations)
- Huai-Yuan Tseng of San Ramon CA (US) (1 collaborations)
- Tomer Tzvi Eliash of Sunnyvale CA (US) (1 collaborations)
- Zhenlei Shen of Milpitas CA (US) (1 collaborations)
- Charles See Yeung Kwong of Redwood City CA (US) (1 collaborations)
- John Paul Aglubat of Meridian ID (US) (1 collaborations)
- Nagendra Prasad Ganesh Rao of Folsom CA (US) (1 collaborations)
- Paing Htet of Union City CA (US) (1 collaborations)
- Ching-Huang Lu of Fremont CA (US) (1 collaborations)
- Fangfang Zhu of Boise ID (US) (1 collaborations)
- Hanping Chen of San Jose CA (US) (1 collaborations)
Subcategories
This category has the following 3 subcategories, out of 3 total.
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Pages in category "Zhenming Zhou of San Jose CA (US)"
The following 103 pages are in this category, out of 103 total.
1
- 17819826. DETECTING A MEMORY WRITE RELIABILITY RISK WITHOUT USING A WRITE VERIFY OPERATION simplified abstract (Micron Technology, Inc.)
- 17823191. PARTIAL BLOCK READ VOLTAGE OFFSET simplified abstract (Micron Technology, Inc.)
- 17830625. ADAPTIVE ENHANCED CORRECTIVE READ BASED ON WRITE AND READ TEMPERATURE simplified abstract (Micron Technology, Inc.)
- 17830802. DYNAMIC READ LEVEL TRIM SELECTION FOR SCAN OPERATIONS OF MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 17842278. ERROR AVOIDANCE FOR PARTIALLY PROGRAMMED BLOCKS OF A MEMORY DEVICE simplified abstract (Micron Technology, Inc.)
- 17858731. ADAPTIVE WEAR LEVELING FOR ENDURANCE COMPENSATION simplified abstract (Micron Technology, Inc.)
- 17874828. RELIABILITY BASED DATA VERIFICATION simplified abstract (Micron Technology, Inc.)
- 17876346. MEMORY CELL VOLTAGE LEVEL SELECTION simplified abstract (Micron Technology, Inc.)
- 17887244. VOLTAGE WINDOW ADJUSTMENT simplified abstract (Micron Technology, Inc.)
- 17887348. INDEPENDENT SENSING TIMES simplified abstract (Micron Technology, Inc.)
- 17888080. ADAPTIVE BITLINE VOLTAGE FOR MEMORY OPERATIONS simplified abstract (Micron Technology, Inc.)
- 17888171. ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS simplified abstract (Micron Technology, Inc.)
- 17888225. ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS simplified abstract (Micron Technology, Inc.)
- 17894528. ADAPTIVE ERROR AVOIDANCE IN THE MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 17897183. PROXIMITY BASED PARITY DATA MANAGEMENT simplified abstract (Micron Technology, Inc.)
- 17897184. PADDING IN FLASH MEMORY BLOCKS simplified abstract (Micron Technology, Inc.)
- 17898043. NAND DETECT EMPTY PAGE SCAN simplified abstract (Micron Technology, Inc.)
- 17938153. APPARATUS WITH READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE SAME simplified abstract (Micron Technology, Inc.)
- 17938307. APPARATUS WITH READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE SAME simplified abstract (Micron Technology, Inc.)
- 17942977. READ LEVEL COMPENSATION FOR PARTIALLY PROGRAMMED BLOCKS OF MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 18205083. MEMORY SUB-SYSTEM THRESHOLD VOLTAGE MODIFICATION OPERATIONS simplified abstract (Micron Technology, Inc.)
- 18388342. MANAGING WRITE DISTURB BASED ON IDENTIFICATION OF FREQUENTLY-WRITTEN MEMORY UNITS simplified abstract (Micron Technology, Inc.)
- 18388506. READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME simplified abstract (Micron Technology, Inc.)
- 18402306. MANAGING ALLOCATION OF SUB-BLOCKS IN A MEMORY SUB-SYSTEM simplified abstract (Micron Technology, Inc.)
- 18405049. ELONGATED CAPACITORS IN 3D NAND MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 18406687. DYNAMIC READ RETRY VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM simplified abstract (Micron Technology, Inc.)
- 18406852. PROGRAM PULSE MODIFICATION simplified abstract (Micron Technology, Inc.)
- 18421893. MODIFICATION OF PROGRAM VOLTAGE LEVEL WITH READ OR PROGRAM-VERIFY ADJUSTMENT FOR IMPROVING RELIABILITY IN MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 18425383. SELECTIVE DATA PATTERN WRITE SCRUB FOR A MEMORY SYSTEM simplified abstract (Micron Technology, Inc.)
- 18434616. ADAPTIVE ENHANCED CORRECTIVE READ BASED ON WRITE AND READ TEMPERATURE simplified abstract (Micron Technology, Inc.)
- 18439318. DYNAMIC ERASE OPERATION SELECTION USING ERASE POLICY simplified abstract (Micron Technology, Inc.)
- 18514926. OPTIMIZING DATA RELIABILITY USING ERASE RETENTION simplified abstract (Micron Technology, Inc.)
- 18519248. DYNAMIC READ CALIBRATION simplified abstract (Micron Technology, Inc.)
- 18521458. RELIABILITY GAIN IN MEMORY DEVICES WITH ADAPTIVELY SELECTED ERASE POLICIES simplified abstract (Micron Technology, Inc.)
- 18610770. APPARATUS WITH TIME-BASED READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE SAME simplified abstract (Micron Technology, Inc.)
- 18617430. EMPTY PAGE SCAN OPERATIONS ADJUSTMENT simplified abstract (Micron Technology, Inc.)
- 18662940. ADAPTIVE TIME SENSE PARAMETERS AND OVERDRIVE VOLTAGE PARAMETERS FOR RESPECTIVE GROUPS OF WORDLINES IN A MEMORY SUB-SYSTEM simplified abstract (Micron Technology, Inc.)
- 18663978. ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS simplified abstract (Micron Technology, Inc.)
- 18666063. PROGRAMMING DELAY SCHEME FOR IN A MEMORY SUB-SYSTEM BASED ON MEMORY RELIABILITY simplified abstract (Micron Technology, Inc.)
- 18671855. ADAPTIVE TIME SENSE PARAMETERS AND OVERDRIVE VOLTAGE PARAMETERS FOR WORDLINES AT CORNER TEMPERATURES IN A MEMORY SUB-SYSTEM simplified abstract (Micron Technology, Inc.)
- 18672635. ADAPTIVE WEAR LEVELING FOR ENDURANCE COMPENSATION simplified abstract (Micron Technology, Inc.)
- 18672640. ERROR AVOIDANCE FOR PARTIALLY PROGRAMMED BLOCKS OF A MEMORY DEVICE simplified abstract (Micron Technology, Inc.)
- 18734724. REFRESH OF NEIGHBORING MEMORY CELLS BASED ON READ STATUS simplified abstract (Micron Technology, Inc.)
- 18739769. WORD LINE BASED PROGRAM VOLTAGE ADJUSTMENT (Micron Technology, Inc.)
- 18755062. PERFORMING DATA INTEGRITY CHECKS TO IDENTIFY DEFECTIVE WORDLINES simplified abstract (Micron Technology, Inc.)
- 18757422. SELECTIVE USE OF A WORD LINE MONITORING PROCEDURE FOR RELIABILITY-RISK WORD LINES (Micron Technology, Inc.)
- 18771479. ACCESS LINE VOLTAGE RAMP RATE ADJUSTMENT (Micron Technology, Inc.)
- 18774642. ENHANCING READ WINDOW BUDGET USING READ VERIFY (Micron Technology, Inc.)
- 18779926. MANAGING AN ORDER OF PROGRAMMING OPERATIONS IN A MEMORY SUB-SYSTEM (Micron Technology, Inc.)
- 18784022. ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINES (Micron Technology, Inc.)
- 18784133. RANDOMIZED OR PROGRAM-ERASE-CYCLE- DEPENDENT PROGRAM VERIFY SCHEME (Micron Technology, Inc.)
- 18820480. DETECTING A MEMORY WRITE RELIABILITY RISK WITHOUT USING A WRITE VERIFY OPERATION (Micron Technology, Inc.)
- 18821484. PROXIMITY BASED PARITY DATA MANAGEMENT (Micron Technology, Inc.)
- 18958121. ELIMINATING WRITE DISTURB FOR SYSTEM METADATA IN A MEMORY SUB-SYSTEM (Micron Technology, Inc.)
M
- Micron technology, inc. (20240176496). OPTIMIZING DATA RELIABILITY USING ERASE RETENTION simplified abstract
- Micron technology, inc. (20240176508). RELIABILITY GAIN IN MEMORY DEVICES WITH ADAPTIVELY SELECTED ERASE POLICIES simplified abstract
- Micron technology, inc. (20240177781). READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME simplified abstract
- Micron technology, inc. (20240177795). DYNAMIC READ CALIBRATION simplified abstract
- Micron technology, inc. (20240185924). PASS VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK simplified abstract
- Micron technology, inc. (20240185931). PROGRAM VERIFY COMPENSATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK simplified abstract
- Micron technology, inc. (20240185934). PROGRAM VERIFY COMPENSATION BY SENSING TIME MODULATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK simplified abstract
- Micron technology, inc. (20240185935). BITLINE VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK simplified abstract
- Micron technology, inc. (20240203502). BITLINE VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE simplified abstract
- Micron technology, inc. (20240203503). PROGRAM VERIFY LEVEL ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE simplified abstract
- Micron technology, inc. (20240203504). SENSING TIME ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE simplified abstract
- Micron technology, inc. (20240203513). PASS VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE simplified abstract
- Micron technology, inc. (20240231641). MANAGING ALLOCATION OF SUB-BLOCKS IN A MEMORY SUB-SYSTEM simplified abstract
- Micron technology, inc. (20240231644). APPARATUS WITH TIME-BASED READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE SAME simplified abstract
- Micron technology, inc. (20240231666). EMPTY PAGE SCAN OPERATIONS ADJUSTMENT simplified abstract
- Micron technology, inc. (20240233843). SELECTIVE DATA PATTERN WRITE SCRUB FOR A MEMORY SYSTEM simplified abstract
- Micron technology, inc. (20240241664). ADAPTIVE ENHANCED CORRECTIVE READ BASED ON WRITE AND READ TEMPERATURE simplified abstract
- Micron technology, inc. (20240248612). PROGRAM PULSE MODIFICATION simplified abstract
- Micron technology, inc. (20240248619). DYNAMIC READ RETRY VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM simplified abstract
- Micron technology, inc. (20240249772). ELONGATED CAPACITORS IN 3D NAND MEMORY DEVICES simplified abstract
- Micron technology, inc. (20240256155). MEMORY READ OPERATION USING A VOLTAGE PATTERN BASED ON A READ COMMAND TYPE simplified abstract
- Micron technology, inc. (20240256444). GENERATING VIRTUAL BLOCKS USING PARTIAL GOOD BLOCKS simplified abstract
- Micron technology, inc. (20240281145). DYNAMIC ERASE OPERATION SELECTION USING ERASE POLICY simplified abstract
- Micron technology, inc. (20240290404). GATE VOLTAGE STEP AND PROGRAM VERIFY LEVEL ADJUSTMENT IN A MEMORY DEVICE simplified abstract
- Micron technology, inc. (20240302967). ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS simplified abstract
- Micron technology, inc. (20240304256). PROGRAMMING DELAY SCHEME FOR IN A MEMORY SUB-SYSTEM BASED ON MEMORY RELIABILITY simplified abstract
- Micron technology, inc. (20240311042). ADAPTIVE TIME SENSE PARAMETERS AND OVERDRIVE VOLTAGE PARAMETERS FOR WORDLINES AT CORNER TEMPERATURES IN A MEMORY SUB-SYSTEM simplified abstract
- Micron technology, inc. (20240311311). ERROR AVOIDANCE FOR PARTIALLY PROGRAMMED BLOCKS OF A MEMORY DEVICE simplified abstract
- Micron technology, inc. (20240319881). ADAPTIVE TIME SENSE PARAMETERS AND OVERDRIVE VOLTAGE PARAMETERS FOR RESPECTIVE GROUPS OF WORDLINES IN A MEMORY SUB-SYSTEM simplified abstract
- Micron technology, inc. (20240319886). MODIFICATION OF PROGRAM VOLTAGE LEVEL WITH READ OR PROGRAM-VERIFY ADJUSTMENT FOR IMPROVING RELIABILITY IN MEMORY DEVICES simplified abstract
- Micron technology, inc. (20240320077). ADAPTIVE WEAR LEVELING FOR ENDURANCE COMPENSATION simplified abstract
- Micron technology, inc. (20240321350). REFRESH OF NEIGHBORING MEMORY CELLS BASED ON READ STATUS simplified abstract
- Micron technology, inc. (20240347110). PERFORMING DATA INTEGRITY CHECKS TO IDENTIFY DEFECTIVE WORDLINES simplified abstract
- Micron technology, inc. (20240411449). MANAGING PROGRAMMING OPERATION SEQUENCE IN A MEMORY SUB-SYSTEM
- Micron technology, inc. (20240419543). PROXIMITY BASED PARITY DATA MANAGEMENT
- Micron technology, inc. (20240420783). DETECTING A MEMORY WRITE RELIABILITY RISK WITHOUT USING A WRITE VERIFY OPERATION
- Micron technology, inc. (20240420784). WORD LINE BASED PROGRAM VOLTAGE ADJUSTMENT
- Micron technology, inc. (20250069675). ENHANCING READ WINDOW BUDGET USING READ VERIFY
- Micron technology, inc. (20250085863). MANAGING AN ORDER OF PROGRAMMING OPERATIONS IN A MEMORY SUB-SYSTEM
- Micron technology, inc. (20250086282). RANDOMIZED OR PROGRAM-ERASE-CYCLE- DEPENDENT PROGRAM VERIFY SCHEME
- Micron technology, inc. (20250087277). ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINES
- Micron technology, inc. (20250087278). ELIMINATING WRITE DISTURB FOR SYSTEM METADATA IN A MEMORY SUB-SYSTEM
- Micron technology, inc. (20250087283). ACCESS LINE VOLTAGE RAMP RATE ADJUSTMENT
U
- US Patent Application 17752590. ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM simplified abstract
- US Patent Application 17830625. ADAPTIVE ENHANCED CORRECTIVE READ BASED ON WRITE AND READ TEMPERATURE simplified abstract
- US Patent Application 17830802. DYNAMIC READ LEVEL TRIM SELECTION FOR SCAN OPERATIONS OF MEMORY DEVICES simplified abstract
- US Patent Application 17887244. VOLTAGE WINDOW ADJUSTMENT simplified abstract
- US Patent Application 17938307. APPARATUS WITH READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE SAME simplified abstract
Categories:
- Yu-Chung Lien of San Jose CA (US)
- Murong Lang of San Jose CA (US)
- Jun Wan of San Jose CA (US)
- Jiangli Zhu of San Jose CA (US)
- Tingjun Xie of Milpitas CA (US)
- Christina Papagianni of San Jose CA (US)
- Ting Luo of Santa Clara CA (US)
- Peng Zhang of Los Altos CA (US)
- Ying Yu Tai of Mountain View CA (US)
- Zhongguang Xu of San Jose CA (US)
- Daniel Zhang of Milpitas CA (US)
- Seungjune Jeon of Santa Clara CA (US)
- Shyam Sunder Raghunathan
- Aaron Lee of Sunnyvale CA (US)
- Jian Huang of Union City CA (US)
- Huai-Yuan Tseng of San Ramon CA (US)
- Tomer Tzvi Eliash of Sunnyvale CA (US)
- Zhenlei Shen of Milpitas CA (US)
- Charles See Yeung Kwong of Redwood City CA (US)
- John Paul Aglubat of Meridian ID (US)
- Nagendra Prasad Ganesh Rao of Folsom CA (US)
- Paing Htet of Union City CA (US)
- Ching-Huang Lu of Fremont CA (US)
- Fangfang Zhu of Boise ID (US)
- Hanping Chen of San Jose CA (US)
- Zhenming Zhou of San Jose CA (US)
- Inventors
- Inventors filing patents with Micron Technology, Inc.
- Inventors filing patents with MICRON TECHNOLOGY, INC.