Category:Tony M. Brewer of Plano TX (US)
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Contents
Tony M. Brewer of Plano TX (US)
Executive Summary
Tony M. Brewer of Plano TX (US) is an inventor who has filed 24 patents. Their primary areas of innovation include {Command handling arrangements, e.g. command buffers, queues, command scheduling} (7 patents), {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} (5 patents), using clearing, invalidating or resetting means (4 patents), and they have worked with companies such as Micron Technology, Inc. (24 patents). Their most frequent collaborators include (9 collaborations), (4 collaborations), (2 collaborations).
Patent Filing Activity
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Technology Areas
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List of Technology Areas
- G06F3/0659 ({Command handling arrangements, e.g. command buffers, queues, command scheduling}): 7 patents
- G06F3/0679 ({Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}): 5 patents
- G06F12/0891 (using clearing, invalidating or resetting means): 4 patents
- G06F12/0855 (in hierarchically structured memory systems, e.g. virtual memory systems): 3 patents
- G06F3/0673 ({Single storage device}): 3 patents
- G06F13/4027 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 3 patents
- G06F3/0604 (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}): 3 patents
- G06F9/3877 ({using a slave processor, e.g. coprocessor (peripheral processor): 2 patents
- G06F15/82 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 2 patents
- G06F9/30101 ({Special purpose registers}): 2 patents
- G06F12/0875 (with dedicated cache, e.g. instruction or stack): 2 patents
- G06F9/4881 (Program initiating; Program switching, e.g. by interrupt): 2 patents
- G06F9/542 (Interprogram communication): 2 patents
- G06F2212/452 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 2 patents
- G06F9/3816 ({Instruction alignment, e.g. cache line crossing}): 2 patents
- G06F13/1668 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 2 patents
- G06F3/0616 ({in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]}): 1 patents
- G06F9/3851 ({from multiple instruction streams, e.g. multistreaming}): 1 patents
- G06F15/7889 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F15/80 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L27/0248 ({for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection}): 1 patents
- H01L27/0688 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H10B12/50 (ELECTRONIC MEMORY DEVICES): 1 patents
- G06F9/3836 ({Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}): 1 patents
- G06F9/546 (Interprogram communication): 1 patents
- G06F3/0634 ({by changing the state or mode of one or more devices}): 1 patents
- G06F3/0619 ({in relation to data integrity, e.g. data losses, bit errors}): 1 patents
- G06F3/0631 ({by allocating resources to storage systems}): 1 patents
- G06F3/0644 ({Management of space entities, e.g. partitions, extents, pools}): 1 patents
- G06F3/0656 ({Data buffering arrangements}): 1 patents
- G06F3/0607 ({by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device}): 1 patents
- G06F3/0611 ({in relation to response time}): 1 patents
- G06F3/0658 ({Controller construction arrangements}): 1 patents
- G06F3/0622 ({in relation to access}): 1 patents
- G06F9/3009 ({Thread control instructions}): 1 patents
- G06F12/0238 ({Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}): 1 patents
- G06F12/0833 (in hierarchically structured memory systems, e.g. virtual memory systems): 1 patents
- G06F12/0893 (Caches characterised by their organisation or structure): 1 patents
- G06F9/345 (of multiple operands or results {(addressing multiple banks): 1 patents
- G06F9/3004 ({to perform operations on memory}): 1 patents
- G06F2212/60 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F2212/7209 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F9/5016 (Allocation of resources, e.g. of the central processing unit [CPU]): 1 patents
- G06F9/325 ({for loops, e.g. loop detection or loop counter}): 1 patents
- G06F9/3867 ({using instruction pipelines}): 1 patents
- G06F15/7825 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F7/4981 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F7/4983 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F13/4068 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F15/17375 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F9/30018 ({Bit or string instructions}): 1 patents
- G06F9/30098 ({Register arrangements}): 1 patents
- G06F9/30065 ({Loop control instructions; iterative instructions, e.g. LOOP, REPEAT}): 1 patents
- G06F9/4498 ({Finite state machines}): 1 patents
- G06F9/30087 ({Synchronisation or serialisation instructions}): 1 patents
- G06F15/7867 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F9/3824 ({Operand accessing}): 1 patents
Companies
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List of Companies
- Micron Technology, Inc.: 24 patents
Collaborators
- Dean E. Walker of Allen TX (US) (9 collaborations)
- Michael Keith Dugan of Richardson TX (US) (4 collaborations)
- Christopher Baronne of Allen TX (US) (2 collaborations)
- Douglas Vanesko of Dallas TX (US) (1 collaborations)
- Bryan Hornung of Plano TX (US) (1 collaborations)
Subcategories
This category has only the following subcategory.
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Pages in category "Tony M. Brewer of Plano TX (US)"
The following 28 pages are in this category, out of 28 total.
1
- 17823307. EVICTING A CACHE LINE WITH PENDING CONTROL REQUEST simplified abstract (Micron Technology, Inc.)
- 17823314. HOST-PREFERRED MEMORY OPERATION simplified abstract (Micron Technology, Inc.)
- 17823323. MEMORY SIDE CACHE REQUEST HANDLING simplified abstract (Micron Technology, Inc.)
- 17823391. MEMORY-SIDE CACHE DIRECTORY-BASED REQUEST QUEUE simplified abstract (Micron Technology, Inc.)
- 17823408. SILENT CACHE LINE EVICTION simplified abstract (Micron Technology, Inc.)
- 17823462. METHOD OF SUBMITTING WORK TO FABRIC ATTACHED MEMORY simplified abstract (Micron Technology, Inc.)
- 17823468. QUEUEING ASYNCHRONOUS EVENTS FOR ACCEPTANCE BY THREADS EXECUTING IN A BARREL PROCESSOR simplified abstract (Micron Technology, Inc.)
- 17823470. METHOD OF EFFICIENTLY IDENTIFYING ROLLBACK REQUESTS simplified abstract (Micron Technology, Inc.)
- 17898803. CONTROL PARAMETER ADDRESS VIRTUALIZATION simplified abstract (Micron Technology, Inc.)
- 17898929. ACCESS REQUEST REORDERING ACROSS A MULTIPLE-CHANNEL INTERFACE FOR MEMORY-BASED COMMUNICATION QUEUES simplified abstract (Micron Technology, Inc.)
- 17899016. ACCESS REQUEST REORDERING FOR MEMORY-BASED COMMUNICATION QUEUES simplified abstract (Micron Technology, Inc.)
- 17899171. RECALL PENDING CACHE LINE EVICTION simplified abstract (Micron Technology, Inc.)
- 17899184. VARIABLE EXECUTION TIME ATOMIC OPERATIONS simplified abstract (Micron Technology, Inc.)
- 17899197. SYNCHRONIZED REQUEST HANDLING AT A MEMORY DEVICE simplified abstract (Micron Technology, Inc.)
- 18386880. Multi-Threaded, Self-Scheduling Processor simplified abstract (Micron Technology, Inc.)
- 18388784. CONNECTIVITY IN COARSE GRAINED RECONFIGURABLE ARCHITECTURE simplified abstract (Micron Technology, Inc.)
- 18412846. System Having a Hybrid Threading Processor, a Hybrid Threading Fabric Having Configurable Computing Elements, and a Hybrid Interconnection Network simplified abstract (Micron Technology, Inc.)
- 18524942. EFFICIENT PROCESSING OF NESTED LOOPS FOR COMPUTING DEVICE WITH MULTIPLE CONFIGURABLE PROCESSING ELEMENTS USING MULTIPLE SPOKE COUNTS simplified abstract (Micron Technology, Inc.)
- 18591718. RECALL PENDING CACHE LINE EVICTION simplified abstract (Micron Technology, Inc.)
- 18596254. Power and Temperature Management for Functional Blocks Implemented by a 3D Stacked Integrated Circuit simplified abstract (Micron Technology, Inc.)
- 18606809. NEAR-MEMORY PSEUDORANDOM NUMBER GENERATION simplified abstract (Micron Technology, Inc.)
- 18618483. VARIABLE EXECUTION TIME ATOMIC OPERATIONS simplified abstract (Micron Technology, Inc.)
- 18815521. 3D STACKED INTEGRATED CIRCUITS HAVING FAILURE MANAGEMENT (Micron Technology, Inc.)
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- Micron technology, inc. (20240248846). RECALL PENDING CACHE LINE EVICTION simplified abstract
- Micron technology, inc. (20240311084). NEAR-MEMORY PSEUDORANDOM NUMBER GENERATION simplified abstract
- Micron technology, inc. (20240311306). VARIABLE EXECUTION TIME ATOMIC OPERATIONS simplified abstract
- Micron technology, inc. (20240421823). 3D STACKED INTEGRATED CIRCUITS HAVING FAILURE MANAGEMENT
