Category:Ruilong Xie of Niskayuna NY (US)

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Ruilong Xie of Niskayuna NY (US)

Executive Summary

Ruilong Xie of Niskayuna NY (US) is an inventor who has filed 64 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (22 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (22 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (21 patents), and they have worked with companies such as International Business Machines Corporation (35 patents), INTERNATIONAL BUSINESS MACHINES CORPORATION (29 patents). Their most frequent collaborators include (20 collaborations), (18 collaborations), (14 collaborations).

Patent Filing Activity

Ruilong Xie of Niskayuna NY (US) Monthly Patent Applications.png

Technology Areas

Ruilong Xie of Niskayuna NY (US) Top Technology Areas.png

List of Technology Areas

  • H01L29/42392 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 22 patents
  • H01L29/775 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 22 patents
  • H01L29/0673 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 21 patents
  • H10D30/6735 (No explanation available): 21 patents
  • H10D62/121 (No explanation available): 20 patents
  • H10D30/43 (No explanation available): 19 patents
  • H10D30/6757 (No explanation available): 16 patents
  • H01L29/78696 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 14 patents
  • H01L29/66439 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 14 patents
  • H10D30/014 (No explanation available): 14 patents
  • H01L27/088 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 13 patents
  • H01L29/66545 ({using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate}): 11 patents
  • H01L23/5286 ({Geometry or} layout of the interconnection structure {(): 11 patents
  • H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 10 patents
  • H01L23/481 (Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor}): 10 patents
  • H10D84/038 (No explanation available): 10 patents
  • H10D30/6729 (No explanation available): 9 patents
  • H10D84/83 (No explanation available): 9 patents
  • H10D64/017 (No explanation available): 8 patents
  • H01L21/823475 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 7 patents
  • H01L21/823807 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 5 patents
  • H01L27/092 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 5 patents
  • H01L21/823481 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 5 patents
  • H10D62/151 (No explanation available): 5 patents
  • H10D84/85 (No explanation available): 5 patents
  • H01L23/5283 ({Geometry or} layout of the interconnection structure {(): 4 patents
  • H01L29/41733 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
  • H01L21/823418 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 4 patents
  • H01L29/0847 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
  • H01L29/41766 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
  • H10D84/013 (No explanation available): 4 patents
  • H10D84/017 (No explanation available): 4 patents
  • H01L21/823412 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 3 patents
  • H01L27/124 (the substrate being other than a semiconductor body, e.g. an insulating body): 3 patents
  • H01L27/1266 (the substrate being other than a semiconductor body, e.g. an insulating body): 3 patents
  • H01L23/564 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
  • H01L23/585 ({comprising conductive layers or plates or strips or rods or rings (): 3 patents
  • H01L23/60 (Protection against electrostatic charges or discharges, e.g. Faraday shields): 3 patents
  • H01L21/76897 ({Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step (self-aligned silicidation on field effect transistors): 3 patents
  • H10D84/0149 (No explanation available): 3 patents
  • H10D84/0128 (No explanation available): 3 patents
  • H10D64/258 (No explanation available): 3 patents
  • H10B10/125 (ELECTRONIC MEMORY DEVICES): 2 patents
  • H01L29/41725 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L21/823468 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 2 patents
  • H01L29/6656 ({using self aligned silicidation, i.e. salicide (formation of conductive layers comprising silicides): 2 patents
  • H01L27/0922 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L21/8221 ({Three dimensional integrated circuits stacked in different levels}): 2 patents
  • H01L21/76804 ({by forming tapered via holes}): 2 patents
  • H01L21/76898 ({formed through a semiconductor substrate}): 2 patents
  • H01L23/528 ({Geometry or} layout of the interconnection structure {(): 2 patents
  • H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L2225/06541 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L23/562 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H10B10/12 (ELECTRONIC MEMORY DEVICES): 2 patents
  • H01L21/823871 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 2 patents
  • H01L21/76224 ({using trench refilling with dielectric materials (trench filling with polycristalline silicon): 2 patents
  • H01L29/401 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L27/0928 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H10D30/024 (No explanation available): 2 patents
  • H10D62/154 (No explanation available): 2 patents
  • H10D62/158 (No explanation available): 2 patents
  • H10D84/811 (No explanation available): 2 patents
  • H10D84/0186 (No explanation available): 2 patents
  • H01L23/5256 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H10D64/256 (No explanation available): 2 patents
  • H10D64/021 (No explanation available): 2 patents
  • H10D64/01 (No explanation available): 2 patents
  • H01L21/76886 ({Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances}): 1 patents
  • H01L21/28123 ({Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects}): 1 patents
  • H01L27/1207 ({combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits}): 1 patents
  • H01L21/823462 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
  • H01L21/84 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/16 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/16227 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2924/14 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/5223 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L21/768 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
  • H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/08145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2924/19041 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/0649 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/66977 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L21/823885 ({with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface (with a current flow parallel to the substrate surface): 1 patents
  • H01L29/66666 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/7827 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L21/76802 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
  • H01L21/76831 ({in via holes or trenches, e.g. non-conductive sidewall liners}): 1 patents
  • H01L21/76885 ({By forming conductive members before deposition of protective insulating material, e.g. pillars, studs}): 1 patents
  • H01L27/0924 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L21/823842 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
  • H01L21/823437 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
  • H01L21/76816 ({Aspects relating to the layout of the pattern or to the size of vias or trenches (layout of the interconnections per se): 1 patents
  • H01L21/823864 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
  • H01L29/66553 ({using self aligned silicidation, i.e. salicide (formation of conductive layers comprising silicides): 1 patents
  • H01L29/0653 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/66 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/49822 ({Multilayer substrates (multilayer metallisation on monolayer substrate): 1 patents
  • H01Q1/2283 ({mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package}): 1 patents
  • H01Q1/50 (Structural association of antennas with earthing switches, lead-in devices or lightning protectors): 1 patents
  • H10D8/00 (No explanation available): 1 patents
  • H01L2223/6616 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2223/6677 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H10D30/6748 (No explanation available): 1 patents
  • H01L21/308 (using masks (): 1 patents
  • H01L27/1255 (the substrate being other than a semiconductor body, e.g. an insulating body): 1 patents
  • H01L27/127 (the substrate being other than a semiconductor body, e.g. an insulating body): 1 patents
  • H01L21/76229 (Dielectric regions {, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers}): 1 patents
  • H01L21/76805 ({the opening being a via or contact hole penetrating the underlying conductor}): 1 patents
  • H01L23/62 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H10D64/251 (No explanation available): 1 patents
  • H01L21/7682 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
  • H01L21/76838 ({characterised by the formation and the after-treatment of the conductors (etching for patterning the conductors): 1 patents
  • H10D84/0179 (No explanation available): 1 patents
  • H10D30/792 (No explanation available): 1 patents
  • H10D64/018 (No explanation available): 1 patents
  • H01L21/02532 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L21/02609 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/5228 ({Resistive arrangements or effects of, or between, wiring layers (other resistive arrangements): 1 patents
  • H10D1/474 (No explanation available): 1 patents
  • H10D86/80 (No explanation available): 1 patents
  • H10D86/01 (No explanation available): 1 patents
  • H10D86/0214 (No explanation available): 1 patents
  • H10D86/481 (No explanation available): 1 patents
  • H10D86/60 (No explanation available): 1 patents
  • H10D87/00 (No explanation available): 1 patents
  • H10D86/421 (No explanation available): 1 patents
  • H01L29/41775 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/0669 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/535 (including internal interconnections, e.g. cross-under constructions {(internal lead connections): 1 patents
  • H10D84/0167 (No explanation available): 1 patents
  • H10D84/856 (No explanation available): 1 patents
  • H10D88/01 (No explanation available): 1 patents
  • G11C11/412 (using field-effect transistors only): 1 patents
  • H10D84/853 (No explanation available): 1 patents
  • H10D30/62 (No explanation available): 1 patents
  • H10D84/0151 (No explanation available): 1 patents
  • H10D84/0158 (No explanation available): 1 patents
  • H10D84/834 (No explanation available): 1 patents
  • H10B80/00 (Assemblies of multiple devices comprising at least one memory device covered by this subclass): 1 patents

Companies

Ruilong Xie of Niskayuna NY (US) Top Companies.png

List of Companies

  • International Business Machines Corporation: 35 patents
  • INTERNATIONAL BUSINESS MACHINES CORPORATION: 29 patents

Collaborators

Subcategories

This category has the following 8 subcategories, out of 8 total.

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C

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N

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Pages in category "Ruilong Xie of Niskayuna NY (US)"

The following 200 pages are in this category, out of 497 total.

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