Category:Kishore Kumar Muchherla of Fremont CA (US)
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Kishore Kumar Muchherla of Fremont CA (US)
Executive Summary
Kishore Kumar Muchherla of Fremont CA (US) is an inventor who has filed 2 patents. Their primary areas of innovation include Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers (1 patents), Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines (1 patents), Word line organisation; Word line lay-out (1 patents), and they have worked with companies such as Micron Technolgy, Inc. (2 patents). Their most frequent collaborators include (1 collaborations), (1 collaborations), (1 collaborations).
Patent Filing Activity
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Technology Areas
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List of Technology Areas
- G11C7/1096 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
- G11C8/08 (Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines): 1 patents
- G11C8/14 (Word line organisation; Word line lay-out): 1 patents
- G11C16/10 (Programming or data input circuits): 1 patents
- G06F3/0655 ({Replication mechanisms}): 1 patents
- G06F3/0604 (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}): 1 patents
- G06F3/0679 ({Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}): 1 patents
- G06F12/02 (Addressing or allocation; Relocation (program address sequencing): 1 patents
Companies
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List of Companies
- Micron Technolgy, Inc.: 2 patents
Collaborators
- Jiangang Wu of Milpitas CA (US) (1 collaborations)
- Lei Zhou (1 collaborations)
- Jung Sheng Hoei of Newark CA (US) (1 collaborations)
- Qisong Lin of El Dorado Hills CA (US) (1 collaborations)
- Karl David Schuh of Santa Cruz CA (US) (1 collaborations)
- Daniel Jerre Hubbard of Boise ID (US) (1 collaborations)
- James Fitzpatrick of Laguna Niguel CA (US) (1 collaborations)
Subcategories
This category has the following 12 subcategories, out of 12 total.
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Pages in category "Kishore Kumar Muchherla of Fremont CA (US)"
The following 33 pages are in this category, out of 33 total.
1
- 17830166. MANAGING QUAD-LEVEL CELL COMPACTION STRATEGY OF A MEMORY DEVICE simplified abstract (Micron Technology, Inc.)
- 17859468. MEMORY COMPACTION MANAGEMENT IN MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 17863000. MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM simplified abstract (Micron Technology, Inc.)
- 17884432. MULTI-LAYER CODE RATE ARCHITECTURE FOR SPECIAL EVENT PROTECTION WITH REDUCED PERFORMANCE PENALTY simplified abstract (Micron Technology, Inc.)
- 17894794. TWO-TIER DEFECT SCAN MANAGEMENT simplified abstract (Micron Technology, Inc.)
- 17895886. READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS simplified abstract (Micron Technology, Inc.)
- 17899409. TWO-PASS CORRECTIVE PROGRAMMING FOR MEMORY CELLS THAT STORE MULTIPLE BITS AND POWER LOSS MANAGEMENT FOR TWO-PASS CORRECTIVE PROGRAMMING simplified abstract (Micron Technology, Inc.)
- 17941831. ADAPTIVE PRE-READ MANAGEMENT IN MULTI-PASS PROGRAMMING simplified abstract (Micron Technology, Inc.)
- 18401251. USING DUPLICATE DATA FOR IMPROVING ERROR CORRECTION CAPABILITY simplified abstract (Micron Technology, Inc.)
- 18432326. MEMORY COMPACTION MANAGEMENT IN MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 18483091. TEMPORARY PARITY BUFFER ALLOCATION FOR ZONES IN A PARITY GROUP simplified abstract (Micron Technology, Inc.)
- 18511698. MULTI-LAYER CODE RATE ARCHITECTURE FOR COPYBACK BETWEEN PARTITIONS WITH DIFFERENT CODE RATES simplified abstract (Micron Technology, Inc.)
- 18612028. MEMORY DEVICE PROGRAMMING TECHNIQUE FOR INCREASED BITS PER CELL simplified abstract (Micron Technology, Inc.)
- 18651590. MULTIPLE-PASS PROGRAMMING OF MEMORY CELLS USING TEMPORARY PARITY GENERATION simplified abstract (Micron Technology, Inc.)
- 18668021. ONE-LADDER READ OF MEMORY CELLS COARSELY PROGRAMMED VIA INTERLEAVED TWO-PASS DATA PROGRAMMING TECHNIQUES simplified abstract (Micron Technology, Inc.)
- 18753389. MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION simplified abstract (Micron Technology, Inc.)
- 18821886. Reduction of Errors in Data Retrieved from a Memory Device to Apply an Error Correction Code of a Predetermined Code Rate (Micron Technology, Inc.)
- 18895236. READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS (Micron Technology, Inc.)
- 18895273. QUICK CHARGE LOSS MITIGATION USING TWO-PASS CONTROLLED DELAY (Micron Technology, Inc.)
M
- Micron technology, inc. (20240126690). MEMORY DEVICE WITH DYNAMIC CACHE MANAGEMENT simplified abstract
- Micron technology, inc. (20240176698). MEMORY COMPACTION MANAGEMENT IN MEMORY DEVICES simplified abstract
- Micron technology, inc. (20240231617). MEMORY DEVICE PROGRAMMING TECHNIQUE FOR INCREASED BITS PER CELL simplified abstract
- Micron technology, inc. (20240302999). MULTIPLE-PASS PROGRAMMING OF MEMORY CELLS USING TEMPORARY PARITY GENERATION simplified abstract
- Micron technology, inc. (20240304250). ONE-LADDER READ OF MEMORY CELLS COARSELY PROGRAMMED VIA INTERLEAVED TWO-PASS DATA PROGRAMMING TECHNIQUES simplified abstract
- Micron technology, inc. (20240347128). MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION simplified abstract
- Micron technology, inc. (20240412792). SIMPLIFIED OPERATIONS TO READ MEMORY CELLS COARSELY PROGRAMMED VIA INTERLEAVED TWO-PASS DATA PROGRAMMING TECHNIQUES
- Micron technology, inc. (20240419544). Reduction of Errors in Data Retrieved from a Memory Device to Apply an Error Correction Code of a Predetermined Code Rate
- Micron technology, inc. (20250004645). COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY DEVICE
- Micron technology, inc. (20250013382). QUICK CHARGE LOSS MITIGATION USING TWO-PASS CONTROLLED DELAY
- Micron technology, inc. (20250014655). READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS
U
- US Patent Application 17830166. MANAGING QUAD-LEVEL CELL COMPACTION STRATEGY OF A MEMORY DEVICE simplified abstract
- US Patent Application 17863000. MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM simplified abstract
- US Patent Application 18232949. MEMORY DEVICES FOR MULTIPLE READ OPERATIONS simplified abstract
Categories:
- Jiangang Wu of Milpitas CA (US)
- Lei Zhou
- Jung Sheng Hoei of Newark CA (US)
- Qisong Lin of El Dorado Hills CA (US)
- Karl David Schuh of Santa Cruz CA (US)
- Daniel Jerre Hubbard of Boise ID (US)
- James Fitzpatrick of Laguna Niguel CA (US)
- Kishore Kumar Muchherla of Fremont CA (US)
- Inventors
- Inventors filing patents with Micron Technolgy, Inc.
