Category:Fatma Arzum Simsek-Ege of Boise ID (US)

Fatma Arzum Simsek-Ege of Boise ID (US)

Executive Summary

Fatma Arzum Simsek-Ege of Boise ID (US) is an inventor who has filed 22 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (8 patents), {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge} (6 patents), the devices being of types provided for in two or more different subgroups of the same main group of groups (6 patents), and they have worked with companies such as Micron Technology, Inc. (22 patents). Their most frequent collaborators include (5 collaborations), (4 collaborations), (3 collaborations).

Patent Filing Activity

Technology Areas

List of Technology Areas

• H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 8 patents
• G11C11/4085 ({Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}): 6 patents
• H01L25/18 (the devices being of types provided for in two or more different subgroups of the same main group of groups): 6 patents
• H01L25/50 ({Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group): 6 patents
• H10B12/482 (ELECTRONIC MEMORY DEVICES): 4 patents
• H10B12/485 (ELECTRONIC MEMORY DEVICES): 4 patents
• H10B12/488 (ELECTRONIC MEMORY DEVICES): 4 patents
• G11C11/4091 (Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating): 4 patents
• H01L23/5386 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 3 patents
• H10B12/30 (ELECTRONIC MEMORY DEVICES): 3 patents
• H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L24/80 ({Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}): 3 patents
• H10B12/50 (ELECTRONIC MEMORY DEVICES): 3 patents
• H01L2224/08145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L2224/80896 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L23/5384 ({Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors (): 2 patents
• H01L24/83 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H10B12/33 (ELECTRONIC MEMORY DEVICES): 2 patents
• H10B12/036 (ELECTRONIC MEMORY DEVICES): 2 patents
• H01L2224/83895 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/83896 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/80895 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2924/1431 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2924/1436 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H10B12/0335 (ELECTRONIC MEMORY DEVICES): 2 patents
• H10B12/315 (ELECTRONIC MEMORY DEVICES): 2 patents
• H10B80/00 (Assemblies of multiple devices comprising at least one memory device covered by this subclass): 2 patents
• G11C5/025 ({Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits,): 2 patents
• G11C11/4087 ({Address decoders, e.g. bit - or word line decoders; Multiple line decoders}): 2 patents
• G11C5/06 (STATIC STORES (semiconductor memory devices): 2 patents
• H01L29/04 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/1033 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H10B12/00 (Dynamic random access memory [DRAM] devices): 1 patents
• H01L23/5385 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
• H01L23/31 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L27/10897 (including a plurality of individual components in a repetitive configuration): 1 patents
• H10B12/03 (ELECTRONIC MEMORY DEVICES): 1 patents
• H10B12/05 (ELECTRONIC MEMORY DEVICES): 1 patents
• G11C5/063 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C8/14 (Word line organisation; Word line lay-out): 1 patents
• H01L27/10891 (including a plurality of individual components in a repetitive configuration): 1 patents
• G11C11/221 ({using ferroelectric capacitors}): 1 patents
• G11C11/2257 ({Word-line or row circuits}): 1 patents
• G11C11/2259 ({Cell access}): 1 patents
• H01L2924/1441 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L27/10805 (including a plurality of individual components in a repetitive configuration): 1 patents
• H01L27/10885 (including a plurality of individual components in a repetitive configuration): 1 patents
• G06F3/0619 ({in relation to data integrity, e.g. data losses, bit errors}): 1 patents
• G06F3/0623 ({in relation to content}): 1 patents
• G06N20/00 (Machine learning): 1 patents
• G06F3/0659 ({Command handling arrangements, e.g. command buffers, queues, command scheduling}): 1 patents
• G06F3/067 ({Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]}): 1 patents
• G06F3/0656 ({Data buffering arrangements}): 1 patents
• H01L27/1207 ({combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits}): 1 patents
• G11C13/0028 ({Word-line or row circuits}): 1 patents
• G11C13/0038 ({Power supply circuits}): 1 patents
• H01L27/0688 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/8238 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L27/092 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/528 ({Geometry or} layout of the interconnection structure {(): 1 patents
• H01L23/53228 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06541 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents

Companies

List of Companies

• Micron Technology, Inc.: 22 patents

Collaborators

• Mingdong Cui of Folsom CA (US) (5 collaborations)
• Yuan He of Boise ID (US) (4 collaborations)
• Kunal R. Parekh of Boise ID (US) (3 collaborations)
• Masihhur R. Laskar of Meridian ID (US) (1 collaborations)
• Nicholas R. Tapias of Boise ID (US) (1 collaborations)
• Darwin Franseda Fan of Boise ID (US) (1 collaborations)
• Manuj Nahar of Boise ID (US) (1 collaborations)
• Luoqi Li of Boise ID (US) (1 collaborations)
• Marsela Pontoh of Boise ID (US) (1 collaborations)
• Richard E. Facekenthal of Carmichael CA (US) (1 collaborations)
• Richard E. Fackenthal of Carmichael CA (US) (1 collaborations)
• Carly M. Wantulok of Boise ID (US) (1 collaborations)
• Sumana Adusumilli of Boise ID (US) (1 collaborations)
• Chiara Cerafogli of Boise ID (US) (1 collaborations)
• Terrence B. McDaniel of Boise ID (US) (1 collaborations)
• Beau D. Barry of Boise ID (US) (1 collaborations)
• Brenton P. Van Leeuwen of Boise ID (US) (1 collaborations)