Intel Corporation patent applications on 2025-06-26
Patent Applications by Intel Corporation on June 26th, 2025
Intel Corporation: 102 patent applications
Intel Corporation has applied for patents in the areas of H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (use of semiconductor devices for measuring ; resistors in general ; magnets, inductors or transformers ; capacitors in general ; electrolytic devices ; batteries or accumulators ; waveguides, resonators or lines of the waveguide type ; line connectors or current collectors ; stimulated-emission devices ; electromechanical resonators ; loudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers ; electric light sources in general ; printed circuits, hybrid circuits, casings or constructional details of electrical apparatus, manufacture of assemblages of electrical components ; use of semiconductor devices in circuits having a particular application, see the subclass for the application), 2), H01L23/5286 ({Geometry or} layout of the interconnection structure {( takes precedence; algorithms )}, 2), G01N21/9501 ({Semiconductor wafers (manufacturing processes per se of semiconductor devices implementing a measuring step )}, 2), H10D62/118 (No explanation available, 2), H10D30/6757 (No explanation available, 2), H01L23/24 (solid or gel at the normal operating temperature of the device {( takes precedence)}, 2), G01R31/31704 (MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits ), 2), H01L21/7682 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}, 2), H04L9/0631 ({Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms}, 2), H04B1/0475 ({with means for limiting noise, interference or distortion ( takes precedence)}, 2)
With keywords such as: apparatus, plurality, substrate, having, including, glass, coating, support, frame, through-holes in patent application abstracts.
Top Inventors:
- Joshua STACEY of Chandler AZ US (1 patents)
- Whitney BRYKS of Tempe AZ US (1 patents)
- Daniel WANDERA of Chandler AZ US (1 patents)
- Aaditya Anand CANDADAI of Chandler AZ US (1 patents)
- Mahdi MOHAMMADIGHALENI of Phoenix AZ US (1 patents)
Patent Applications by Intel Corporation
20250206659. APPARATUS SYSTEM COATING GLASS SUBSTRATE HAVING PLURALITY THROUGH-HOLES (Intel)
Abstract: an apparatus for coating a glass substrate having a plurality of through-holes, the apparatus including a support frame including one or more abutment portions configured to support the glass substrate in a levelled orientation; a dispenser head operable to deposit a liquid coating on the glass substrate; and a coating unit configured to apply a force on the liquid coating so as to urge the liquid coating to permeate the plurality of through-holes in the glass substrate.
20250207254. METAL PHOSPHIDE DEPOSITION VIA PHOSPHASILANE REACTANTS RELATED STRUCTURES (Intel)
Abstract: metal phosphide deposition via phosphoserine reactants and related structures are disclosed. an example method to deposit a metal phosphide layer via atomic layer deposition, the method including applying a first pulse of a metal precursor to a substrate, purging the first pulse, applying a second pulse of a phosphasilane precursor, and purging the second pulse.
20250207608. APPARATUS REDUCING AIR TURBULENCE FAN CHASSIS (Intel)
Abstract: an apparatus for reducing air turbulence in a fan chassis. the chassis including a cutwater extending from a base of the chassis in a continuous or stepwise manner. wherein a portion of the cutwater extends at one or more acute angles to an axis orthogonal to the base or an axis of an impeller mount of the chassis. wherein the cutwater may include an aperture or recess that extends from a proximal portion of the cutwater to a distal portion of the cutwater.
20250208060. METHODS, APPARATUS, ARTICLES MANUFACTURE DETECT TRANSPARENT FLUX VISIBLE LIGHT (Intel)
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to detect transparent flux with visible light. an example apparatus includes interface circuitry to communicate with an image sensor and programmable circuitry to at least one of instantiate or execute machine-readable instructions. additionally, the example programmable circuitry is to cause the image sensor to capture reflected light off of a substrate, the reflected light being visible. the example programmable circuitry is also to, based on a level of attenuation of the reflected light relative to projected light projected onto the substrate, determine at least one of a presence or a property of transparent flux on the substrate.
20250208061. FAULT ISOLATION SEMICONDUCTOR DEVICE MANUFACTURING (Intel)
Abstract: devices and methods that are useful for fault isolation in microelectronic devices are provided. a portion of a microelectronic device to be analyzed is grounded through the creation of a cavity in the device surface. voltage contrast provides the ability to identify individual failure sites on the microelectronic device. the grounding of the portion of the device can be reversed and a different portion of the microelectronic device grounded for additional voltage contrast analysis and fault identification. these processes can be repeated a number of times to probe multiple chained structures.
20250208190. TITLE DIRECT FLUID COOLING MULTI TEMPERATURE CONTROL (Intel)
Abstract: in some embodiments, provided are test apparatuses suitable for operation in semiconductor environmental testing chambers that can provide both first fluid (e.g., hot fluid) and second fluid (cold fluid) delivery without requiring a complete teardown of the utilized assembly.
Abstract: a test pattern syntax allows cycles of interest for a device to be tagged as serial protocol data sources during test of the integrated circuit in semiconductor automatic test equipment (ate). a test pattern syntax is used to tag serial bits of interest. metadata (from serial capture control contents) in combination with the tagged serial bits of interest received during the test of the integrated circuit is used to identify data in the tagged serial bits of interest. data in the with tagged serial bits of interest is sent to other location(s) in the automated test equipment. the data in the tagged serial bits of interest can be used for real time decisions (such as thermal control) or plotted in a graphical user interface (gui) during test of the integrated circuit.
20250208196. METHODS APPARATUS DETECT CAPACITOR LEAKAGE SEMICONDUCTOR DIES (Intel)
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to detect capacitor leakage in semiconductor dies. an example apparatus includes a semiconductor die comprising a transistor, a first contact on a first surface of the semiconductor die, the first contact electrically coupled to a first terminal of the transistor, a second contact on the first surface of the semiconductor die, the second contact electrically coupled to a second terminal of the transistor, a capacitor between the first surface and a second surface of the semiconductor die opposite the first surface, the second contact electrically coupled to a first electrode of the capacitor, and a third contact on the first surface of the semiconductor die, the third contact electrically coupled to a second electrode of the capacitor.
20250208197. MULTI ZONE TEMPERATURE CONTROL DEVICES UNDER TEST (Intel)
Abstract: provided is a fluid delivery system with a plurality of nozzles to control the temperatures of multiple zones in a device under test.
20250208204. DOUBLE-SIDED INTEGRATED CIRCUIT PACKAGE APPARATUS RELATED METHODS (Intel)
Abstract: double-sided integrated circuit package apparatus and related methods are disclosed herein. an example apparatus includes an integrated circuit package including a die, and a package substrate having a first surface and a second surface opposite the first surface, the die coupled to the first surface, the first surface including a plurality of first contact pads and the second surface including a plurality of second contact pads, the first contact pads spaced apart from the die, the first contact pads and the second contact pads being electrically coupled with the die.
20250208206. AUTOMATED LOW POWER CELL INSERTION DFT-ENABLED MULTI POWER PLANE DESIGNS (Intel)
Abstract: a method includes determining a register-transfer level and unified power format (rtl-upf) description for a circuit that includes a plurality of rtl modules, at least two of the rtl modules being located in different power plane domains; determining a design for test (dft) for the rtl-upf description by adding a scan control logic and associated scan flip flops to the rtl-upf description, thereby generating at least one power domain crossing between the at least two power plane domains, wherein the at least one power domain crossing is unprotected with respect to a floating voltage level on the at least one power domain crossing; determining an isolation cell requirement for the at least one power domain crossing; selecting an rtl-upf isolation rule using the determined isolation cell requirement for the at least one power domain crossing; and inserting an isolation cell described by the selected rtl isolation rule into the dft.
20250208207. TEST (DFT) DESIGN DEBUG (DFD) GATED POWER DOMAINS (Intel)
Abstract: power-gated domains are provided for design for test (dft) and/or design for debug (dfx) logic units in a semiconductor chip. power-gated domains allow power consumption to be reduced when dft and dfd logic units are not in use. power-gated domains can include reset features and output port power isolation.
20250208208. METHODS APPARATUS FAULT ISOLATION SCANNING ELECTRON MICROCROSCOPE PROBING (Intel)
Abstract: methods and apparatus for fault isolation with scanning electron microscope probing are disclosed. an example apparatus to test a circuit includes interface circuitry operatively coupled to an electron detector, the electron detector to output a signal corresponding to electron emissions from the circuit as the circuit is driven with a signal source and the circuit is rastered with an electron beam, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to demodulate the signal, and generate an image based on the demodulated signal for determination of a condition of the circuit.
20250208250. ADAPTATION INDOOR LOCALIZATION SYSTEM (Intel)
Abstract: a fingerprint is received from a device that identifies a plurality of signal strength values corresponding to a plurality of wireless access points as measured by the device within a physical environment. a first machine learning model is used to determine that a subset of access points in the plurality of wireless access points are missing in the physical environment based on the fingerprint, and a machine-learning-based localization model is modified to generate a modified localization model to account for the subset of access points missing in the physical environment, where the localization model is trained based on training data collected when the plurality of wireless access points were present and operational within the environment.
20250208497. EUV MASK BLANK CONNECTIVITY-BASED DEFECT MITIGATION (Intel)
Abstract: possible positions for forming an absorber pattern on an extreme ultraviolet (euv) mask blank are determined. the absorber pattern corresponds to a mask layer that in turn corresponds to integrated circuit design. the position of the buried defects identified in the euv mask blank are analyzed with respect to the absorber pattern placed in the possible positions. if, based in part on connectivity information for the mask layer, all of the buried defects are located within empty regions of the mask layer or coincide with dummy polygons of the mask layer, the possible position is identified as a candidate position. one of the candidate positions is selected as the selected position at which the absorber pattern will be formed on the euv mask. the selected position can be, for example, the candidate position having the fewest number of buried defects that coincide with dummy regions.
20250208638. LEVEL SHIFT FUNCTIONAL CIRCUITS EOS PROTECTION (Intel)
Abstract: in some embodiments, bias circuits are provided that can generate resilient output supplies without consuming excessive power. in addition, other resilient and efficient bias circuits may be provided that can be used for biasing level shift and other high supply circuit blocks such as ldos with thin gate transistors over a relatively wide high supply voltage operational range.
20250208685. INVERSE TEMPERATURE-DEPENDENT POWER CONTROL MULTI-CORE PROCESSOR (Intel)
Abstract: embodiments herein relate to techniques to select one or more processor cores, of a multi-core processor, for a workload based on a temperature associated with the processor cores. the processor circuitry may further include temperature sensors (e.g., temperature sensing diodes) arranged to generate temperature information that is associated with respective individual processor cores of the plurality of processor cores. it may be determined that one or more of the processor cores need to be woken up from a low power state to handle a workload. a control circuitry may receive the temperature information and may select a first processor core, of the plurality of processor cores, to wakeup from the low power state based on the temperature information. for example, the control circuitry may prioritize the processor core with the highest temperature according to the temperature information. other embodiments may be described and claimed.
Abstract: an echo detection device is provided. the echo detection device may include a processor, configured to activate a transcription process that transcribes words generated from audio transmissions between a host device and at least one further device to text, analyze the text for identification of repeated character strings that are indicative of an echo, and, if an echo is detected, decode the audio transmission into a plurality of audio packets, form an echo-filtered audio stream by filtering out duplicate audio packets of the plurality of audio packets, and transmit the echo-filtered audio stream to the at least one further device and/or to an audio device of the host device is provided.
20250208826. METHODS DEVICES PERFORM SHORT-RANGE WIRELESS COMMUNICATION (Intel)
Abstract: an apparatus of a communication device, the apparatus may include a first interface configured to stream first audio data via an established link, wherein the established link is between the communication device and a further communication device; a second interface configured to receive second audio data from an audio input device; and a processor configured to: monitor, during a streaming of the first audio data via the established link, the second audio data; and determine a result representing whether the second audio data comprises information representative of a presence of an auditory interruption.
Abstract: examples include techniques for contention-free routing for number-theoretic-transform (ntt) or inverse-ntt (intt) computations routed through a parallel processing device. examples include a tile array that includes a plurality of tiles arranged in a 2-dimensional mesh interconnect-based architecture. each tile includes a plurality of compute elements configured to execute ntt or intt computations associated with a fully homomorphic encryption workload. contention-free routing to include use of selective stalls and destination ports indicated in routing tables maintained at tiles of the tile array can facilitate ntt/intt computation throughput through the parallel processing device.
20250208902. DEVICE, METHOD SYSTEM PROVIDE PREDICTION STATE INFORMATION PROCESSOR (Intel)
Abstract: techniques and mechanisms for automatically saving and recovering microarchitectural prediction state information of a processor core. in an embodiment, a core comprises prediction circuitry which generates microarchitectural prediction state information based on an execution of a software process by the core. a prediction state manager of the processor detects a context switch of the processor and, based on such detection, automatically saves a version of the microarchitectural prediction state information to a repository which is external to the core. the microarchitectural prediction state information is available to be recovered from the repository to facilitate a resumed execution of the software process. in another embodiment, the microarchitectural prediction state information is saved to, or recovered from, the repository independent of an instruction of the software process, if any, which specifies that such saving or recovery is to be performed.
20250208905. METHODS, APPARATUS, SYSTEMS, INSTRUCTIONS MIGRATE PROTECTED VIRTUAL MACHINES (Intel)
Abstract: techniques for migration of a source protected virtual machine from a source platform to a destination platform are descried. a method of an aspect includes enforcing that bundles of state, of a first protected virtual machine (vm), received at a second platform over a stream, during an in-order phase of a migration of the first protected vm from a first platform to the second platform, are imported to a second protected vm of the second platform, in a same order that they were exported from the first protected vm. receiving a marker over the stream marking an end of the in-order phase. determining that all bundles of state exported from the first protected vm prior to export of the marker have been imported to the second protected vm. starting an out-of-order phase of the migration based on the determination that said all bundles of the state exported have been imported.
20250208919. DEVICE, METHOD SYSTEM DETERMINING CREDIT-BASED ACCESS SHARED CIRCUIT RESOURCE (Intel)
Abstract: techniques and mechanisms for any of multiple processor circuits to be able to access a shared circuit resource. in an embodiment, processor circuits variously provide respective requests to access a resource of a computation circuit. a pool of requestor processor circuits is managed based on the access requests. for a pending access request, an amount of credit for the corresponding pool member accumulates at a rate which is based on the current pool size. for an access request which is being serviced, the amount of credit for the corresponding pool member is consumed at a relatively fast rate. access to the resource is allocated based on the respective amounts of credit for each pool member. in another embodiment, a prioritized access request results in a transition from resource access allocation according to a credit-based scheme to resource access allocation according to a priority-based scheme.
20250208920. CONTEXT AWARE FREQUENCY PRIORITIZATION (Intel)
Abstract: disclosed are processor systems having cores with context registers to store priority information for threads to run on the core. they also include circuitry to change the core frequency for the thread based on the priority information.
20250208939. METHODS APPARATUS MONITOR CORRECTABLE ERRORS DEVICE INTERFACE (Intel)
Abstract: disclosed examples include interface circuitry; machine-readable instructions; and at least one out-of-band processor circuit to be coupled to at least one host processor circuit, the at least one out-of-band processor circuit to be programmed by the machine-readable instructions to at least: detect a first error in a link between devices; increment an error count after the detection of the first error; decrement the error count after a duration has elapsed relative to the first error; and cause sending of a message to a reliability, accessibility, and serviceability agent after the error count satisfies a threshold.
Abstract: techniques for probabilistic data manipulation detection based on collision patterns and encryption in a computing system are described. in certain examples, a computing system includes a memory; an execution circuitry to execute an instruction to generate a memory request to read a data line from the memory; and a memory controller circuit to: decrypt the data line into a decrypted data line, determine that a field of the decrypted data line is not set to a conflict indicator value, determine a number of value collisions within the data line, and mark the data line with an error indication in response to the number of value collisions being less than a maximum threshold of value collisions, and the field of the decrypted data line not being set to the conflict indicator value.
20250208960. CORRECTABLE ERROR ADDRESS FILTERING PROCESSING ARCHITECTURE (Intel)
Abstract: an apparatus to facilitate correctable error address filtering in a processing architecture is disclosed. the apparatus includes a processor comprising error routing hardware circuitry to: receive data associated with an error detected in a source hardware component hosting the error routing circuitry; determine, based on the data, that the error is classified as a correctable error; compare an address of the correctable error to entries maintained by correctable error address filtering circuitry of the error routing circuitry; responsive to the address of the correctable error matching an entry of the correctable error address filtering circuitry, mask the correctable error to prevent reporting of the correctable error to error aggregation hardware circuitry of the processor; and responsive to the address of the correctable error not matching the entries of the correctable error address filtering circuitry, report the correctable error to the error aggregation hardware circuitry.
20250209003. ERROR INJECTION ARCHITECTURE PROCESSING ENVIRONMENT (Intel)
Abstract: an apparatus to facilitate an error injection architecture in a processing environment is disclosed. the apparatus includes at least one register to enable an error injection; and error injection hardware circuitry communicably coupled to the at least one register, wherein the error injection hardware circuitry is to: determine a type of the error injection configured in the at least one register, wherein the at least one register is configured via a memory-mapped input/output (mmio) interface of the error injection hardware circuitry; inject an error in accordance with the type of the error injection, wherein the error is injected to at least one of a parity-protected storage unit, an error correction code (ecc)-protected storage unit, a parity-protected fabric agent, or an ecc-protected fabric agent; and log a status of the error injection using the at least one register.
20250209009. HARDWARE RESOURCE SHARING THROUGH DEVICE PROXY (Intel)
Abstract: a device includes memory-based cross-domain solutions (m-cds) circuitry including shared memory and logic to create a buffer in the shared memory region for data exchange with a given device, where the buffer is created to implement a restricted memory-based communication channel for the given device, and implement a device proxy to emulate the given device, where the device proxy exchanges data with the given device through the memory-based communication channel, and an application is to interact with the device proxy as if the device proxy were the given device.
20250209010. SCALABLE CENTRALIZED ERROR QUEUES PROCESSING ARCHITECTURE (Intel)
Abstract: an apparatus to facilitate scalable centralized error queues in a processing architecture is disclosed. the apparatus includes a processor comprising a systems interface hosting an error aggregator, wherein the processor is to host at least one centralized error queue in the error aggregator, the at least one centralized error queue is to store error logs for errors detected by components of the processor; receive an error reporting message from a component of the components of the processor, the error reporting message corresponding to an error detected by the component; and log the error as an entry in the at least one centralized error queue based on an error type of the error.
20250209021. SCALABLE I/O VIRTUALIZATION INTERRUPT SCHEDULING (Intel)
Abstract: embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. the techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.
20250209027. RESILIENT I/O INTERCONNECT (Intel)
Abstract: disclosed are interconnect systems with spatially separated redundant interconnects to replace faulty interconnects. in some embodiments, error correction code techniques may also be used to enhance communications robustness.
20250209169. METHOD APPARATUS PLATFORM ROOT KEY UPDATE BASED SECURITY ATTACK DETECTION (Intel)
Abstract: methods, apparatus, and computer programs are disclosed to update a platform root key based on security attack detection. in one embodiment, a method comprises: detecting an attack to a platform root key of a computing system, the platform root key stored in a region within a hardware module of the computing system and serving as a seed key of a plurality of cryptographic keys of the computing system; responsive to detecting the attack to the platform root key, generating an updated platform root key using a key generation function to replace the platform root key; and causing the updated platform root key to be utilized in one or more of application signing, verification, and attestation in the computing system.
20250209221. SYSTEMS METHODS THAT INCLUDE STANDARD CELL YIELD PREDICTIONS LIBRARY (Intel)
Abstract: systems and methods for providing standard cell yield information in a library (i.e., creating “defect-aware” libraries). the method includes accessing a library of a plurality of standard cells characterized on a foundry process node and revision. a geometric analysis is performed on individual ones of the standard cells to identify potential defects, such as shorts and opens. a defect is injected (i.e., “realized” or “actualized”) at the location of the identified potential defects. the standard cells in the library are then simulated with the defects injected to generate simulated yield information. additionally, methods can access silicon failure analysis data representing test chips designed with the library and generate an inferred failure rate for the individual standard cells in the library, as a function of the silicon failure analysis and the simulated yield information.
20250209316. EFFICIENT CONVOLUTION MACHINE LEARNING ENVIRONMENTS (Intel)
Abstract: a mechanism is described for facilitating smart convolution in machine learning environments. an apparatus of embodiments, as described herein, includes one or more processors including one or more graphics processors, and detection and selection logic to detect and select input images having a plurality of geometric shapes associated with an object for which a neural network is to be trained. the apparatus further includes filter generation and storage logic (“filter logic”) to generate weights providing filters based on the plurality of geometric shapes, where the filter logic is further to sort the filters in filter groups based on common geometric shapes of the plurality of geographic shapes, and where the filter logic is further to store the filter groups in bins based on the common geometric shapes, wherein each bin corresponds to a geometric shape.
20250209564. SPARSE OPTIMIZATIONS MATRIX ACCELERATOR ARCHITECTURE (Intel)
Abstract: embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.
20250209807. DYNAMIC NEURAL NETWORK SCHEDULING VISUAL TASKS (Intel)
Abstract: an example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to identify at least one region of interest associated with a computer vision task, measure accuracy of the computer vision task in a covariance space, the accuracy of the computer vision task associated with computer resource consumption, and select at least one neural network from a group of neural networks based on the measured accuracy of the computer vision task.
20250210102. MEMORY BITCELL BALANCED DIFFUSION LAYOUT (Intel)
Abstract: various embodiments provide apparatuses, systems, and methods for a memory bitcells with a balanced distribution of (e.g., equal numbers of) p-type transistors (e.g., p-type metal-oxide-semiconductor (pmos)) and n-type transistors (e.g., n-type metal-oxide-semiconductor (nmos)). for example, the memory bitcell may include an nmos passgate transistor and a pmos passgate transistor coupled to the bit node. the memory bitcell may further include another nmos passgate transistor and another pmos passgate transistor coupled to the bit bar node. other embodiments may be described and claimed.
20250210120. POWER CONDITIONING CIRCUIT IN-FIELD FUSE PROGRAMMING (Intel)
Abstract: an apparatus of a fuse array includes a bit cell coupled to a high voltage (hv) programming supply rail. the bit cell includes at least one p-channel metal-oxide semiconductor (pmos) transistor. the fuse array further includes a column selection n-channel metal-oxide semiconductor (nmos) device coupled to the bit cell. the column selection nmos device includes a first nmos transistor and a second nmos transistor. the second nmos transistor is configured to enable programming of the bit cell based on a program enable signal. the fuse array further includes a power multiplexer (mux) coupled to the first nmos transistor and configured to control voltage supplied to a gate of the first nmos transistor based on a program control signal and the program enable signal.
20250210268. PRE-FABRICATED COMPONENT-HYBRIDS EMBEDDING CORE (Intel)
Abstract: embodiments disclosed herein include assemblies with component substrates that are coupled to spacer base substrates. in an embodiment, such an apparatus comprises a first substrate with a first width, and a first layer on the first substrate. in an embodiment, a second substrate with a second width is over the first layer, and the second width is smaller than the first width. in an embodiment, a second layer is over the first substrate and around the second substrate.
20250210392. HANDLING ASSEMBLY, HANDLING SYSTEM METHOD (Intel)
Abstract: various aspects may provide a handling assembly. the handling assembly may include a body with a component-handling surface. the component-handling surface may include a first component-handling region configured to accommodate a first semiconductor component arrangement and a second component-handling region configured to accommodate a second semiconductor component arrangement. the handling assembly may further include an electrode arrangement disposed at the body in a manner so as to be capable of independently toggling each of the first component-handling region and the second component-handling region between an active state and an inactive state. in the active state the electrode arrangement may provide an electrostatic retention force over the component-handling region, configured to retain a corresponding semiconductor component arrangement on the component-handling region.
20250210398. PATTERNABLE BOND-DEBOND PROCESSES APPARATUSES (Intel)
Abstract: in some embodiments, a patternable tbdb for assembling 3d assemblies such as ic/optical assemblies are provided. a patternable tbdb adhesive may be formed using silicone based tbdb adhesives with incorporated photocatalysts to allow for patterning of the tbdb adhesive layer.
20250210402. METHODS APPARATUS DISAGGREGATION SEMICONDUCTOR DIES INTEGRATED CIRCUIT PACKAGE (Intel)
Abstract: methods and apparatus for disaggregation of semiconductor dies in an integrated circuit package. an example apparatus includes interface circuitry, machine readable instructions, programmable circuitry to at least one of instantiate or execute the machine readable instructions to generate an adjacency matrix for different functional blocks to be implemented in an integrated circuit, the adjacency matrix defining connections between ones of the functional blocks, and determine a group of the functional blocks to be included in a first chiplet of a plurality of chiplets for the integrated circuit, the group of the functional blocks determined based on weights assigned to the connections defined in the adjacency matrix.
20250210411. INTERCONNECT LAYERS AIR GAPS (Intel)
Abstract: in a metallization layer of an integrated circuit device, air gaps are formed between adjacent metal lines, e.g., between high aspect ratio metal lines at tight pitches, to reduce the capacitance between the metal lines. a deposition process for a dielectric material between metal lines is tuned so that air gaps are formed within the dielectric material, in areas between metal lines. the dielectric material is also deposited between the upper portions of the metal lines, closing the air gaps from the top. the dielectric material is highly selective to a subsequent via etch, so that the dielectric material near the tops of the metal lines acts as an etch stop and prevents punch through into the air gaps.
20250210412. RECESSED OXIDE SEAM-FIRST ETCH AIR-GAPPED ISOLATION WALLS (Intel)
Abstract: air gaps are incorporated into a transistor layer to reduce capacitance between conductive components. in some embodiments, along a gate cut region extending across the gates of multiple transistors, a gate cut dielectric may be partially or fully replaced by an air gap. the air gap may extend between two adjacent gates of two adjacent transistors, or between a gate and a via, where the via extends through the gate line and between two gates. the air gaps are capped by a dielectric material, so that additional layers (e.g., back side interconnect layers) may be formed over the air gap. an oxide layer over the transistor layer may be recessed relative to a via to ensure capping of the air gaps. the air gaps may be widened outward from a central seam in the gate cute dielectric.
20250210426. MICROELECTRONIC ASSEMBLIES STRENGTHENED GLASS CORES (Intel)
Abstract: various techniques for alleviating crack formation and propagation in glass cores of microelectronic assemblies, and related devices and methods, are disclosed. the techniques are based on including fillers into glass cores and/or in layers provided on top and/or bottom of glass cores. the fillers have at least one characteristic indicative of material's resistance to breaking under stress being higher than that of glass, which may provide reinforcement and/or increase stiffness of glass, thereby strengthening glass cores. examples of such characteristics include material strength, fracture toughness, or elastic modulus.
20250210428. STIFFENER ASSEMBLY (Intel)
Abstract: there may be provided a stiffener assembly for a semiconductor package. the stiffener assembly may include a corner member and a frame member. a primary mating element of the corner member and a secondary mating element of the frame member may be configured to interlock with each other to form a connection joint that permits movement of the secondary mating element relative to the primary mating element.
Abstract: integrated circuit packages with stiffeners containing semiconductor dies and associated methods are disclosed. an example apparatus includes: a base die coupled to a package substrate; a stiffener adjacent the base die, the stiffener including a cavity; and a semiconductor die different from the base die. the semiconductor die is in the cavity in the stiffener. the example apparatus also includes a bridge to electrically couple the semiconductor die to the base die.
20250210456. Active Cooling Heterogenous Packages (Intel)
Abstract: a present chip assembly may have a matrix of dies and cooling devices that may provide active cooling within a package. the cooling devices may provide airflow directed to spaces that are provided between dies placed on a support platform. the placement of the cooling devices may be optimized to provide active cooling at hot spot areas of the package.
Abstract: devices, transistor structures, systems, and techniques are described herein related to selective front and backside contacts for stacked transistor devices. a transistor structure includes stacked first and second semiconductor structures with stacked first and second conductivity type source and drain structures coupled to the first and second semiconductor structures, respectively. a selective metal is on the frontside of first conductivity type source and a different metal is on the backside of the second conductivity type source. a deep via optionally having yet a different metal couples the frontside contact to backside metallization over the backside contact.
20250210469. MIXED DEPTH CAVITY EMBEDDED BRIDGE STRUCTURES (Intel)
Abstract: embodiments disclosed herein comprise an apparatus. in an embodiment, the apparatus comprises a substrate with a first cavity into the substrate. in an embodiment, the first cavity has a first depth. in an embodiment, a second cavity is provided into the substrate, where the second cavity has a second depth that is different than the first depth. in an embodiment, a first die is in the first cavity, where the first die has a first thickness. in an embodiment, a second die is in the second cavity, where the second die has a second thickness that is different than the first thickness.
20250210491. VERTICALLY EMBEDDED UTILITY PATCH SEMICONDUCTOR PACKAGES (Intel)
Abstract: integrated circuit (ic) devices and systems with embedded utility patches, and methods of forming the same, are disclosed herein. in one embodiment, a microelectronic assembly includes a first substrate with a cavity, and one or more second substrates embedded in the cavity. the first substrate is oriented on a first plane, and the one or more second substrates are oriented on one or more second planes that are substantially orthogonal to the first plane.
20250210495. MICROELECTRONIC ASSEMBLIES SELECTIVE METALLIZATION GLASS CORES (Intel)
Abstract: selective metallization for fabricating conductive vias in glass cores, as well as related devices, are disclosed. in one aspect, a method for fabricating a conductive via in a glass core using selective metallization includes forming an opening in the glass core, the opening extending from a surface of the glass core (e.g., from the top surface) towards an opposite surface of the glass core (e.g., towards the bottom surface), lining sidewalls of the opening with a seed material, depositing a passivation material onto the surface of the glass core from which the opening lined with the seed material extends into the glass core, and subsequently filling the opening with a conductive fill material. the passivation material is a material that reduces or prevents deposition of the conductive fill material thereon.
Abstract: apparatuses, capacitor structures, systems, and techniques related to capacitors having passivation boundary defects within a polycrystalline dielectric material of the capacitor are discussed. the polycrystalline dielectric material includes crystalline grains of a first composition having grain boundaries between the crystalline grains. at some of the grain boundaries, the polycrystalline dielectric material includes amorphous passivation material having a second composition.
20250210509. SINGLE DAMASCENE VIA PROFILES ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION (Intel)
Abstract: embodiments of the disclosure are in the field of integrated circuit structure fabrication. in an example, an integrated circuit structure includes a first conductive interconnect line in a first inter-layer dielectric (ild) layer above a substrate, the first conductive interconnect line along a first direction. a second conductive interconnect line is in a second ild layer above the first ild layer, the second conductive interconnect line along a second direction orthogonal to the first direction. a conductive via is coupling the first conductive interconnect line and the second conductive interconnect line, the conductive via inwardly tapered from a top to a bottom of the conductive via along curved sidewalls along the second direction but not along the first direction, and the conductive via contiguous with but not continuous with the second conductive interconnect line.
20250210510. INTEGRATED CIRCUIT STRUCTURES TRENCH CONTACT SPACER STRUCTURE (Intel)
Abstract: integrated circuit structures having trench contact spacer structures are described. a structure includes a fin or a vertical stack of horizontal nanowires, a gate stack, and an epitaxial source or drain structure. a first conductive layer is on the epitaxial source or drain structure. a second conductive layer is on the first conductive layer. a first dielectric spacer is along a side of the gate stack and laterally adjacent to the epitaxial source or drain structure, the first conductive layer, and the second conductive layer. a second dielectric spacer is along the first dielectric spacer and vertically over the epitaxial source or drain structure, the first conductive layer, and the second conductive layer. a conductive fill material is on the second conductive layer and laterally adjacent to the second dielectric spacer, wherein the conductive fill material has a lateral width less than a lateral width of the second conductive layer.
20250210521. SEMICONDUCTOR DIES HAVING BACKSIDE POWER SWITCH COMPONENTS RELATED METHODS (Intel)
Abstract: semiconductor dies having backside power switch components and related methods are disclosed herein. an example semiconductor die includes a semiconductor substrate defining a front side and a backside. a signal network is provided on the front side. the signal network includes a plurality of first transistors. a power delivery network is provided on the backside. the power delivery network includes a power switch provided on the backside. the power switch includes a plurality of second transistors. the power switch is to cause operation of the first transistors to switch between a first operating state and a second operating state.
20250210522. AIR-GAPPED ISOLATION WALLS (Intel)
Abstract: air gaps are incorporated into a transistor layer to reduce capacitance between conductive components. in some embodiments, along a gate cut region extending across the gates of multiple transistors, a gate cut dielectric may be partially or fully replaced by an air gap. the air gap may extend between two adjacent gates of two adjacent transistors, or between a gate and a via, where the via extends through the gate line and between two gates. as another example, air gaps may extend between adjacent source or drain regions between pairs of adjacent transistors, e.g., in a device that includes back side source or drain contacts. the air gap may be formed on the back side of the device. the air gaps are capped by a dielectric material, so that additional layers (e.g., back side interconnect layers) may be formed over the air gap.
20250210586. SEMICONDUCTOR PACKAGE SUBSTRATE DICING EDGE PASSIVATION (Intel)
Abstract: processes and process equipment for modifying edges of semiconductor package substrates, and semiconductor package substrates having modified edges are provided. the processes and process equipment are especially useful for semiconductor package substrates that have cores that can crack or chip during processing, such as, for example, cores comprised of glass. semiconductor package substrates having glass cores and modified edges are also provided.
20250210587. PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES VOLTAGE DOMAIN STACKING (Intel)
Abstract: embodiments of an integrated circuit (ic) die may include a substrate having a first surface with an array of first conductive pads, an opposite second surface, a third surface orthogonal to first and second surfaces, and through substrate vias (tsvs) electrically coupled to the array of first conductive pads; and a metallization stack having a fourth surface, an opposite fifth surface, and a sixth surface orthogonal to the fourth and fifth surfaces, and including a conductive trace parallel to the fourth and fifth surfaces and exposed at the sixth surface, and conductive vias between the fourth and fifth surfaces and exposed at the fifth surface, wherein the second surface of the substrate is coupled to the fourth surface of the metallization stack and an interface between the substrate and the metallization stack includes an array of second conductive pads electrically coupled to the conductive trace and conductive vias.
20250210894. GRID ARRAY ELECTRICAL CONNECTORS (Intel)
Abstract: electrical connectors for a semiconductor device package to a circuit board are provided. the electrical connectors can include interconnections having a first resistance that is greater than a second resistance. assemblies are provided that include an electrical connector and a circuit board. assemblies can also include a semiconductor device package. the assemblies provide connections to ground on the circuit board that have a higher resistance than connections for signal input output.
20250211009. IDENTIFICATION CHARGER PLUG (Intel)
Abstract: embodiments herein relate to a power cable assembly that includes a light source, an output to provide direct current (dc) power to an electronic device, an input to receive alternating current (ac) power from a power source, first circuitry, and second circuitry. the first circuitry may be configured to identify, from the electronic device, a first signal; generate, based on the first signal, a high-frequency (hf) signal with a frequency at or above 9 khz; and output, to second circuitry, the hf signal. the second circuitry may be configured to provide power to the light source based on the ac high-frequency signal. other embodiments may be described and/or claimed.
20250211085. LIGHT LOAD EFFICIENCY BOOST SWITCHED CAPACITOR POWER CONVERTERS (Intel)
Abstract: embodiments herein relate to a switched capacitor power converter which reduces the leakage current through a power switch when the power switch is turned off. in one aspect, a first charge pump provides a voltage vcc_cp which is higher than a power supply voltage vcc, and a second charge pump provides a voltage vss_cp which is lower than a ground voltage vss. transistors are used to couple the first charge pump to the control gate of a p-type power switch and to couple the second charge pump to the control gate of an n-type power switch. in another example implementation, the voltage of the power switch is pulled up or down using a bootstrap capacitor.
Abstract: embodiments herein relate to a switching power converter which monitors the output voltage of a power train as it varies between peaks and valleys during switching of the power train. the power train includes a high-side p-type transistor and a low-side n-type transistor. when a peak of the output voltage is positive for a number of consecutive clock cycles, a process is initiated to transition the high-side transistor from hard switching to soft switching. this involve gradually increasing a time between a turn off of the low-side transistor and a turn on of the high-side transistor. the switching power converter can include a comparator and logic circuits.
20250211109. VOLTAGE REGULATOR (Intel)
Abstract: embodiments herein relate to a voltage regulator (vr) which includes a main current source (mcs), a parallel current source (pcs) which is activated when a voltage droop is detected, and a finite state machine (fsm) to manage a recovery from the voltage droop. the fsm can have a droop state in which a droop is detected in the output voltage of the vr and the pcs provides an output current to an output node of the vr, a pcs ramp down state in which the output current of the pcs ramps down while the mcs has a boosted set point, and a voltage identifier (vid) boost ramp down state in which the set point of the mcs ramps down from the boosted set point.
20250211212. DUTY CYCLE REGULATOR (Intel)
Abstract: embodiments herein relate to a duty cycle evaluation circuit which includes a finite state machine (fsm), a logic circuit coupled to the fsm, a tunable delay circuit having an input coupled to an output of the logic circuit, a flip-flop having clock input coupled to the input of the tunable delay circuit and a data input coupled to an output of the tunable delay circuit, a first sampling circuit having a data input coupled to a data output of the flip-flop, a data output coupled to the fsm and a clock input coupled to the fsm, and a second sampling circuit having a data input coupled to the data output of the flip-flop, a data output coupled to the fsm and a clock input coupled to the fsm.
20250211238. DIE-TO-DIE CLOCK SIGNALLING INCLUDING ADAPTIVE FREQUENCY DELAY-LOCKED LOOP (Intel)
Abstract: some embodiments include an apparatus having a first delay line of a delay-locked loop (dll) circuitry, the first delay line including an input node to receive an input clock signal and delay stages coupled in series with the input node; a first multiplexer including input nodes coupled to output nodes of a portion of the delay stages; and a second delay line of the dll circuitry including an input node coupled to an output node of the multiplexer, and delay stages coupled in series with the input node of the second delay line, the second delay line including an output node to provide an output clock signal.
Abstract: an apparatus for processing an undersampled digital input signal, comprises an input node configured to receive the undersampled digital input signal. a first circuitry is configured to perform a bandpass interpolation on the undersampled digital input signal to generate an interpolated digital signal using an interpolation factor depending on a nyquist zone m selected from multiple nyquist zones, m being greater than 1. a non-linear equalizer generates an equalized signal from the interpolated digital signal. a second circuitry is configured to downsample the equalized signal to a sample rate of the undersampled digital input signal.
20250211265. Method apparatus digital pre-distortion adaptation (Intel)
Abstract: a method and apparatus configured for digital pre-distortion (dpd) adaptation. the apparatus may include dpd circuitry and dpd adaptation circuitry. the dpd circuitry is configured to process input data using a pre-distortion function to generate pre-processed input data that is to be subsequently processed by a non-linear system. the pre-distortion function is represented as a sum of a plurality of non-linear terms, and non-linear effects of the non-linear system are compensated by the dpd circuitry. the dpd adaptation circuitry is configured to adapt coefficients of the dpd circuitry based on feedback information derived from an output signal of the non-linear system. the dpd adaptation circuitry is configured to adapt the plurality of non-linear terms of the pre-distortion function one non-linear term at a time. the pre-distortion function may be evaluated using look-up tables (luts). the luts may be adapted one lut at a time in a round robin fashion.
20250211266. METHOD APPARATUS REDUCING COMPLEXITY DIGITAL PRE-DISTORTION MODEL (Intel)
Abstract: a method and apparatus for reducing complexity of a digital pre-distortion (dpd) model for a non-linear system. dpd circuitry applies a pre-distortion function to input samples to generate pre-distorted samples. the pre-distortion function is represented by a sum of a plurality of terms, and each term is a function of one or more input samples. an optimization process is performed to determine a subset of the terms and a subset of input samples for each term. an optimization function is solved iteratively to find parameters of the pre-distortion function that minimize the optimization function. each term of the pre-distortion function may be multiplied with a multiplier factor with a constraint that the terms have a unit norm. alternatively, the subset of input samples may be selected for each term by filtering the input samples with a filter with a constraint that coefficients of the filer have a unit norm.
20250211302. ENHANCED CHANNEL STATUS INDICATOR PREDICTIONS (Intel)
Abstract: disclosed herein are devices, methods, and systems for predicting channel status information (csi) values and their confidence levels. the system may obtain a current csi value of a wireless channel at a current time and generate, based on the current csi value and a learning model that is based on csi values and csi predictions, a predicted csi value and a confidence metric. the system may generate a recommended periodicity of csi measurements of the wireless channel. in addition, the confidence metric is for the predicted csi value based on the learning model, wherein the confidence metric indicates a level of confidence in the predicted csi value for the prediction time. the system may adjust a scheduling parameter for the wireless channel based on the predicted csi value and the confidence metric.
20250211314. SYSTEMS, DEVICES METHODS WIRELESS COMMUNICATION (Intel)
Abstract: a radio communication system includes an antenna array comprising a plurality of antenna elements configured to receive a plurality of radio frequency (rf) signals, rf circuitry coupled to the antenna array configured to downconvert the rf signals to generate analog baseband signals, and analog processing circuitry coupled to the rf circuitry. the analog processing circuitry is configured to generate spatially compressed beamspace domain analog signals from the analog baseband signals.
20250211315. HIGH-ISOLATION DUAL-FEED ANTENNA INTEGRATED STEERING SYSTEM (Intel)
Abstract: a mobile device comprising multi-feed antennas having high feed-to-feed isolation and high antenna-to-antenna isolation. rf transceiver circuitry can couple to the antennas through passive elements to form rf chains. connectivity circuitry coupled to the rf circuitry can detect communication-related data and perform antenna control functions based on the communication-related data by providing a digital control signal to modify magnitude and phase of the rf chains. no separate antenna controls, apart from the connectivity circuitry, is provided in the mobile device.
Abstract: a communication device is provided including a first radio configured to determine a position of another communication device, wherein the first radio is a wideband near-field communication radio; and a second radio configured to form a communication link with the other communication device, wherein the second radio is a wireless local area network radio configured to generate a directional beam to form the communication link based on a parameter set; and an interface controller configured to determine the parameter set based on the determined position of the other communication device and to provide the parameter set to the second radio.
20250211416. COMPUTE ENGINE CONTROL BLOCK (CCB) DISTRIBUTED DATA WORD ARCHITECTURE (Intel)
Abstract: compute circuitry to perform fully homomorphic encryption (fhe) includes a memory system and a compute engine. the compute engine includes tiles organized in an array. the array of tiles in the compute engine provides compute elements to perform polynomial operations for polynomials. synchronization support is provided by a compute engine control block (ccb) in the compute circuitry. the compute engine control block decomposes large data word loads and stores (with data spread across memory channels) into smaller requests for each memory channel. the compute engine control block uses completion signals received from each memory channel to assess the completion state of the large data word load/store. the compute engine control block to manage instruction dispatch across all tiles in the array of tiles and to ensure the tiles in the compute engine to operate in lockstep to enable synchronization free communication between the tiles.
Abstract: examples include techniques for contention-free routing for number-theoretic-transform (ntt) or inverse-ntt (intt) computations routed through a parallel processing device. examples include a tile array that includes a plurality of tiles arranged in a 2-dimensional mesh interconnect-based architecture. each tile includes a plurality of compute elements configured to execute ntt or intt computations associated with a fully homomorphic encryption workload. contention-free routing to include use of grouped or compressed source addresses to be used in routing tables maintained at tiles of the tile array.
20250211421. Apparatus Method Attack-Resistant Encryption Decryption (Intel)
Abstract: an apparatus and method for attack-resistant encryption and decryption. for example, one embodiment of an apparatus comprises: execution circuitry to execute instructions and generate memory access requests including load requests to read data from memory and store requests to store data to memory; and cryptographic circuitry to perform a plurality of rounds of encryption or decryption to encrypt or decrypt the data, respectively, the cryptographic circuitry to perform one or more redundant rounds for a corresponding one or more of the plurality of rounds, the one or more redundant rounds to include spatial or temporal differences relative to the corresponding one or more rounds; the cryptographic circuitry to generate a fault upon detecting a mismatch between an output of a redundant round output and an output of a corresponding round.
20250211435. CONFIGURABLE VARIABLE-WORD SIZE XORSHIFT RANDOM NUMBER GENERATOR (Intel)
Abstract: efficient generation of uniform random numbers for fhe public key generation across varying prime numbers with different bit width is provided by configuring an xorshift linear feedback shift register (lfsr) based random number generator (rng) to optimal bit width while maintaining the uniformity properties. the prime value and corresponding xorshift rng tap locations are used to configure the xorshift lfsr based rng to generate the random numbers between [0, 2] where m is configured to generate the next power of 2 corresponding to a selected prime q value. the configuration of the xorshift lfsr based rng reduces the worst-case rejection rate from 100% to 50% across prime q values from 17 bits to 32 bits.
20250211459. VIRTUAL ENVIRONMENT MODIFICATIONS BASED USER BEHAVIOR OR CONTEXT (Intel)
Abstract: in one embodiment, a virtual environment is instantiated to provide a virtual two-dimensional or three-dimensional space in which a plurality of users can interact. interactions by the plurality of users within the virtual environment are classified, and a topic of interest for a particular user in the classified interactions is identified based on a topics of interest model for the particular user. a response action is then initiated in a local execution of the virtual environment presented to the particular user based on the identified topic of interest. the topics of interest model may be generated by content associated with the particular user, e.g., stored on a user device of the particular user or in a cloud storage account of the particular user.
20250211976. DEVICES METHODS AGAINST ADVERSARIAL ATTACKS WIRELESS COMMUNICATION SYSTEMS (Intel)
Abstract: an apparatus may include a trusted execution environment and a processor configured to execute a machine learning (ml)-based application within the trusted execution environment, the ml-based application is configured to provide an output based on input data comprising telemetry data and decrypt encrypted data received by the trusted execution environment to obtain the telemetry data of the network.
20250211984. HANDOVER CONNECTIVITY PRIVACY COMMUNICATION SYSTEMS (Intel)
Abstract: control devices for network control and privacy protection are described. for network control, processing circuitry can exchange information with at least one other device to determine which device should communicate to a peripheral device. the processing circuitry can pass a token to the at least one other device in response to detecting the at least one other device should communicate to the peripheral device, and refrain from further transmissions after passing the token. in privacy control, users can be notified before audio is played on a new or different peripheral device.
20250212013. METHODS APPARATUS IMPROVED CELL PLACEMENT (Intel)
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to improve cell placement in semiconductor dies. an apparatus includes interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to extract a gate-level netlist from a cell placement arrangement, the cell placement arrangement corresponding to cells on a semiconductor die, extract information from the gate-level netlist corresponding to an operation of the gate-level netlist, use unsupervised learning to learn an embedding for a node in the gate-level netlist, and update the cell placement arrangement based on the learned embedding of the node.
20250212015. WIRELESS COMMUNICATION DEVICE SYSTEM (Intel)
Abstract: a wireless communication device configured to provide an omnidirectional transmission mode and a directional transmission mode, the wireless communication device comprising: a processor configured to: determine an orientation of a part of a body of a user of the wireless communication device; determine a scanning region of a transceiver of the wireless communication device based on the determined orientation; instruct the transceiver to operate in the directional transmission mode to scan the scanning region; and detect one or more other wireless communication devices based on the scanning of the scanning region.
20250212083. INTELLIGENT USER BURST TRAFFIC HANDLING MOVING VIRTUAL NETWORK (Intel)
Abstract: a network device for use in an open radio access network (o-ran) base station or a network-side device for other radio access technology (rat) includes communication circuitry. the communication circuitry can receive communications from a user equipment (ue) or group of ues and from a plurality of cells. the network device can include processing circuitry coupled to the communication circuitry. the processing circuitry can receive data, over the communication circuitry, indicating a speed of the ue and data indicating a mobile cell speed of at least one of the plurality of cells. the processing circuitry receive an indication that the speed of the ue is within a threshold of the mobile cell speed and responsive to this indication, provide an instruction to the ue to connect to the mobile cell.
20250212111. METHODS DEVICES SELECTING RADIO COMMUNICATION NETWORK (Intel)
Abstract: a method for selecting a radio communication network may include determining a plurality of first and second radio communication networks available respectively for a first and second radio communication terminals, wherein the plurality of second radio communication networks is at least partially identical to the plurality of first radio communication networks, determining first and second link metrics for each of the first and second radio communication networks, the first and second link metrics representing a link quality for a respective link between a radio communication terminal and a radio communication network, selecting a radio communication network that is included in the plurality of first and second radio communication networks based on the first and second link metrics, and instructing the first and second radio communication terminals to establish a communication link to the selected radio communication network.
20250212182. RESOURCE ALLOCATION USER EQUIPMENT PAIRED PROCESSING (Intel)
Abstract: a network device for use in an open radio access network (o-ran) base station or a network-side device for other radio access technology (rat) includes communication circuitry. the communication circuitry can receive communications from a first user device for running a user application on a second user device. the network device can include processing circuitry coupled to the communication circuitry. the processing circuitry can determine a latency requirement for the user application. the processing circuitry can configure communication resources based on the latency requirement. the processing circuitry can configure communication of user application data based on the latency requirement and using the configured communication resources.
20250212193. TECHNIQUES SECURE WIRELESS INTERNET THINGS DEVICES (Intel)
Abstract: techniques to secure wireless internet of things (iot) devices are described. in one embodiment, a method comprises initiating scanning of a first frequency band used by a wireless digital key, the wireless digital key capable of communication with an electronic control unit (ecu) of a vehicle; detecting an indication of the wireless digital key operating in the first frequency band to communicate with the ecu of the vehicle; and generating a first instruction for the wireless digital key or a wireless device within a defined geographic area to switch from a first frequency range to a second frequency range. other embodiments are described and claimed.
20250212213. UE CONFIGURED DYNAMICALLY SCHEDULED PUCCH REPETITION PUCCH RESOURCE INDICATION (Intel)
Abstract: a ue configured for operation in a 5g nr network may decode rrc signalling from a generation gnb that includes a pucch-config ie to configure the ue with a number of slots for pucch repetition. the ue may decode a dci format scheduling dynamic pucch repetition per pucch resource when the dci format indicates a pucch resource for the pucch repetition. the pucch resource may include a repetition number of slot and may be indicated by the dci format comprising a starting symbol index and a number of symbols for repetition of the pucch within each of the slots of the number of slots. if the dci indicates the pucch resource that includes the repetition number of slots, the dci format schedules dynamic pucch repetition and the ue repeats the scheduled pucch transmission in accordance with the repetition number of slots per the pucch resource indicated by the dci format, otherwise, the ue repeats the scheduled pucch transmission in accordance with a repetition number indicated by the pucch-config ie. each repetition of the pucch may have the same first symbol corresponding to the starting symbol index in each slot and the same number of consecutive symbols in each slot corresponding to the number of symbols.
20250212244. METHODS DEVICES INCREASE CONNECTIVITY QUALITY EXPERIENCE (Intel)
Abstract: an apparatus of a radio communication device, the apparatus may include a processor configured to: determine a radiation pattern for a plurality of channels of a short-range wireless communication network, wherein the radiation pattern is representative of quality metrics for the plurality of channels at a plurality of directions relative to the radio communication device; determine a location of a further radio communication device; configure a parameter of a connection with the further radio communication device based on the radiation pattern and the location of the further radio communication device.
20250212312. PRINTED CIRCUIT BOARD BUILT-IN VAPOR CHAMBER (Intel)
Abstract: a printed circuit board, pcb, comprises a plurality of substrate layers. the pcb comprises a first laminate comprising a hot region of a vapor chamber, configured to absorb heat from at least one component coupled to an outermost substrate of the pcb. the pcb further comprises a second laminate comprising a cold region of the vapor chamber, configured to be a condensing substrate. additionally, the pcb comprises a middle laminate between the first and second laminates, the middle laminate comprising the vapor chamber.
20250212315. STRUCTURES REDUCING CROSSTALK INSIDE SHIELDED DEVICE (Intel)
Abstract: a system can include a communication chain to operate in a communication band. the communication chain can be mounted on a circuit board. the system can include a connectivity device coupled to the communication chain. the system can include a metal shield. the metal shield can have a shield perimeter and the metal shield can be disposed over at least a portion of the communication chain. the metal shield can have at least one formation formed within the shield perimeter for providing a connection between the metal shield and the circuit board.
20250212357. METHODS APPARATUS CONTROL AIRFLOW FOLDABLE COMPUTING DEVICES (Intel)
Abstract: methods and apparatus to control airflow in foldable computing devices are disclosed. a disclosed apparatus for use with a foldable computing device includes a barrier carried by at least one of a first folding portion or a second folding portion of the computing device, the first folding portion rotatable relative to the second folding portion, and an actuator to move the barrier in response to a rotation between the first and second folding portions to reduce a flow of air into the foldable computing device.
20250212365. HEAT DISSIPATION SYSTEMS ELECTRONIC DEVICES RELATED METHODS (Intel)
Abstract: heat dissipation systems, apparatus, articles of manufacture, and methods are disclosed. an example computing device includes a display, a keyboard, processor circuitry, and a dual-phase heat dissipation system. the dual-phase dissipation system includes a housing defining a chamber, a fluid inlet, and a fluid outlet. the chamber receives a working fluid via the fluid inlet. a pump fluidly couples to the fluid inlet and the fluid outlet of the housing. the pump is to receive the working fluid via the fluid outlet of the housing and increase at least one of a flow rate or volume of the working fluid at the fluid inlet.
Abstract: contacts to n-type and p-type source/drain regions of field-effect transistors comprise a doped contact metal layer positioned between the fill metal and the source/drain regions. the doped contact metal layer comprises a metal and a semiconductor dopant and is formed by reactive sputtering. by varying the concentration of a reactive gas comprising the dopant in the sputtering environment, the atomic composition of the dopant in the doped contact metal layer can vary as the doped contact metal layer is formed. the presence of doped contact metal layers in source/drain contacts can provide for thermally stable low resistance source/drain contacts by inhibiting dopant diffusion from the source/drain regions to the contact metal. in some embodiments, a non-doped contact metal layer can be positioned between the fill metal and the doped contact metal layer.
Abstract: integrated circuit structures having a metal gate cut plug and an alignment structure are described. for example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. a gate electrode is over the vertical stack of horizontal nanowires or the fin. a conductive trench contact is adjacent to the gate electrode. a dielectric sidewall spacer is between the gate electrode and the conductive trench contact. a dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and past the conductive trench contact. a semiconductor structure is adjacent to a side of the dielectric cut plug structure opposite the gate electrode, the dielectric sidewall spacer, and the conductive trench contact. a dielectric structure covers a top and sides of the semiconductor structure, the dielectric structure in contact with the side of the dielectric cut plug structure.
20250212463. METAL-ALL-AROUND CONTACT STRUCTURE COUPLED SOURCE OR DRAIN REGION (Intel)
Abstract: a fabrication method and associated integrated circuit (ic) structures and devices that include a metal-all-around contact structure coupled with an s/d region are described herein. in one example, an ic structure may include a region of a doped semiconductor material. an ic structure may include a stack of nanoribbons of a semiconductor material including first portions and second portions on either side of the region, wherein the first portions are in contact with a first side of the region and the second portions are in contact with a second side of the region. an ic structure may include a conductive material over portions of the region between the first side and the second side in a same layer as at least one of the nanoribbons of the stack.
20250212464. BILAYER CAVITY SPACER GATE-ALL-AROUND TRANSISTOR (Intel)
Abstract: described herein are nanoribbon transistors with bilayer cavity spacers deposited near the ends of the nanoribbons, including between the ends of adjacent nanoribbons. the cavity spacers include a first, inner layer next to the gate stack, and a second, outer layer next to the source or drain. the inner layer may be a low-k dielectric material, while the outer layer may be a high-k dielectric material.
20250212470. INTEGRATED CIRCUIT DEVICE BACKSIDE ISOLATON REGION (Intel)
Abstract: an ic device may have active regions and one or more isolation regions. the ic device includes gates that are in parallel. one or more semiconductor structures (e.g., fins, nanoribbons, etc.) may extend across each gate in the ic device. some of the gates are in the active regions. the other gates are in the isolation region. a gate in an active region may be between semiconductor regions, which may function as the source region and drain region of a transistor. a gate in an isolation region may be between insulator regions. the insulator regions may be formed from the backside of the ic device. for instance, semiconductor regions may be formed in both the active regions and the isolation regions. the semiconductor regions in the regions designated to be isolation regions may be removed from the backside and filled with one or more electrical insulators.
20250212471. BACKSIDE LOGIC INTERCONNECTS (Intel)
Abstract: techniques are provided herein to form an integrated circuit having a backside interconnect structure coupled between different transistor source or drain regions. the backside interconnect structure may be used to replace frontside local interconnect structures, thus freeing up more space in the frontside interconnect region. a first semiconductor device includes a first semiconductor region extending between a first source or drain region and a second source or drain region, and a second semiconductor device includes a second semiconductor region extending between a third source or drain region and a fourth source or drain region. each of the source or drain regions have corresponding backside contacts coupled to a bottom surface of the source or drain region. a backside conductive layer may extend beneath the semiconductor devices and be coupled to any of the backside contacts to provide connection between the corresponding source or drain regions.
20250212507. CMOS METAL CONTACTS DOPANT DIFFUSION BARRIERS (Intel)
Abstract: contacts to n-type and p-type source/drain regions in complementary metal-oxide semiconductor (cmos) technologies comprise a diffusion barrier layer positioned between the contact metal and the source/drain regions. the contact metal-diffusion barrier layer pairs used to contact n-type and p-type source/drain regions can comprise different materials. the contact metal layers used in n-type and p-type source/drain contacts can comprise the same or different materials. the presence of diffusion barrier layers can provide for thermally stable low resistance source/drain contacts by inhibiting dopant diffusion from the source/drain regions to the contact metal.
20250212522. CAPPING NANORIBBON FINS SUPERLATTICE STRUCTURES DURING FABRICATION (Intel)
Abstract: in embodiments herein, a cap layer (e.g., a layer comprising silicon) is deposited on a fin formed in a superlattice structure, e.g., during a fabrication process.
20250212525. INTEGRATED CIRCUIT STRUCTURES HAVING MULTI-HEIGHT CELLS (Intel)
Abstract: integrated circuit structures having multi-height cells, and methods of fabricating integrated circuit structures having multi-height cells, are described. for example, an integrated circuit structure includes a single height cell in a block, and a multi-height cell in the block, the multi-height cell having a single nmos diffusion area and a single pmos diffusion area, and the multi-height cell having a power rail above the single nmos diffusion area and the single pmos diffusion area, where the power rail is not shared between the multi-height cell and the single height cell. another integrated circuit structure includes a row of relatively taller cells with relatively wider 2-stack nanosheets, and a row of relatively shorter cells with relatively narrower 2-stack nanosheet, the row of relatively shorter cells coupled to the row of relatively taller cells.