SEMICONDUCTOR PACKAGE INCLUDING CONDUCTIVE POST AND METHOD OF MANUFACTURING THE SAME

Abstract: a semiconductor package includes: a first wiring structure including at least one first wiring pattern and a first insulating layer including the first wiring pattern therein; a second wiring structure including at least one second wiring pattern and a second insulating layer including the second wiring pattern therein; a semiconductor chip between the first wiring structure and the second wiring structure; a molding layer between the first wiring structure and the second wiring structure, the molding layer comprising the semiconductor chip therein; and a conductive post penetrating the molding layer and configured to electrically connect the first wiring structure to the second wiring structure, wherein the conductive post includes: a body extended through the molding layer in a vertical direction; and a bonding surface on a side surface of the body and having a greater roughness than an upper surface and a lower surface of the conductive post.

Inventor(s): Jing Cheng Lin, Youngkun Jee, Jongho Park, Jaemok Jung, Taeoh Ha

CPC Classification: H01L23/49838 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate )})

Search for rejections for patent application number 20250174541