20250166114. Architecture Block Spars (Intel)
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
Abstract: embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. one embodiment provides for data aware sparsity via compressed bitstreams. one embodiment provides for block sparse dot product instructions. one embodiment provides for a depth-wise adapter for a systolic array.
Inventor(s): Abhishek Appu, Subramaniam Maiyuran, Mike Macpherson, Fangwen Fu, Jiasheng Chen, Varghese George, Vasanth Ranganathan, Ashutosh Garg, Joydeep Ray
CPC Classification: G06T1/20 (Processor architectures; Processor configuration, e.g. pipelining)
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Categories:
- Patent Applications
- Intel Corporation
- CPC G06T1/20
- Abhishek Appu of El Dorado Hills CA US
- Subramaniam Maiyuran of Gold River CA US
- Mike Macpherson of Portland OR US
- Fangwen Fu of Folsom CA US
- Jiasheng Chen of El Dorado Hills CA US
- Varghese George of Folsom CA US
- Vasanth Ranganathan of El Dorado Hills CA US
- Ashutosh Garg of Folsom CA US
- Joydeep Ray of Folsom CA US