Micron technology, inc. (20250013376). POWER SAFETY CONFIGURATIONS FOR LOGICAL ADDRESS SPACE PARTITIONS: Difference between revisions
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==Inventor(s)== | ==Inventor(s)== | ||
[[:Category:David Aaron Palmer of Boise ID | [[:Category:David Aaron Palmer of Boise ID US|David Aaron Palmer of Boise ID US]][[Category:David Aaron Palmer of Boise ID US]] | ||
==POWER SAFETY CONFIGURATIONS FOR LOGICAL ADDRESS SPACE PARTITIONS== | ==POWER SAFETY CONFIGURATIONS FOR LOGICAL ADDRESS SPACE PARTITIONS== | ||
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This abstract first appeared for US patent application 20250013376 titled 'POWER SAFETY CONFIGURATIONS FOR LOGICAL ADDRESS SPACE PARTITIONS | This abstract first appeared for US patent application 20250013376 titled 'POWER SAFETY CONFIGURATIONS FOR LOGICAL ADDRESS SPACE PARTITIONS | ||
==Original Abstract Submitted== | ==Original Abstract Submitted== | ||
Latest revision as of 09:58, 25 March 2025
POWER SAFETY CONFIGURATIONS FOR LOGICAL ADDRESS SPACE PARTITIONS
Organization Name
Inventor(s)
David Aaron Palmer of Boise ID US
POWER SAFETY CONFIGURATIONS FOR LOGICAL ADDRESS SPACE PARTITIONS
This abstract first appeared for US patent application 20250013376 titled 'POWER SAFETY CONFIGURATIONS FOR LOGICAL ADDRESS SPACE PARTITIONS
Original Abstract Submitted
a system includes a memory device, and a processing device, operatively coupled to the memory device, to perform operations including obtaining, from a host system, a power safety configuration for a partition, wherein the power safety configuration for the partition configures the memory device to implement power safe writing for the partition by operating in a first write mode utilizing single level cell (slc) caching, or to implement non-power safe writing for the partition by operating in a second write mode without utilizing slc caching, and configuring the memory device to operate in the first write mode or the second write mode based on the power safety configuration.