Samsung electronics co., ltd. (20250006606). SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME: Difference between revisions
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==Inventor(s)== | ==Inventor(s)== | ||
[[:Category:HYUNJU Lee of Suwon-si | [[:Category:HYUNJU Lee of Suwon-si KR|HYUNJU Lee of Suwon-si KR]][[Category:HYUNJU Lee of Suwon-si KR]] | ||
[[:Category:GYUHO Kang of Suwon-si | [[:Category:GYUHO Kang of Suwon-si KR|GYUHO Kang of Suwon-si KR]][[Category:GYUHO Kang of Suwon-si KR]] | ||
[[:Category:SUNG KEUN Park of Suwon-si | [[:Category:SUNG KEUN Park of Suwon-si KR|SUNG KEUN Park of Suwon-si KR]][[Category:SUNG KEUN Park of Suwon-si KR]] | ||
[[:Category:KWANGOK Jeong of Suwon-si | [[:Category:KWANGOK Jeong of Suwon-si KR|KWANGOK Jeong of Suwon-si KR]][[Category:KWANGOK Jeong of Suwon-si KR]] | ||
[[:Category:JAEMOK Jung of Suwon-si | [[:Category:JAEMOK Jung of Suwon-si KR|JAEMOK Jung of Suwon-si KR]][[Category:JAEMOK Jung of Suwon-si KR]] | ||
[[:Category:JU-IL Choi of Suwon-si | [[:Category:JU-IL Choi of Suwon-si KR|JU-IL Choi of Suwon-si KR]][[Category:JU-IL Choi of Suwon-si KR]] | ||
==SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME== | ==SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME== | ||
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This abstract first appeared for US patent application 20250006606 titled 'SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME | This abstract first appeared for US patent application 20250006606 titled 'SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME | ||
==Original Abstract Submitted== | ==Original Abstract Submitted== | ||
Latest revision as of 02:48, 25 March 2025
SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
This abstract first appeared for US patent application 20250006606 titled 'SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
Original Abstract Submitted
a semiconductor package may include: a substrate; a seed layer on a first surface of the substrate; a pad on the seed layer and including a first metal layer and a second metal layer on the first metal layer; an insulating layer on the first surface and including a side surface in contact with the second metal layer; and a semiconductor chip above a second surface of the substrate. an interface between the side surface of the insulating layer and the second metal layer may be nonplanar.
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