Samsung electronics co., ltd. (20250069979). SEMICONDUCTOR PACKAGE: Difference between revisions
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[[Category:samsung electronics co., ltd.]] | [[Category:samsung electronics co., ltd.]] | ||
==Inventor(s)== | |||
[[:Category:Eunseok Cho of Asan-si (KR)|Eunseok Cho of Asan-si (KR)]][[Category:Eunseok Cho of Asan-si (KR)]] | |||
[[:Category:Minjeong Gu of Asan-si (KR)|Minjeong Gu of Asan-si (KR)]][[Category:Minjeong Gu of Asan-si (KR)]] | |||
[[:Category:Joonsung Kim of Suwon-si (KR)|Joonsung Kim of Suwon-si (KR)]][[Category:Joonsung Kim of Suwon-si (KR)]] | |||
[[:Category:Jaehoon Choi of Seoul (KR)|Jaehoon Choi of Seoul (KR)]][[Category:Jaehoon Choi of Seoul (KR)]] | |||
==SEMICONDUCTOR PACKAGE== | |||
This abstract first appeared for US patent application 20250069979 titled 'SEMICONDUCTOR PACKAGE | |||
==Original Abstract Submitted== | |||
a method of manufacturing a semiconductor package is provided and includes: forming a lower redistribution structure, the lower redistribution structure including lower redistribution patterns having lower connection pads; forming an upper redistribution structure on a boundary surface of the lower redistribution structure, the upper redistribution structure including upper redistribution patterns having upper connection pads electrically connected to the lower connection pads; forming openings exposing at least a portion of each of the lower connection pads; disposing an interposer substrate, including the lower redistribution structure and the upper redistribution structure, on a base substrate, the lower connection pads of the interposer substrate electrically connected to wiring patterns of the base substrate through lower connection bumps disposed on the openings; and disposing at least one of semiconductor chips, including connection pads, on the interposer substrate, the connection pads electrically connected to the upper connection pads through upper connection bumps. | |||
[[Category:H01L23/367]] | |||
[[Category:H01L21/48]] | |||
[[Category:H01L21/56]] | |||
[[Category:H01L23/00]] | |||
[[Category:H01L23/31]] | |||
[[Category:H01L23/498]] | |||
[[Category:H01L23/552]] | |||
[[Category:H01L25/065]] | |||
[[Category:H01L25/18]] | |||
[[Category:CPC_H01L23/3675]] | |||
Latest revision as of 06:59, 17 March 2025
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE
This abstract first appeared for US patent application 20250069979 titled 'SEMICONDUCTOR PACKAGE
Original Abstract Submitted
a method of manufacturing a semiconductor package is provided and includes: forming a lower redistribution structure, the lower redistribution structure including lower redistribution patterns having lower connection pads; forming an upper redistribution structure on a boundary surface of the lower redistribution structure, the upper redistribution structure including upper redistribution patterns having upper connection pads electrically connected to the lower connection pads; forming openings exposing at least a portion of each of the lower connection pads; disposing an interposer substrate, including the lower redistribution structure and the upper redistribution structure, on a base substrate, the lower connection pads of the interposer substrate electrically connected to wiring patterns of the base substrate through lower connection bumps disposed on the openings; and disposing at least one of semiconductor chips, including connection pads, on the interposer substrate, the connection pads electrically connected to the upper connection pads through upper connection bumps.