View source for Taiwan semiconductor manufacturing company, ltd. (20250140743). CHIP STACKING STRUCTURE

<!-- JSON-LD markup for search engines:
{"@context":"https://schema.org","@type":"TechArticle","headline":"CHIP STACKING STRUCTURE","name":"CHIP STACKING STRUCTURE","description":"a structure including a first semiconductor die, second semiconductor dies, a bridge die, and a gap filling material is provided. the first semiconductor die includes integrated circuit regions. the s...","datePublished":"May 1st, 2025","mainEntity":{"@type":"Patent","identifier":"20250140743","name":"CHIP STACKING STRUCTURE","abstract":"a structure including a first semiconductor die, second semiconductor dies, a bridge die, and a gap filling material is provided. the first semiconductor die includes integrated circuit regions. the second semiconductor dies are disposed over and electrically connected to the first semiconductor die. the bridge die is disposed over and electrically connected to the first semiconductor die, and the integrated circuit regions are electrically connected to each other through the bridge die. the gap filling material is disposed on the first semiconductor die to laterally encapsulate the bridge die and the second semiconductor dies.","applicationNumber":"20250140743","datePublished":"May 1st, 2025","inventor":[{"@type":"Person","name":"Sheng-An Kuo"},{"@type":"Person","name":"Chao-Wen Shih"},{"@type":"Person","name":"Kuo-Chiang Ting"},{"@type":"Person","name":"Yen-Ming Chen"}],"applicant":{"@type":"Organization","name":"taiwan semiconductor manufacturing company, ltd."},"additionalProperty":[{"@type":"PropertyValue","name":"IPC Classification","value":"H01L25/065"},{"@type":"PropertyValue","name":"IPC Classification","value":"H01L23/00"},{"@type":"PropertyValue","name":"IPC Classification","value":"H01L23/31"},{"@type":"PropertyValue","name":"IPC Classification","value":"H01L23/48"},{"@type":"PropertyValue","name":"IPC Classification","value":"H01L23/522"},{"@type":"PropertyValue","name":"IPC Classification","value":"H01L23/538"},{"@type":"PropertyValue","name":"CPC Classification","value":"H01L25/0652"}]}}
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=CHIP STACKING STRUCTURE=


==Organization Name==

[[:Category:taiwan semiconductor manufacturing company, ltd.|taiwan semiconductor manufacturing company, ltd.]]


[[Category:taiwan semiconductor manufacturing company, ltd.]]

==Inventor(s)==

[[:Category:Sheng-An Kuo of Hsinchu TW|Sheng-An Kuo of Hsinchu TW]][[Category:Sheng-An Kuo of Hsinchu TW]]

[[:Category:Chao-Wen Shih of Hsinchu County TW|Chao-Wen Shih of Hsinchu County TW]][[Category:Chao-Wen Shih of Hsinchu County TW]]

[[:Category:Kuo-Chiang Ting of Hsinchu City TW|Kuo-Chiang Ting of Hsinchu City TW]][[Category:Kuo-Chiang Ting of Hsinchu City TW]]

[[:Category:Yen-Ming Chen of Hsin-Chu County TW|Yen-Ming Chen of Hsin-Chu County TW]][[Category:Yen-Ming Chen of Hsin-Chu County TW]]

==CHIP STACKING STRUCTURE==


This abstract first appeared for US patent application 20250140743 titled 'CHIP STACKING STRUCTURE

==Original Abstract Submitted==

a structure including a first semiconductor die, second semiconductor dies, a bridge die, and a gap filling material is provided. the first semiconductor die includes integrated circuit regions. the second semiconductor dies are disposed over and electrically connected to the first semiconductor die. the bridge die is disposed over and electrically connected to the first semiconductor die, and the integrated circuit regions are electrically connected to each other through the bridge die. the gap filling material is disposed on the first semiconductor die to laterally encapsulate the bridge die and the second semiconductor dies.



[[Category:H01L25/065]]
[[Category:H01L23/00]]
[[Category:H01L23/31]]
[[Category:H01L23/48]]
[[Category:H01L23/522]]
[[Category:H01L23/538]]
[[Category:CPC_H01L25/0652]]