View source for 19018452. Transient Stabilized SOI FETs (pSemi Corporation)

<!-- JSON-LD markup for search engines:
{"@context":"https://schema.org","@type":"TechArticle","headline":"Transient Stabilized SOI FETs","name":"Transient Stabilized SOI FETs","description":"Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one emb...","datePublished":"2025-01-13","mainEntity":{"@type":"Patent","identifier":"19018452","name":"Transient Stabilized SOI FETs","abstract":"Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same Vas during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same Vas during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a \u201ctrickle current\u201d state) that keeps both Vand Vclose to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.","applicationNumber":"19018452","datePublished":"2025-01-13","inventor":[{"@type":"Person","name":"Robert Mark Englekirk"},{"@type":"Person","name":"Keith Bargroff"},{"@type":"Person","name":"Christopher C. Murphy"},{"@type":"Person","name":"Tero Tapio Ranta"},{"@type":"Person","name":"Simon Edward Willard"}],"applicant":{"@type":"Organization","name":"pSemi Corporation"},"additionalProperty":[{"@type":"PropertyValue","name":"IPC Classification","value":"H01L23/60"},{"@type":"PropertyValue","name":"IPC Classification","value":"H01L21/762"},{"@type":"PropertyValue","name":"IPC Classification","value":"H01L23/552"},{"@type":"PropertyValue","name":"IPC Classification","value":"H01L23/66"},{"@type":"PropertyValue","name":"IPC Classification","value":"H03K17/0412"},{"@type":"PropertyValue","name":"IPC Classification","value":"H03K17/0416"},{"@type":"PropertyValue","name":"IPC Classification","value":"H03K17/042"},{"@type":"PropertyValue","name":"IPC Classification","value":"H03K17/14"},{"@type":"PropertyValue","name":"IPC Classification","value":"H03K17/687"},{"@type":"PropertyValue","name":"IPC Classification","value":"H10D30/67"},{"@type":"PropertyValue","name":"IPC Classification","value":"H10D62/17"},{"@type":"PropertyValue","name":"IPC Classification","value":"H10D86/00"},{"@type":"PropertyValue","name":"IPC Classification","value":"H10D86/40"},{"@type":"PropertyValue","name":"IPC Classification","value":"H10D86/60"},{"@type":"PropertyValue","name":"IPC Classification","value":"H10D87/00"},{"@type":"PropertyValue","name":"CPC Classification","value":"H01L23/60"}]}}
-->

=Transient Stabilized SOI FETs=


==Organization Name==

[[:Category:pSemi Corporation|pSemi Corporation]]


[[Category:pSemi Corporation]]

==Inventor(s)==

[[:Category:Robert Mark Englekirk of Littleton CO US|Robert Mark Englekirk of Littleton CO US]][[Category:Robert Mark Englekirk of Littleton CO US]]

[[:Category:Keith Bargroff of San Diego CA US|Keith Bargroff of San Diego CA US]][[Category:Keith Bargroff of San Diego CA US]]

[[:Category:Christopher C. Murphy of Lake Zurich IL US|Christopher C. Murphy of Lake Zurich IL US]][[Category:Christopher C. Murphy of Lake Zurich IL US]]

[[:Category:Tero Tapio Ranta of San Diego CA US|Tero Tapio Ranta of San Diego CA US]][[Category:Tero Tapio Ranta of San Diego CA US]]

[[:Category:Simon Edward Willard of Irvine CA US|Simon Edward Willard of Irvine CA US]][[Category:Simon Edward Willard of Irvine CA US]]

==Transient Stabilized SOI FETs==


This abstract first appeared for US patent application 19018452 titled 'Transient Stabilized SOI FETs

==Original Abstract Submitted==

Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same Vas during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same Vas during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both Vand Vclose to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.



[[Category:H01L23/60]]
[[Category:H01L21/762]]
[[Category:H01L23/552]]
[[Category:H01L23/66]]
[[Category:H03K17/0412]]
[[Category:H03K17/0416]]
[[Category:H03K17/042]]
[[Category:H03K17/14]]
[[Category:H03K17/687]]
[[Category:H10D30/67]]
[[Category:H10D62/17]]
[[Category:H10D86/00]]
[[Category:H10D86/40]]
[[Category:H10D86/60]]
[[Category:H10D87/00]]
[[Category:CPC_H01L23/60]]