View source for 18478831. SELECTIVE LAYER TRANSFER PROCESS IMPROVEMENTS (INTEL CORPORATION)

=SELECTIVE LAYER TRANSFER PROCESS IMPROVEMENTS=


==Organization Name==

[[:Category:INTEL CORPORATION|INTEL CORPORATION]]


[[Category:INTEL CORPORATION]]

==Inventor(s)==

[[:Category:Brandon M. Rawlings of Chandler AZ US|Brandon M. Rawlings of Chandler AZ US]][[Category:Brandon M. Rawlings of Chandler AZ US]]

[[:Category:Adel Elsherbini of Chandler AZ US|Adel Elsherbini of Chandler AZ US]][[Category:Adel Elsherbini of Chandler AZ US]]

[[:Category:Thomas L. Sounart of Chandler AZ US|Thomas L. Sounart of Chandler AZ US]][[Category:Thomas L. Sounart of Chandler AZ US]]

[[:Category:Feras Eid of Chandler AZ US|Feras Eid of Chandler AZ US]][[Category:Feras Eid of Chandler AZ US]]

[[:Category:Tushar Kanti Talukdar of Wilsonville OR US|Tushar Kanti Talukdar of Wilsonville OR US]][[Category:Tushar Kanti Talukdar of Wilsonville OR US]]

[[:Category:Kimin Jun of Portland OR US|Kimin Jun of Portland OR US]][[Category:Kimin Jun of Portland OR US]]

[[:Category:Johanna Swan of Scottsdale AZ US|Johanna Swan of Scottsdale AZ US]][[Category:Johanna Swan of Scottsdale AZ US]]

[[:Category:Richard F. Vreeland of Beaverton OR US|Richard F. Vreeland of Beaverton OR US]][[Category:Richard F. Vreeland of Beaverton OR US]]

==SELECTIVE LAYER TRANSFER PROCESS IMPROVEMENTS==


This abstract first appeared for US patent application 18478831 titled 'SELECTIVE LAYER TRANSFER PROCESS IMPROVEMENTS

==Original Abstract Submitted==

In one embodiment, a selective layer transfer process includes forming a layer of integrated circuit (IC) components on a first substrate, forming first bonding structures on a second substrate, and partially bonding the first substrate to the second substrate, which includes bonding a first subset of IC components on the first substrate to respective bonding structures on the second substrate. The process also includes forming second bonding structures on a third substrate, where the second bonding structures are arranged in a layout that is offset from the layout of the second substrate. The process further includes partially bonding the first substrate to the third substrate, which includes bonding a second subset of IC components on the first substrate to respective bonding structures on the third substrate.



[[Category:H01L25/00]]
[[Category:H01L21/683]]
[[Category:H01L25/075]]
[[Category:CPC_H01L25/50]]