View source for 18232442. PROCESSOR AND METHOD OF DETECTING SOFT ERROR FROM PROCESSOR simplified abstract (Samsung Electronics Co., Ltd.)

=PROCESSOR AND METHOD OF DETECTING SOFT ERROR FROM PROCESSOR=


==Organization Name==

[[:Category:Samsung Electronics Co., Ltd.|Samsung Electronics Co., Ltd.]]


[[Category:Samsung Electronics Co., Ltd.]]

==Inventor(s)==

[[:Category:TAESUN Kim of SUWON-SI (KR)|TAESUN Kim of SUWON-SI (KR)]][[Category:TAESUN Kim of SUWON-SI (KR)]]

[[:Category:JINHONG Park of SUWON-SI (KR)|JINHONG Park of SUWON-SI (KR)]][[Category:JINHONG Park of SUWON-SI (KR)]]

[[:Category:HWISOO So of SEOUL (KR)|HWISOO So of SEOUL (KR)]][[Category:HWISOO So of SEOUL (KR)]]

[[:Category:KYOUNGWOO Lee of SEOUL (KR)|KYOUNGWOO Lee of SEOUL (KR)]][[Category:KYOUNGWOO Lee of SEOUL (KR)]]

[[:Category:JINHYO Jung of Seoul (KR)|JINHYO Jung of Seoul (KR)]][[Category:JINHYO Jung of Seoul (KR)]]

==PROCESSOR AND METHOD OF DETECTING SOFT ERROR FROM PROCESSOR - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18232442 titled 'PROCESSOR AND METHOD OF DETECTING SOFT ERROR FROM PROCESSOR

==Simplified Explanation==

The processor described in the patent application includes an instruction pipeline that processes an original instruction and a duplicate instruction in sequence. The original instruction's result is stored in the original register file, while the duplicate instruction's result is stored in the duplicate register file. A comparing unit then checks for any discrepancies between the results stored in the two register files and outputs an error detection signal if needed.

* Instruction pipeline processing original and duplicate instructions sequentially
* Original register file storing result of original instruction
* Duplicate register file storing result of duplicate instruction
* Comparing unit checking for discrepancies between results in the two register files
* Error detection signal output in response to control signal

== Potential Applications ==
This technology could be applied in:
* High-performance computing systems
* Real-time processing applications
* Fault-tolerant systems

== Problems Solved ==
This technology helps in:
* Detecting errors in instruction processing
* Ensuring accuracy in results
* Enhancing system reliability

== Benefits ==
The benefits of this technology include:
* Improved error detection capabilities
* Enhanced system performance
* Increased reliability in processing instructions

== Potential Commercial Applications ==
Potential commercial applications of this technology could be in:
* Data centers
* Supercomputing facilities
* Aerospace and defense industries

== Possible Prior Art ==
One possible prior art for this technology could be:
* Error detection mechanisms in multi-core processors

=== Unanswered Questions ===

=== How does this technology impact power consumption in the processor? ===
This article does not address the potential impact of this technology on power consumption in the processor. 

=== What are the scalability limitations of this technology in terms of the number of instructions processed simultaneously? ===
This article does not discuss the scalability limitations of this technology in terms of the number of instructions processed simultaneously.


==Original Abstract Submitted==

A processor includes an instruction pipeline that sequentially processes an original instruction and a duplicate instruction, which is generated by duplicating the original instruction. An original register file stores a result obtained by processing the original instruction in the instruction pipeline within a register of a nindex thereof. A duplicate register file stores a result obtained by processing the duplicate instruction in the instruction pipeline within a register of a nindex thereof. A comparing unit compares the register of the nindex in the original register file with the register of nindex in the duplicate register file and outputs an error detection signal, in response to a control signal.



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