View source for 17830488. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

=SEMICONDUCTOR PACKAGE=


==Organization Name==

[[:Category:SAMSUNG ELECTRONICS CO., LTD.|SAMSUNG ELECTRONICS CO., LTD.]]


[[Category:SAMSUNG ELECTRONICS CO., LTD.]]

==Inventor(s)==

[[:Category:Yong Ho Kim of Hwaseong-si (KR)|Yong Ho Kim of Hwaseong-si (KR)]][[Category:Yong Ho Kim of Hwaseong-si (KR)]]

[[:Category:Woo Jin Jang of Seoul (KR)|Woo Jin Jang of Seoul (KR)]][[Category:Woo Jin Jang of Seoul (KR)]]

[[:Category:Jeong Hoon Ahn of Seongnam-si (KR)|Jeong Hoon Ahn of Seongnam-si (KR)]][[Category:Jeong Hoon Ahn of Seongnam-si (KR)]]

[[:Category:Yun Ki Choi of Yongin-si (KR)|Yun Ki Choi of Yongin-si (KR)]][[Category:Yun Ki Choi of Yongin-si (KR)]]

==SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17830488 titled 'SEMICONDUCTOR PACKAGE

==Simplified Explanation==

The patent application describes a semiconductor package that includes two chip substrates connected through a connection bump. The connection bump's width increases as it moves away from the first surface of the first chip substrate.

* The semiconductor package includes a first chip substrate with a through via passing through it.
* An upper passivation layer on the second surface of the first chip substrate exposes a portion of the second surface.
* An upper pad on the trench of the upper passivation layer is electrically connected to the through via.
* A second chip substrate with a lower pad is connected to the first chip substrate.
* The connection bump electrically connects the upper pad with the lower pad and widens as it moves away from the first chip substrate's surface.

== Potential Applications ==
* Semiconductor packaging industry
* Electronic devices manufacturing

== Problems Solved ==
* Improved electrical connection between chip substrates
* Enhanced performance and reliability of semiconductor packages

== Benefits ==
* Better electrical connectivity between chip substrates
* Increased performance and reliability of semiconductor packages
* Improved manufacturing efficiency and cost-effectiveness


==Original Abstract Submitted==

Provided is a semiconductor package including a first chip substrate including a first surface and a second surface, a through via passing through the first chip substrate, an upper passivation layer including a trench on the second surface of the first chip substrate, the trench exposing at least a portion of the second surface of the first chip substrate, an upper pad electrically connected with the through via on the trench, a second chip substrate including a third surface and a fourth surface, a lower pad electrically connected to the second chip substrate on the third surface of the second chip substrate, and a connection bump electrically connecting the upper pad with the lower pad and contacting the lower pad, wherein a width of the connection bump increases as the connection bump becomes farther away from the first surface of the first chip substrate.



[[Category:H01L23/00]]
[[Category:H01L25/065]]