Western Digital Technologies, Inc. patent applications on January 2nd, 2025
Patent Applications by Western Digital Technologies, Inc. on January 2nd, 2025
Western Digital Technologies, Inc.: 26 patent applications
Western Digital Technologies, Inc. has applied for patents in the areas of G06F3/06 (4), G11C16/34 (4), G11C29/12 (3), G11C16/10 (2), G11C16/16 (2) G11C29/12005 (2), B32B43/006 (1), G11B5/5526 (1), H04L47/6255 (1), H01S5/023 (1)
With keywords such as: data, memory, device, storage, configured, word, lines, erase, based, and side in patent application abstracts.
Patent Applications by Western Digital Technologies, Inc.
Inventor(s): Kok Kiong Chai of Sarawak (MY) for western digital technologies, inc., Siew Fu Chai of Sarawak (MY) for western digital technologies, inc., Samg Yin Tang of Sarawak (MY) for western digital technologies, inc.
IPC Code(s): B32B43/00
CPC Code(s): B32B43/006
Abstract: automatic separation of substrates from spacers within a substrate/spacer stack or laminate for use during a hard disk recording media fabrication process. in one example, a delamination apparatus includes a roller or brush configured to rotate while pressing against a flat surface of a substrate at one end of the laminate to peel the substrate from the laminate to expose an adjacent spacer and to then rotate against a flat surface of the spacer to peel the spacer from the laminate to expose another substrate of the laminate. the apparatus also includes a pusher bar configured to push against the opposite end of the laminate to push the laminate against the roller. the pusher bar may be offset from a central longitudinal axis of the laminate. a bath may be provided for submerging the laminate, the pusher, and the roller in a lubricating liquid. method embodiments are also described.
Inventor(s): Shoji Suzuki of San Jose CA (US) for western digital technologies, inc.
IPC Code(s): G01B21/08
CPC Code(s): G01B21/08
Abstract: methods and apparatus of identifying a substrate suitable for use within a magnetic medium of a data storage device configured for magnetic recording are described. in an aspect, the method includes identifying dimensions of a slider of the data storage device to be used in conjunction with the magnetic medium and determining a measurement length and a localized height threshold as a function of the dimensions of the slider. the method further includes measuring localized height values of the substrate at distances from a center of the substrate, each of the localized height values measured within the measurement length and at one of the distances, comparing the localized height values and the localized height threshold, and determining to utilize the substrate for the magnetic medium based on the comparison of the localized height values and the localized height threshold.
Inventor(s): Swarup Kulkarni of Bangalore (IN) for western digital technologies, inc., Sarabjot Singh of Bangalore (IN) for western digital technologies, inc., Pradeep Tiwari of Bangalore (IN) for western digital technologies, inc.
IPC Code(s): G06F1/20, G05B19/4155
CPC Code(s): G06F1/20
Abstract: methods and apparatus for thermal management in data storage devices are provided. a data storage device includes one or more components, at least one component temperature sensor configured to detect one or more component temperatures, one or more fans configured to reduce the one or more component temperatures, and a processor. the processor is configured to determine a type of each respective component of the one or more components, set a priority of a respective component of the one or more components based on the type of the respective component, assign a fan speed offset for operating at least one fan of the one or more fans corresponding to the respective component based on the priority of the respective component, and operate the at least one fan corresponding to the respective component according to the assigned fan speed offset based on preselected conditions.
Inventor(s): Amit Sharma of Bangalore (IN) for western digital technologies, inc., Dinesh Kumar Agarwal of Bangalore (IN) for western digital technologies, inc., Abhinandan Venugopal of Mysore (IN) for western digital technologies, inc.
IPC Code(s): G06F1/3234, G06F1/3212, G06F3/06
CPC Code(s): G06F1/3275
Abstract: techniques are provided for optimizing the power consumption of a data storage device included in a battery-operated device. the battery-operated device (e.g., portable devices like wearable devices, smartwatches, and mobile phones) can access certain data stored on the data storage device more frequently when the device operates on battery power as compared to when the device does not operate on battery power. techniques are provided for identifying and classifying data into different classifications, for example, power sensitive data and non-power sensitive data. then the device can optimize the battery power consumption of the data storage device by storing or relocating data stored at the data storage device based on the classification of the data.
Inventor(s): Amit Sharma of Bengaluru (IN) for western digital technologies, inc., Abhinandan Venugopal of Bengaluru (IN) for western digital technologies, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0634
Abstract: systems, methods, and data storage devices for dynamic mode selection for hybrid mlc/slc data storage devices are described. storage operations at a plurality of storage devices from a host device may be processed, wherein each storage device of the plurality of storage devices comprises a plurality of partitions including multi-level cell blocks and single-level cell blocks and multi-level cell blocks may be selectively written in a single-level write operation. a usage value is determined for each partition of the plurality of partitions at each storage device of the plurality of storage devices. a storage device of the plurality of storage devices may be dynamically selected based on the usage value for single-level cell blocks of the selected storage device having available single level cell blocks. new data may then be stored at the dynamically selected storage device of the plurality of storage devices.
Inventor(s): Ramanathan Muthiah of Bangalore (IN) for western digital technologies, inc., Daniel Joseph Linnen of Limestone (TN) for western digital technologies, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: a computational storage device (csd) is provided with a processor that obtains fixed point data having an initial precision (e.g., 32 bits per word) and determines a computation precision requirement for the fixed point data (such as a requirement for regular precision processing as opposed to low precision processing). the processor separates the fixed point data, based on the computational precision requirement, into a first group of bits, e.g., the most significant bits, and a second group of bits, e.g., the least significant bits, then separately stores the first the second groups of bits in the nvm array so that the different groups of bits can be fetched and managed separately. in this manner, bitwise grouping of fixed point data may be exploited to facilitate low precision processing when it is sufficient, while also accommodating full or regular precision processing when needed. various methods are also described.
Inventor(s): Ramanathan Muthiah of Bangalore (IN) for western digital technologies, inc., Sundararajan Rajagopal of Bangalore (IN) for western digital technologies, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a data storage device comprising a data port, configured to transceive data via a wired communication channel, a control port, configured to transceive data via a peer-to-peer wireless communication channel, a non-volatile storage medium, and a controller. in response to receiving, from a user device, via the control port, a command to enable control channel access, the controller performs an unlocking process, and, in response to completing the unlocking process, transitions from a locked state to a control channel access state. in response to being in the control channel access state, and in response to receiving, from the user device, via the control port, a write command, the controller stores write data in the storage medium, and, in response to receiving, from a host computer, via the data port, a command to access the storage medium, the controller transmits, to the host computer, a locked state indication.
Inventor(s): Marjan Radi of San Jose CA (US) for western digital technologies, inc., Dejan Vucinic of San Jose CA (US) for western digital technologies, inc.
IPC Code(s): G06F9/455
CPC Code(s): G06F9/45558
Abstract: a server includes at least one local memory used as a portion of a shared memory. the server communicates with network devices that are each configured to provide a respective shared memory via a network. a virtual switching (vs) kernel module executed in a kernel space of the server receives a packet from a virtual machine (vm) executed by the at least one processor or by a processor of a remote server and parses the packet to identify a memory request from an application executed by the vm. memory usage information is determined for the application based at least in part on the identified memory request. the memory usage information is provided to a vs controller of the server, which adjusts at least one of a memory request rate and a memory allocation for the application based at least in part on the determined memory usage information.
Inventor(s): Pavan Gururaj of Bangalore (IN) for western digital technologies, inc., Dinesh Babu of Bangalore (IN) for western digital technologies, inc., Sridhar Sabesan of Bangalore (IN) for western digital technologies, inc.
IPC Code(s): G06F12/02, G06F12/0891
CPC Code(s): G06F12/0253
Abstract: systems, methods, and data storage devices for management of key-value delete operations for namespaces supporting multiple hosts are described. responsive to a delete command, the key for the deleted key-value pair may be moved to a deleted data structure having a delete order. during garbage collection erase blocks corresponding to the key-value pairs may be invalidated based on the delete order and removed from the deleted data structure.
Inventor(s): Rewa Prasad Ahirwar of Bangalore (IN) for western digital technologies, inc., Ramanathan Muthiah of Bangalore (IN) for western digital technologies, inc.
IPC Code(s): G06F12/14
CPC Code(s): G06F12/1458
Abstract: a computer implemented method for transferring data from a user device to a non-volatile storage medium of a data storage device via a wireless peer-to-peer communication channel. the method executing on a user device comprising a user interface and memory store. the method comprises establishing a wireless peer-to-peer control channel between the user device and the data storage device. in response to receiving, via the user interface, a request to transfer data from the user device to the storage medium, sending, to the data storage device, via the control channel, a command to enable control channel access, and performing a secure unlocking process to transition the data storage device to a control channel access state. in response to successfully completing the secure unlocking process, obtaining write data, and sending, to the data storage device, via the control channel, a write command comprising the write data.
Inventor(s): Sukumar Rajauria of San Jose CA (US) for western digital technologies, inc., Erhard Schreck of San Jose CA (US) for western digital technologies, inc., Dongying Li of San Jose CA (US) for western digital technologies, inc.
IPC Code(s): G11B5/02, G01K7/16
CPC Code(s): G11B5/02
Abstract: a data storage device may include a disk, an actuator arm assembly comprising a magnetic recording head, a laser diode, and one or more processing devices configured to: initiate a write operation, wherein the write operation is associated with a first temperature of the laser diode; measure a resistance of the laser diode, wherein the resistance corresponds to a temperature of the laser diode; detect, based at least in part on measuring the resistance, a change in the temperature of the laser diode relative to the first temperature; and in response to detecting the change, adjust the temperature of the laser diode during the write operation.
Inventor(s): Quang LE of San Jose CA (US) for western digital technologies, inc., Xiaoyong LIU of San Jose CA (US) for western digital technologies, inc., Cherngye HWANG of San Jose CA (US) for western digital technologies, inc., Brian R. YORK of San Jose CA (US) for western digital technologies, inc., Son T. LE of San Jose CA (US) for western digital technologies, inc., Sharon Swee Ling BANH of San Jose CA (US) for western digital technologies, inc., Maki MAEDA of Fujisawa-shi (JP) for western digital technologies, inc., Fan TUO of Fujisawa-shi (JP) for western digital technologies, inc., Yu TAO of Fujisawa-shi (JP) for western digital technologies, inc., Hisashi TAKANO of Fujisawa-shi (JP) for western digital technologies, inc., Nam Hai PHAM of Tokyo (JP) for western digital technologies, inc.
IPC Code(s): G11B5/39
CPC Code(s): G11B5/3909
Abstract: the present disclosure generally relates to a magnetic media drive comprising a magnetic recording head. the magnetic recording head comprises a main pole disposed at a media facing surface (mfs), a shield disposed at the mfs, a spin blocking layer disposed between the shield and the main pole, at least one non-magnetic layer disposed between the main pole and the shield, the at least one non-magnetic layer being disposed at the mfs, and at least one spin orbit torque (sot) layer disposed over the at least one non-magnetic layer, the sot layer being recessed a distance of about 20 nm to about 100 nm from the mfs. a ratio of a length of the sot layer to a thickness of the sot layer is greater than 1. the at least one sot layer comprises bisb.
Inventor(s): Kohichiroh Naka of Fujisawa-shi (JP) for western digital technologies, inc., Yuhsuke Matsumoto of Fujisawa-shi (JP) for western digital technologies, inc., Hiroto Sato of Fujisawa-shi (JP) for western digital technologies, inc.
IPC Code(s): G11B5/48
CPC Code(s): G11B5/4846
Abstract: disclosed herein is a magnetic storage device that comprises a suspension arm co-movably fixed to a carriage arm. the suspension arm comprises a slider attachment side and at least one first electrical contact pad on the slider attachment side. the suspension arm also comprises a slider co-movably fixed to the suspension arm. the slider comprises a suspension attachment side, a non-head side facing the suspension arm and intersecting the suspension attachment side at a first slider edge of the slider, a head side facing away from the suspension arm, and at least one electrical contact component on the suspension attachment side up to the first slider edge. at least one solder weldment is directly coupled to the at least one first electrical contact pad and the at least one electrical contact component. additionally, a read-write head is coupled to the head side of the slider.
Inventor(s): Robert G. BISKEBORN of Hollister CA (US) for western digital technologies, inc., David J. SEAGLE of Morgan Hill CA (US) for western digital technologies, inc., Diane L. BROWN of San Jose CA (US) for western digital technologies, inc., Trevor W. OLSON of San Jose CA (US) for western digital technologies, inc.
IPC Code(s): G11B5/55
CPC Code(s): G11B5/5526
Abstract: the present disclosure generally relates to a tape drive comprising one or more tape head modules. each tape head module comprises 65 data elements disposed in a first row, each data element being a write element or a read element, and at least 5 servo element pairs disposed in a second row, the second row being disposed parallel to the first row. the second row is spaced a distance in a first direction from the first row. one or more data elements and one or more servo element pairs may be unwired and non-operable. the tape drive may comprise three tape head modules, where the second tape head module is disposed between the first and third tape head modules. each data element of the first tape head module and the third tape head module are write elements, and each data element of the second module is a read element.
Inventor(s): Mohan Vamsi Dunga of Santa Clara CA (US) for western digital technologies, inc., Xiang Yang of Santa Clara CA (US) for western digital technologies, inc.
IPC Code(s): G11C11/4074, G11C16/16, G11C16/24, G11C16/26
CPC Code(s): G11C11/4074
Abstract: a memory apparatus and method of operation are provided. the apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes and configured to retain a threshold voltage corresponding to one of a plurality of data states. a control means is coupled to the plurality of word lines and the memory holes. the control means is configured to apply a plurality of pulses of a program voltage increasing in magnitude by a program step amount to selected ones of the plurality of word lines while applying at least one pass voltage to unselected ones of the plurality of word lines during a plurality of programming loops of a programming operation. the control means is also configured to adjust the at least one pass voltage based on the program voltage.
Inventor(s): Hua-Ling Hsu of Fremont CA (US) for western digital technologies, inc., Henry Chin of Fremont CA (US) for western digital technologies, inc., Yanwei He of Fremont CA (US) for western digital technologies, inc.
IPC Code(s): G11C16/10, G11C11/56, G11C16/34
CPC Code(s): G11C16/10
Abstract: the memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. the memory device also includes circuitry that is configured to program at least some of the plurality of memory cells of a selected word line of the plurality of word lines in at least one program loop of a programming operation. during the at least one program loop, the circuitry is configured to apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation. the circuitry is also configured to determine an output of the analog bitscan operation. the output is one of at least three options. the circuitry is further configured to control at least one programming parameter based on the output of the analog bitscan operation.
Inventor(s): Hua-Ling Hsu of Fremont CA (US) for western digital technologies, inc., Henry Chin of Fremont CA (US) for western digital technologies, inc., Yen-Lung Li of San Jose CA (US) for western digital technologies, inc., Yanwei He of Fremont CA (US) for western digital technologies, inc.
IPC Code(s): G11C16/34, G11C16/04, G11C16/14
CPC Code(s): G11C16/3436
Abstract: the memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. circuitry is configured to program at least some of the plurality of memory cells in a program loop or that is configured to erase at least some of the plurality of memory cells in an erase loop. during the program loop or the erase loop, the circuitry is configured to perform a verify operation and an analog bitscan operation. in the analog bitscan operation, the circuitry counts the memory cells that pass or that fail the verify operation. the circuitry is also configured to determine an output of the analog bitscan operation, the output being one of at least three options.
Inventor(s): Henry Chin of Fremont CA (US) for western digital technologies, inc., Hua-Ling Hsu of Fremont CA (US) for western digital technologies, inc., Yanwei He of Fremont CA (US) for western digital technologies, inc., Dong-II Moon of San Jose CA (US) for western digital technologies, inc.
IPC Code(s): G11C16/34, G11C16/08, G11C16/16
CPC Code(s): G11C16/3445
Abstract: the memory device includes a plurality of memory cells which are arranged in a plurality of word lines. the plurality of word lines includes a selected group of word lines to be erased in an erasing operation. the memory device also includes circuitry that is configured to erase the memory cells of the selected group of word lines in at least one erase loop. the at least one erase loop includes an erase pulse, an erase-verify operation, and an analog bitscan operation. the circuitry is configured to determine an output of the analog bitscan operation, the output being one of at least three options. the circuitry is also configured to set at least one erase parameter based on the output of the analog bitscan operation.
Inventor(s): Hua-Ling Hsu of Fremont CA (US) for western digital technologies, inc., Henry Chin of Fremont CA (US) for western digital technologies, inc., Yanwei He of Fremont CA (US) for western digital technologies, inc.
IPC Code(s): G11C16/34, G11C16/08, G11C16/10
CPC Code(s): G11C16/3459
Abstract: the memory device includes a plurality of memory cells that are arranged in word lines, including a selected word line. circuitry is configured to program at least some of the plurality of memory cells of the selected word line in at least one program loop of a programming operation. during the at least one program loop, the circuitry is configured to apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation. the circuitry is further configured to determine an output of the analog bitscan operation, the output being one of at least three options. the circuitry is also configured to control at least one programming parameter based on the output of the analog bitscan operation. the at least one programming parameter is an early program-verify termination parameter or a smart verify parameter.
Inventor(s): Abhijith Prakash of Milpitas CA (US) for western digital technologies, inc., Parth Amin of Livermore CA (US) for western digital technologies, inc., Xiang Yang of Santa Clara CA (US) for western digital technologies, inc.
IPC Code(s): G11C29/02, G11C29/12, G11C29/36
CPC Code(s): G11C29/022
Abstract: technology is disclosed herein for detecting evolved bad blocks in three-dimensional nand. the test may include a drain side erase that includes applying an erase voltage from the bit lines and a source side erase that includes applying an erase voltage from the source line(s). if the source side erase performed worse than the drain side erase this may indicate a defect near the source side of the block. for example, the source side erase may fail but the drain side erase may pass. as another example the source side erase may take at least a pre-determined number of additional erase pulses to pass than the drain side erase. if the block is found as having a defect the entire block could be marked bad or the defective region could be identified such that the defective region is no longer used.
Inventor(s): Xuan Tian of Shanghai (CN) for western digital technologies, inc., Liang Li of Shanghai (CN) for western digital technologies, inc., Dandan Yi of Shanghai (CN) for western digital technologies, inc., Jojo Xing of Shanghai (CN) for western digital technologies, inc., Vincent Yin of Shanghai (CN) for western digital technologies, inc.
IPC Code(s): G11C29/12, G11C29/24
CPC Code(s): G11C29/12005
Abstract: in addition to word line related short circuits within the blocks of the array structure of a non-volatile memory device, such as nand memory, word line related shorts can also occur in the routing for supplying the word lines of the memory blocks. depending on the layout of the routing, some shorts for the word lines associated with one block can affect other blocks of the memory array. in particular, if the routing of a pair of adjacent local supply lines are adjacent to a global supply line, a short between the pair of adjacent local supply lines for one block can lead, through the global supply line, to defects in another of the block. techniques are presented for detecting these layout related problematic word lines.
Inventor(s): Jiahui Yuan of Fremont CA (US) for western digital technologies, inc., Lito De La Rama of San Jose CA (US) for western digital technologies, inc.
IPC Code(s): G11C29/12, G11C29/46
CPC Code(s): G11C29/12005
Abstract: a non-volatile memory system tests for a voltage leak in any of multiple planes using a voltage being ramped up on selected word lines in the multiple planes. if no voltage leak is detected, then the system concurrently programs data into memory cells connected to the selected word lines in the multiple planes. if a voltage leak is detected in any of the planes, then the system separately tests each plane for the voltage leak at its respective selected word line in order to determine which plane is the source of the voltage leak, and then concurrently programs data into memory cells connected to the selected word lines in planes without the detected voltage leak while isolating the plane with the detected voltage leak.
Inventor(s): Nagesh Vodrahalli of Los Altos CA (US) for western digital technologies, inc., Chih Yang Li of Menlo Park CA (US) for western digital technologies, inc., Rama Kant Shukla of Saratoga CA (US) for western digital technologies, inc.
IPC Code(s): H01L25/065, H01L23/00, H01L23/48
CPC Code(s): H01L25/0657
Abstract: semiconductor dies in a stack of semiconductor dies are interconnected using metal lines instead of bond wires or through silicon vias (tsvs). the semiconductor dies in the stack are arranged in a stairstep configuration such that a step corner is defined between a top surface of a first semiconductor die in the stack and a sidewall of a second semiconductor die in the stack. a step ramp is formed in the step corner. the step ramp defines a slope that extends between the top surface of the first semiconductor die and a top surface of the second semiconductor die. a metal line is formed over a bond pad associated with the first semiconductor die, the step ramp and a bond pad associated with the second semiconductor die.
Inventor(s): Sukumar Rajauria of San Jose CA (US) for western digital technologies, inc., Erhard Schreck of San Jose CA (US) for western digital technologies, inc.
IPC Code(s): H01S5/023, G11B5/012, G11B5/29, G11B5/596, H01S5/06, H01S5/068
CPC Code(s): H01S5/023
Abstract: a data storage device may include one or more disks, an actuator arm assembly comprising one or more magnetic recording heads, at least one laser diode, and one or more processing devices configured to: set the at least one laser diode to a first temperature; apply a first forward bias and supply a first current to the at least one laser diode such that it is in a lasing state; measure, for the at least one laser diode, a first output corresponding to the first temperature and current; set the at least one laser diode to a second temperature; measure, for the at least one laser diode, a second output corresponding to the second temperature and the first current; and determine an output profile for the at least one laser diode, based at least in part on the respective output at the first temperature and the second temperature.
Inventor(s): Marjan Radi of San Jose CA (US) for western digital technologies, inc., Dejan Vucinic of San Jose CA (US) for western digital technologies, inc.
IPC Code(s): H04L47/625, H04L47/6275, H04L67/1097
CPC Code(s): H04L47/6255
Abstract: a processing node executes one or more applications that are allocated memory of at least one shared memory of one or more memory nodes via a network. packets including memory messages for memory nodes are enqueued into one or more transmission queues for sending the packets to the memory nodes. each packet is enqueued into a transmission queue according to the application issuing the memory message included in the packet. one or more time slots of a predetermined time period are assigned to a transmission queue for sending at least a portion of the packets enqueued in the transmission queue within the assigned one or more time slots. at least a portion of the packets from the transmission queue are sent during the one or more assigned time slots. in one aspect, time slots are assigned based on scheduling information from a network scheduling device.
Inventor(s): Lovish Singla of Bangalore (IN) for western digital technologies, inc., Shaheed Nehal A of Mysore (IN) for western digital technologies, inc.
IPC Code(s): H04N7/18, G06T7/292, G06V20/54
CPC Code(s): H04N7/181
Abstract: systems, video cameras, and methods for predictive adjustment of multi-camera surveillance video data capture based on graph maps are described. a plurality of networked video camera is deployed and represented in a graph map based on the video camera environment, with parent nodes corresponding to video cameras and child nodes corresponding to path intersections among the video cameras. when a video event is detected from video data for one of the video cameras, a video capture update message indicating a shared child node identifier is selectively sent to other video cameras to modify their video capture operations.
Inventor(s): Adarsh RAJASHEKHAR of Santa Clara CA (US) for western digital technologies, inc.,, Raghuveer S. MAKALA of Campbell CA (US) for western digital technologies, inc.,, Kartik SONDHI of Milpitas CA (US) for western digital technologies, inc.,
IPC Code(s): H10B43/27, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/35
CPC Code(s): H10B43/27
Abstract: a semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located on a semiconductor layer, a memory opening vertically extending through the alternating stack and the semiconductor layer, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, and a backside semiconductor source structure including a doped semiconductor material. the backside semiconductor source structure may be polycrystalline or single crystalline.
Inventor(s): Rahul SHARANGPANI of Fremont CA (US) for western digital technologies, inc.,, Raghuveer S. MAKALA of Campbell CA (US) for western digital technologies, inc.,, Fei ZHOU of San Jose CA (US) for western digital technologies, inc.,
IPC Code(s): H10B43/27, G11C16/04, H01L23/522, H01L23/528, H10B43/10, H10B43/35
CPC Code(s): H10B43/27
Abstract: a semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a memory film, a vertical semiconductor channel, and an aluminum nitride layer that laterally surrounds the memory film.
Inventor(s): Kartik SONDHI of Milpitas CA (US) for western digital technologies, inc.,, Raghuveer S. MAKALA of Campbell CA (US) for western digital technologies, inc.,, Adarsh RAJASHEKHAR of Santa Clara CA (US) for western digital technologies, inc.,, Senaka KANAKAMEDALA of San Jose CA (US) for western digital technologies, inc.,
IPC Code(s): H10B43/35, H01L23/00, H01L25/00, H01L25/065, H01L25/18, H10B43/27, H10B51/20, H10B51/30, H10B63/00, H10B80/00
CPC Code(s): H10B43/35
Abstract: a semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located on a semiconductor layer, a memory opening vertically extending through the alternating stack and the semiconductor layer, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, and a backside semiconductor source structure including a doped semiconductor material. the backside semiconductor source structure may be polycrystalline or single crystalline.
Western Digital Technologies, Inc. patent applications on January 2nd, 2025
- Western Digital Technologies, Inc.
- B32B43/00
- CPC B32B43/006
- Western digital technologies, inc.
- G01B21/08
- CPC G01B21/08
- G06F1/20
- G05B19/4155
- CPC G06F1/20
- G06F1/3234
- G06F1/3212
- G06F3/06
- CPC G06F1/3275
- CPC G06F3/0634
- CPC G06F3/0655
- CPC G06F3/0659
- G06F9/455
- CPC G06F9/45558
- G06F12/02
- G06F12/0891
- CPC G06F12/0253
- G06F12/14
- CPC G06F12/1458
- G11B5/02
- G01K7/16
- CPC G11B5/02
- G11B5/39
- CPC G11B5/3909
- G11B5/48
- CPC G11B5/4846
- G11B5/55
- CPC G11B5/5526
- G11C11/4074
- G11C16/16
- G11C16/24
- G11C16/26
- CPC G11C11/4074
- G11C16/10
- G11C11/56
- G11C16/34
- CPC G11C16/10
- G11C16/04
- G11C16/14
- CPC G11C16/3436
- G11C16/08
- CPC G11C16/3445
- CPC G11C16/3459
- G11C29/02
- G11C29/12
- G11C29/36
- CPC G11C29/022
- G11C29/24
- CPC G11C29/12005
- G11C29/46
- H01L25/065
- H01L23/00
- H01L23/48
- CPC H01L25/0657
- H01S5/023
- G11B5/012
- G11B5/29
- G11B5/596
- H01S5/06
- H01S5/068
- CPC H01S5/023
- H04L47/625
- H04L47/6275
- H04L67/1097
- CPC H04L47/6255
- H04N7/18
- G06T7/292
- G06V20/54
- CPC H04N7/181
- H10B43/27
- H10B41/10
- H10B41/27
- H10B41/35
- H10B43/10
- H10B43/35
- CPC H10B43/27
- Western digital technologies, inc.,
- H01L23/522
- H01L23/528
- H01L25/00
- H01L25/18
- H10B51/20
- H10B51/30
- H10B63/00
- H10B80/00
- CPC H10B43/35