Western Digital Technologies, Inc. patent applications on December 19th, 2024
Patent Applications by Western Digital Technologies, Inc. on December 19th, 2024
Western Digital Technologies, Inc.: 18 patent applications
Western Digital Technologies, Inc. has applied for patents in the areas of G06F3/06 (4), G11C16/04 (3), G11C16/08 (3), G11C16/10 (3), H03K19/18 (2) G06F3/0608 (1), G11C16/10 (1), H05K7/20209 (1), G11C29/44 (1), G11C16/30 (1)
With keywords such as: data, memory, voltage, device, read, cells, configured, storage, layer, and sot in patent application abstracts.
Patent Applications by Western Digital Technologies, Inc.
Inventor(s): Anamika Choudhary of Bangalore (IN) for western digital technologies, inc., Disha Sharma of Bangalore (IN) for western digital technologies, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0608
Abstract: a write pattern of a host device is used to dynamically determine when to initiate a garbage collection process on a data storage device. the write pattern of the host device is based on a number of i/o commands received from the host device and on a number of available memory blocks in the data storage device. if the write pattern of the host device indicates that fewer than a threshold number of memory blocks will be available after a predetermined number of additional i/o commands are received, the garbage collection process is initiated. an amount of valid data that is transferred from one memory location to another memory location during the garbage collection process is also dynamically determined. thus, a garbage collection process may be tailored to a specific host device.
Inventor(s): Julian VLAIKO of Kfar Saba IL (US) for western digital technologies, inc., Judah Gamliel HAHN of Ofra (IL) for western digital technologies, inc., Shay BENISTY of Beer Sheva (IL) for western digital technologies, inc., Ariel NAVON of Revava (IL) for western digital technologies, inc., Alexander BAZARSKY of Holon (IL) for western digital technologies, inc., Aki BLEYER of Givatayim (IL) for western digital technologies, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: in a storage system having a plurality of solid state drives (ssds), the performance of propagating data from a primary device to each secondary device may be improved using a dedicated high speed data channel in which data and commands associated with the data is sent from an upstream ssd to a downstream ssd. the data is also sent to the downstream ssd after a minimum amount of data has been programmed to the upstream ssd. the downstream ssd begins programming the data to its own memory device after receiving the data. the programming of data to each ssd of the storage system may be in parallel and at least partially concurrent with each other. data, commands, and control messages may be sent an upstream ssd via a serial bus or a universal asynchronous receiver-transmitter channel, such that the downstream data paths and the upstream data paths are distinct.
Inventor(s): Bharath Radhakrishnan of Georgetown (MY) for western digital technologies, inc., Daniel J. Linnen of Naperville IL (US) for western digital technologies, inc.
IPC Code(s): G06F3/06, G06F11/07
CPC Code(s): G06F3/0619
Abstract: post-write data management operations, such as refresh read, data scrub, and data relocation, are typically performed after a certain period of time has elapsed. however, performing such operations based on probability of access can provide advantages. so, in one example, a post-write data management operation is performed more frequently on relatively-warmer data than on relatively-colder data.
Inventor(s): Amit Sharma of Bangaluru (IN) for western digital technologies, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0664
Abstract: systems, methods, and data storage devices for using data storage device operational profiles for interface-based performance leveling are described. data storage devices are connected to a virtual storage manager using network or storage bus connections. comparisons of the data processing speed and interface speed of each data storage device and its connection may be used to determine an active device operational profile for each data storage device to reach a target aggregate performance. the device operational profiles may be sent to the data storage devices to change their operations, such as the handling of background processes.
Inventor(s): Pradeep Hegde of Bangalore (IN) for western digital technologies, inc., Akhilesh Yadav of Bangalore (IN) for western digital technologies, inc., Shivam Mishra of Bangalore (IN) for western digital technologies, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/10
Abstract: early detection of room temperature data retention (rtdr) phenomena in programmed metablocks of data storage devices. in one embodiment, a memory controller includes a memory interface configured to interface with a non-volatile memory and a controller. the controller is configured to program a metablock of the non-volatile memory. programming the metablock includes assigning the metablock to one of a plurality of thermal region tags (“trts”) associated with a respective one of a plurality of thermal regions. each trt is associated with a respective set of read parameters. the controller is further configured to perform a periodic trt update to detect a rtdr phenomena associated with the metablock. in response to determining that the threshold associated with the detection of a rtdr phenomena has been exceeded, the controller reassigns the metablock to a different one of the trts.
Inventor(s): ANANTHARAJ THALAIMALAI VANARAJ of San Jose CA (US) for western digital technologies, inc., Sai Gautham THOPPA of San Jose CA (US) for western digital technologies, inc., Dharmaraju MARENAHALLY KRISHNA of Bengaluru (IN) for western digital technologies, inc.
IPC Code(s): G06F11/14
CPC Code(s): G06F11/1451
Abstract: embodiments of the present technology provide non-volatile memory devices comprising memory dies that natively generate “exclusive or (xor) data pages” that can be used to recover data pages corrupted by uecc errors. through memory die native-xor data page generation, embodiments can recover data pages corrupted by uecc errors more efficiently, more rapidly, and with fewer resources than potential alternative technologies.
Inventor(s): Quang LE of San Jose CA (US) for western digital technologies, inc., Xiaoyong LIU of San Jose CA (US) for western digital technologies, inc., Brian R. YORK of San Jose CA (US) for western digital technologies, inc., Cherngye HWANG of San Jose CA (US) for western digital technologies, inc., Son T. LE of San Jose CA (US) for western digital technologies, inc., Hisashi TAKANO of Fujisawa-shi (JP) for western digital technologies, inc., Fan TUO of Fujisawa-shi (JP) for western digital technologies, inc., Hassan OSMAN of San Jose CA (US) for western digital technologies, inc., Nam Hai PHAM of Tokyo (JP) for western digital technologies, inc.
IPC Code(s): G11B5/31
CPC Code(s): G11B5/315
Abstract: the present disclosure generally relates to a magnetic recording head comprising a read head. the read head comprises a sensor disposed at a media facing surface (mfs) and a spin generator spaced from the sensor and recessed from the mfs. the sensor and spin generators are disposed on a non-magnetic layer. the sensor comprises a free layer and the spin generator comprises at least one spin orbit torque (sot) layer. the sot layer may comprise topological material such as bisb. the sensor is configured to detect a read signal using a first voltage lead and a second voltage lead. the spin generator is configured to inject spin current through the non-magnetic layer to the sensor using a first current lead and a second current lead. the shape of the non-magnetic layer is a triangular or trapezoidal shape to further concentrate spin current.
Inventor(s): Quang LE of San Jose CA (US) for western digital technologies, inc., Brian R. YORK of San Jose CA (US) for western digital technologies, inc., Sharon Swee Ling BANH of San Jose CA (US) for western digital technologies, inc., Hassan OSMAN of San Jose CA (US) for western digital technologies, inc., Hisashi TAKANO of Fujisawa-shi (JP) for western digital technologies, inc.
IPC Code(s): G11B5/39, G01R33/09, G11C11/16, H03K19/18, H10B61/00, H10N50/10, H10N50/85, H10N52/80
CPC Code(s): G11B5/3909
Abstract: the present disclosure generally relates to spintronic material stacks and devices. the various disclosed embodiments of ybipt based spin orbit torque (sot) stacks can be used for high temperature applications. disclosed herein are various buffer and/or interlayer configurations in spintronic stacks that can promote growth of ybipt in the (110) orientation, to promote a high spin hall angle (sha) in sot applications. one embodiment is a spintronic stack comprising a buffer layer comprising one or more layers, the one or more layers each individually comprising: mgo (100), tin (100), ta, nb, hfn, taw(110), taw(100), tawn, tawn, or heated ypt, an sot layer comprising ybipt in the (110) orientation, an interlayer comprising one or more of mgo, tawn, tawn, taw (110), taw(100), ypt (110), nifegen, nialn, nial, nifege, nialge, or hfn, and a ferromagnetic layer.
Inventor(s): Richard Galbraith of Rochester MN (US) for western digital technologies, inc., Jonas Goode of Lake Forest CA (US) for western digital technologies, inc., Niranjay Ravindran of Rochester MN (US) for western digital technologies, inc., Iouri Oboukhov of Rochester MN (US) for western digital technologies, inc.
IPC Code(s): G11B5/596, G11B20/10, G11B20/12
CPC Code(s): G11B5/59655
Abstract: example channel circuits, data storage devices, and methods for data read synchronization from phase modulated synchronization fields are described. a data synchronization detector may receive an oversampled digital read signal read from a synchronization field that uses a single written pattern to encode the start of data position, phase, and gain for the read channel. the write pattern may use a phase modulated carrier signal to encode a pseudo-random binary sequence indicating the start of data position.
Inventor(s): Robert G. BISKEBORN of Hollister CA (US) for western digital technologies, inc., Masahito KOBAYASHI of Fujisawa (JP) for western digital technologies, inc., Trevor W. OLSON of San Jose CA (US) for western digital technologies, inc.
IPC Code(s): G11B23/087, G11B5/584
CPC Code(s): G11B23/087
Abstract: the present disclosure generally relates to a captive tape drive comprising a tape head. the captive drive comprises an upper assembly, the upper assembly comprising a first tape, a first supply reel, a first take-up reel, and two or more rollers. the captive tape drive further comprises a lower assembly disposed below the upper assembly, the lower assembly comprising a second tape, a second supply reel, a second take-up reel, and two or more rollers. the tape head is disposed between the plurality of rollers, and is configured to move between the upper assembly and the lower assembly to access the first and second tapes. the tape head comprises one or more modules, each module comprising 64 writers and 64 readers. each module is configured to write data to the first and second tapes using the 64 writers and to read verify the newly written data using the 64 readers.
Inventor(s): Peng Wang of San Jose CA (US) for western digital technologies, inc., Jia Li of San Francisco CA (US) for western digital technologies, inc., Yihang Liu of Santa Clara CA (US) for western digital technologies, inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/08
CPC Code(s): G11C16/10
Abstract: the memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. the word lines are grouped in a plurality of layers. the memory device also includes circuitry that is configured to program the memory cells of a selected word line of the plurality of word lines. the circuitry is configured during programming to determine which layer of the plurality of layers the selected word line is located in. the circuitry is also configured to apply a programming voltage to the selected word line and apply pass voltages to a plurality of unselected word lines. for at least some of the unselected word lines, the pass voltage is a baseline pass voltage level that is adjusted by a layer-unique bias pass voltage.
Inventor(s): Panni Wang of San Jose CA (US) for western digital technologies, inc., Xiaojia Jia of San Jose CA (US) for western digital technologies, inc., Swaroop Kaza of San Jose CA (US) for western digital technologies, inc.
IPC Code(s): G11C16/10, G11C16/24, G11C16/26
CPC Code(s): G11C16/102
Abstract: a memory apparatus and method of operation are provided. the apparatus includes memory cells disposed in memory holes connected to bit lines. the memory cells retain a threshold voltage corresponding to data states. a control means applies a bit line voltage to the bit lines while determining whether the memory cells have the threshold voltage above one or more read levels associated with each of the data states in a first portion of a read operation. the control means groups the memory cells targeted for ones of the data states into data state groups based on the first portion of the read operation. the control means also supplies a near zero voltage to the bit lines coupled to the memory cells targeted for ones of the data states associated with at least one of the data state groups while reading the memory cells in subsequent portions of the read operation.
Inventor(s): Xiang Yang of Santa Clara CA (US) for western digital technologies, inc., Eric Fu of Sunnyvale CA (US) for western digital technologies, inc., Albert Chen of Milpitas CA (US) for western digital technologies, inc., Jonathan Huynh of San Jose CA (US) for western digital technologies, inc.
IPC Code(s): G11C16/12, G11C16/04, G11C16/08, G11C16/24
CPC Code(s): G11C16/12
Abstract: an apparatus comprising a set of memory cells and a control circuit coupled to the set of memory cells is disclosed. the control circuit is configured to: transition a wordline voltage of a wordline associated with a target memory cell of the set of memory cells from a first wordline voltage level to a second wordline voltage level; subsequent to transitioning the wordline voltage to the second wordline voltage level, ramp down a bitline voltage of a bitline associated with the target memory cell from a first bitline voltage level to a second bitline voltage level; and prior to sensing a state of the memory cell, ramp up the bitline voltage from the second bitline voltage level to the first bitline voltage level.
Inventor(s): Albert Chen of Milpitas CA (US) for western digital technologies, inc., Xiang Yang of Santa Clara CA (US) for western digital technologies, inc., Eric Fu of Sunnyvale CA (US) for western digital technologies, inc., Jiahui Fu of Fremont CA (US) for western digital technologies, inc.
IPC Code(s): G11C16/26, G11C7/04, G11C16/04, G11C16/08
CPC Code(s): G11C16/26
Abstract: a memory apparatus and method of operation are provided. the apparatus includes memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states. the memory cells are disposed in memory holes grouped in blocks. a control means is configured to determine an amount of the memory cells of one of the blocks that are programmed during at least one read operation. the control means adjusts at least one read parameter based on the amount of the memory cells of the one of the blocks that are programmed. the control means is also configured to utilize the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above one or more read levels associated with each of the plurality of data states in the at least one read operation.
Inventor(s): Jonathan Huynh of San Jose CA (US) for western digital technologies, inc., Khanh Nguyen of San Ramon CA (US) for western digital technologies, inc., Xiang Yang of Santa Clara CA (US) for western digital technologies, inc.
IPC Code(s): G11C16/30, G11C16/10, G11C16/34
CPC Code(s): G11C16/30
Abstract: the memory device includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines and in a plurality of channels. the memory device also includes circuitry that is configured to conduct a hole pre-charge operation to inject holes into the plurality of channels. during the hole pre-charge operation, the circuitry applies a positive celsrc pre-charge voltage to a source line of the memory block and applies a negative unselected word line pre-charge voltage to a plurality of unselected word lines in the memory block to make a plurality of memory cells in the memory block conductive to holes.
Inventor(s): Niles Yang of Mountain View CA (US) for western digital technologies, inc., Judah Gamliel Hahn of Ofra (IL) for western digital technologies, inc.
IPC Code(s): G11C29/44, G06F16/23
CPC Code(s): G11C29/44
Abstract: in one embodiment, a data storage device is provided comprising a memory and a controller. the controller is configured to: receive, from a host, a command to read data from the memory, wherein the command comprises a data integrity level threshold; read the data from the memory; determine a data integrity level of the data; in response to the data integrity level of the data being above the threshold, send the data to the host; and in response to the data integrity level of the data not being above the threshold: perform at least one iteration of an error correction operation on the data until the data integrity level of the data is above the threshold; and send the data to the host. other embodiments are provided, and each of the embodiments can be used alone or in combination.
Inventor(s): Uthayarajan A/L Rasalingam of Nibong Tebal (MY) for western digital technologies, inc., Niladri Dey of West Bengal (IN) for western digital technologies, inc.
IPC Code(s): H05K7/20, F04D25/06, F04D27/00, H05K1/02, H10N10/17
CPC Code(s): H05K7/20209
Abstract: a data storage device includes te elements thermally connected between ic chips thereof and a lid assembly. an electronic controller of the data storage device is configured to receive voltages generated by the te elements in response to the heat generated in the ic chips and is further configured to use the voltages to provide electrical power to an electrical fan of the lid assembly. the fan generates an airflow for keeping the lid assembly at approximately ambient temperature, thereby facilitating heat removal from the ic chips by way of the te elements.
Inventor(s): Shinsuke YADA of Yokkaichi (JP) for western digital technologies, inc.,
IPC Code(s): H10B43/27, H01L23/00, H01L25/00, H01L25/065, H01L25/18, H10B43/35, H10B80/00
CPC Code(s): H10B43/27
Abstract: a three-dimensional memory device includes primary source side select gate electrodes located between word lines and bottom source side select gate electrodes. the primary source side select gate electrodes are laterally separated in each memory block, while the word lines and the bottom source side select gate electrodes are not laterally separated in each memory block.
Inventor(s): Quang LE of San Jose CA (US) for western digital technologies, inc., Xiaoyong LIU of San Jose CA (US) for western digital technologies, inc., Brian R. YORK of San Jose CA (US) for western digital technologies, inc., Cherngye HWANG of San Jose CA (US) for western digital technologies, inc., Hisashi TAKANO of Fujisawa-shi (JP) for western digital technologies, inc., Nam Hai PHAM of Tokyo (JP) for western digital technologies, inc.
IPC Code(s): H10N50/85, H03K19/18, H10N52/80
CPC Code(s): H10N50/85
Abstract: the present disclosure generally relate to an integrated circuit utilizing spin orbital-spin orbital (so-so) logic. the integrated circuit comprises a plurality of so-so logic cells, where each so-so logic cell comprises a first spin orbit torque (sot) layer, a second spin orbit torque (sot) layer, and a ferromagnetic layer disposed between the sot and sot layer. each so-so logic cell is configured for: a first current path that is in plane to a plane of the sot layer, and a second current path that is perpendicular to a plane of the sot layer, the second current path being configured to extend into the ferromagnetic layer. the integrated circuit further comprises a common voltage source connected to each sot device, and one or more interconnects disposed between adjacent sot devices of the plurality of sot devices, the one or more interconnects connecting the adjacent sot devices together.
Western Digital Technologies, Inc. patent applications on December 19th, 2024
- Western Digital Technologies, Inc.
- G06F3/06
- CPC G06F3/0608
- Western digital technologies, inc.
- CPC G06F3/0613
- G06F11/07
- CPC G06F3/0619
- CPC G06F3/0664
- G06F11/10
- CPC G06F11/10
- G06F11/14
- CPC G06F11/1451
- G11B5/31
- CPC G11B5/315
- G11B5/39
- G01R33/09
- G11C11/16
- H03K19/18
- H10B61/00
- H10N50/10
- H10N50/85
- H10N52/80
- CPC G11B5/3909
- G11B5/596
- G11B20/10
- G11B20/12
- CPC G11B5/59655
- G11B23/087
- G11B5/584
- CPC G11B23/087
- G11C16/10
- G11C16/04
- G11C16/08
- CPC G11C16/10
- G11C16/24
- G11C16/26
- CPC G11C16/102
- G11C16/12
- CPC G11C16/12
- G11C7/04
- CPC G11C16/26
- G11C16/30
- G11C16/34
- CPC G11C16/30
- G11C29/44
- G06F16/23
- CPC G11C29/44
- H05K7/20
- F04D25/06
- F04D27/00
- H05K1/02
- H10N10/17
- CPC H05K7/20209
- H10B43/27
- H01L23/00
- H01L25/00
- H01L25/065
- H01L25/18
- H10B43/35
- H10B80/00
- CPC H10B43/27
- Western digital technologies, inc.,
- CPC H10N50/85