United Microelectronics Corp. patent applications on January 9th, 2025
Patent Applications by United Microelectronics Corp. on January 9th, 2025
United Microelectronics Corp.: 21 patent applications
United Microelectronics Corp. has applied for patents in the areas of H01L29/66 (5), H01L29/78 (4), H01L29/423 (4), H01L21/762 (3), H10B63/00 (2) G03F7/70633 (1), H01L29/7786 (1), H10N50/80 (1), H10B63/80 (1), H10B61/00 (1)
With keywords such as: layer, region, structure, gate, dielectric, substrate, disposed, electrode, device, and conductive in patent application abstracts.
Patent Applications by United Microelectronics Corp.
Inventor(s): Chun-Yi Chang of Taichung City (TW) for united microelectronics corp., Chien-Hao Chen of Tainan City (TW) for united microelectronics corp.
IPC Code(s): G03F7/00
CPC Code(s): G03F7/70633
Abstract: provided are a manufacturing method of an overlay mark and an overlay measurement method. the manufacturing method includes the following steps. a first stitching overlay mark structure having a plurality of first patterns is formed on a first layer. a second layer is formed on the first layer. a second stitching overlay mark structure having a plurality of second patterns is formed on the second layer. the second stitching overlay mark structure is located above the first stitching overlay mark structure, and from the top view on the second layer, the second patterns and the first patterns are alternately arranged.
20250014637. MEMORY CIRCUIT_simplified_abstract_(united microelectronics corp.)
Inventor(s): Yang-Ling Wu of Taichung City (TW) for united microelectronics corp.
IPC Code(s): G11C11/412, G11C11/419
CPC Code(s): G11C11/412
Abstract: a memory circuit is provided in the present invention, including multiple storage cells arranged in an array with multiple columns and rows, multiple word lines extending in row direction and connecting with the gates of storage cells, multiple bit lines extending in column direction and connecting respectively with the storage cells, wherein the storage cells in each row correspond to m word lines, m is an integer equal or greater than 2, and the m word lines are sequentially and alternately connected with the storage cells in the row. alternatively, the storage cells of each column correspond to n bit line, n is an integer equal or greater than 2, and the n bit lines are sequentially and alternately connected with the storage cells in the column.
Inventor(s): Kuo-Hsing Lee of Hsinchu County (TW) for united microelectronics corp., Sheng-Yuan Hsueh of Tainan City (TW) for united microelectronics corp., Chi-Horn Pai of Tainan City (TW) for united microelectronics corp., Chih-Kai Kang of Tainan City (TW) for united microelectronics corp.
IPC Code(s): G11C17/16, H10B20/25
CPC Code(s): G11C17/16
Abstract: a bit cell structure for one-time-programming is provided in the present invention, including a first doped region in a substrate and electrically connected to a source line, a second doped region in the substrate and provided with a source and a drain, wherein the drain is electrically connected with a bit line, a doped channel region in the substrate with a first part and a second part connecting respectively to the first doped region and the source of second doped region in a first direction, and a width of the first part in a second direction perpendicular to the first direction is less than a width of the second part and less than a width of the first doped region, and a word line traversing over the second doped region and between the source and drain.
Inventor(s): Chih-Yuan Wen of Tainan City (TW) for united microelectronics corp., Lung-En Kuo of Tainan City (TW) for united microelectronics corp., Chung-Yi Chiu of Tainan City (TW) for united microelectronics corp.
IPC Code(s): H01L21/762
CPC Code(s): H01L21/76229
Abstract: an isolation structure of a semiconductor device includes a substrate, a first isolation structure and a second isolation structure. the substrate has a first region and a second region, and there is a boundary between the first region and the second region. the first isolation structure is disposed in the first region of the substrate, and the first isolation structure includes a dielectric liner and a first insulating layer. the second isolation structure is disposed in the second region of the substrate, and the second isolation structure includes a second insulating layer. the first isolation structure and the second isolation structure are respectively located on both sides of the boundary.
Inventor(s): Fu-Jung Chuang of Kaohsiung City (TW) for united microelectronics corp., Po-Jen Chuang of Kaohsiung City (TW) for united microelectronics corp., Yu-Ren Wang of Tainan City (TW) for united microelectronics corp., Chi-Mao Hsu of Tainan City (TW) for united microelectronics corp., Chia-Ming Kuo of Kaohsiung City (TW) for united microelectronics corp., Guan-Wei Huang of Tainan City (TW) for united microelectronics corp., Chun-Hsien Lin of Tainan City (TW) for united microelectronics corp.
IPC Code(s): H01L21/8238, H01L21/762, H01L27/092
CPC Code(s): H01L21/823878
Abstract: a semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (sdb) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the sdb structure. preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the sdb structure.
20250014991. SEMICONDUCTOR DEVICE_simplified_abstract_(united microelectronics corp.)
Inventor(s): Chia-Chen Sun of Kaohsiung City (TW) for united microelectronics corp.
IPC Code(s): H01L23/522, H01L23/528, H01L27/06
CPC Code(s): H01L23/5228
Abstract: provided is a semiconductor device including a conductive layer, a stop layer, a second dielectric layer disposed on a first dielectric layer and a resistor. the resistor includes a part of the conductive layer, a first strip-like contact, a second strip-like contact, a first auxiliary contact, a second auxiliary contact, a third auxiliary contact and a fourth auxiliary contact. the first strip-like contact and the second strip-like contact respectively extend through the second dielectric layer and the stop layer, and are electrically connected to the conductive layer. the first auxiliary contact and the second auxiliary contact sandwich the first strip-like contact therebetween, extend through the second dielectric layer, and are electrically connected to the conductive layer. the third auxiliary contact and the fourth auxiliary contact sandwich the second strip-like contact therebetween, extend through the second dielectric layer and are electrically connected to the conductive layer.
Inventor(s): Chiu-Jung Chiu of Tainan City (TW) for united microelectronics corp., Chung-Hsing Kuo of Taipei City (TW) for united microelectronics corp., Chun-Ting Yeh of Taipei City (TW) for united microelectronics corp., Chuan-Lan Lin of Chiayi City (TW) for united microelectronics corp., Yu-Ping Wang of Hsinchu City (TW) for united microelectronics corp., Yu-Chun Chen of Kaohsiung City (TW) for united microelectronics corp.
IPC Code(s): H01L23/00, H01L23/522, H01L23/528, H01L23/532
CPC Code(s): H01L24/05
Abstract: the invention provides a semiconductor structure, which comprises a plurality of metal circuit layers stacked with each other, the multi-layer metal circuit layer comprises an aluminum circuit layer which is located at the position closest to a surface among the plurality of circuit layers, the material of the aluminum circuit layer is made of aluminum, and the aluminum circuit layer comprises a concave portion.
20250015142. SEMICONDUCTOR DEVICE_simplified_abstract_(united microelectronics corp.)
Inventor(s): Chih-Tung Yeh of Taoyuan City (TW) for united microelectronics corp., Wen-Jung Liao of Hsinchu City (TW) for united microelectronics corp.
IPC Code(s): H01L29/20, H01L29/66, H01L29/778
CPC Code(s): H01L29/2003
Abstract: a semiconductor device includes a iii-v compound semiconductor layer, a iii-v compound barrier layer, a gate trench, a p-type doped iii-v compound layer, an insulation layer, and a gate electrode. the iii-v compound barrier layer is disposed on the iii-v compound semiconductor layer. the gate trench is disposed in the iii-v compound barrier layer. the p-type doped iii-v compound layer is disposed in the gate trench, and a top surface of the p-type doped iii-v compound layer and a top surface of the iii-v compound barrier layer are substantially coplanar. the insulation layer is disposed on the iii-v compound barrier layer. the insulation layer includes an opening located corresponding to the gate trench in a vertical direction. a part of the p-type doped iii-v compound layer is disposed on the insulation layer in the vertical direction. the gate electrode is disposed on the p-type doped iii-v compound layer.
Inventor(s): Yi-Fan Li of Tainan City (TW) for united microelectronics corp., Wen-Yen Huang of Changhua County (TW) for united microelectronics corp., Shih-Min Chou of Tainan City (TW) for united microelectronics corp., Zhen Wu of Kaohsiung City (TW) for united microelectronics corp., Nien-Ting Ho of Tainan City (TW) for united microelectronics corp., Chih-Chiang Wu of Tainan City (TW) for united microelectronics corp., Ti-Bin Chen of Tainan City (TW) for united microelectronics corp.
IPC Code(s): H01L29/49, H01L27/092, H01L29/40
CPC Code(s): H01L29/4966
Abstract: a method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (bbm) layer on the first region and the second region, forming a first work function metal (wfm) layer on the first bbm layer on the first region and the second region, and then forming a diffusion barrier layer on the first wfm layer.
Inventor(s): Wei-Hsuan Chang of Tainan City (TW) for united microelectronics corp., Ming-Hua Tsai of Tainan City (TW) for united microelectronics corp., Chin-Chia Kuo of Tainan City (TW) for united microelectronics corp.
IPC Code(s): H01L29/66, H01L21/285, H01L29/423, H01L29/45, H01L29/78
CPC Code(s): H01L29/665
Abstract: a semiconductor device includes a substrate; a channel region disposed in the substrate; and a diffusion region disposed in the substrate on a side of the channel region. the diffusion region comprises a ldd region and a heavily doped region within the ldd region. a gate electrode is disposed over the channel region. the gate electrode partially overlaps with the ldd region. a spacer is disposed on a sidewall of the gate electrode. a gate oxide layer is disposed between the gate electrode and the channel region, between the gate electrode and the ldd region, and between the spacer and the ldd region. a silicide layer is disposed on the heavily doped region and is spaced apart from the edge of the spacer.
Inventor(s): Chun-Hao Lin of Kaohsiung City (TW) for united microelectronics corp., Hsin-Yu Chen of Nantou County (TW) for united microelectronics corp., Shou-Wei Hsieh of Hsinchu City (TW) for united microelectronics corp.
IPC Code(s): H01L29/66, H01L21/762
CPC Code(s): H01L29/66628
Abstract: a semiconductor device includes a gate structure on a substrate, a single diffusion break (sdb) structure adjacent to the gate structure, a first spacer adjacent to the gate structure, a second spacer adjacent to the sdb structure, a source/drain region between the first spacer and the second spacer, an interlayer dielectric (ild) layer around the gate structure and the sdb structure, and a contact plug in the ild layer and on the source/drain region. preferably, a top surface of the second spacer is lower than a top surface of the first spacer.
Inventor(s): Shin-Chuan Huang of Tainan City (TW) for united microelectronics corp., Chih-Tung Yeh of Taoyuan City (TW) for united microelectronics corp., Chun-Ming Chang of Kaohsiung City (TW) for united microelectronics corp., Bo-Rong Chen of Hsinchu County (TW) for united microelectronics corp., Wen-Jung Liao of Hsinchu City (TW) for united microelectronics corp., Chun-Liang Hou of Hsinchu County (TW) for united microelectronics corp.
IPC Code(s): H01L29/778, H01L21/265, H01L21/28, H01L29/20, H01L29/205, H01L29/207, H01L29/417, H01L29/423, H01L29/66
CPC Code(s): H01L29/7786
Abstract: a method for fabricating high electron mobility transistor (hemt) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.
Inventor(s): Zong-Han LIN of Tainan City (TW) for united microelectronics corp.
IPC Code(s): H01L29/78, H01L21/8234, H01L27/088, H01L29/10, H01L29/423, H01L29/66
CPC Code(s): H01L29/7816
Abstract: a semiconductor structure and a method for fabricating the same are provided. the semiconductor structure includes a substrate, a source region, a drain region and a gate structure. the source region is located in the substrate. the drain region is located in the substrate. the gate structure is disposed on the substrate and located between the source region and the drain region, and includes a first sub-gate structure and a second sub-gate structure. the first sub-gate structure is adjacent to the source region and includes a first sub-gate insulating layer. the second sub-gate structure is adjacent to the drain region and includes a second sub-gate insulating layer. the second sub-gate insulating layer and the first sub-gate insulating layer are separated from each other. the first sub-gate insulating layer has a first thickness, and the second sub-gate insulating layer has a second thickness greater than the first thickness.
Inventor(s): Shin-Hung Li of Nantou County (TW) for united microelectronics corp.
IPC Code(s): H01L29/78, H01L29/08, H01L29/423
CPC Code(s): H01L29/7827
Abstract: a method of fabricating semiconductor device, the semiconductor device includes a substrate, a first transistor and a second transistor. the substrate includes a high-voltage region and a low-voltage region. the first transistor is disposed on the hv region, and includes a first gate dielectric layer disposed on a first base, and a first gate electrode on the first gate dielectric layer. the first gate dielectric layer includes a composite structure having a first dielectric layer and a second dielectric layer stacked sequentially. the second transistor is disposed on the lv region, and includes a fin shaped structure protruded from a second base on the substrate, and a second gate electrode disposed on the fin shaped structure. the first dielectric layer covers sidewalls of the second gate electrode and a top surface of the first dielectric layer is even with a top surface of the second gate electrode.
20250015186. Semiconductor structure_simplified_abstract_(united microelectronics corp.)
Inventor(s): Hung-Chun Lee of Pingtung County (TW) for united microelectronics corp., Chih-Yi Wang of Tainan City (TW) for united microelectronics corp., Wei-Che Chen of Kaohsiung City (TW) for united microelectronics corp., Ya-Ting Hu of Kaohsiung City (TW) for united microelectronics corp., Yao-Jhan Wang of Tainan City (TW) for united microelectronics corp., Kun-Szu Tseng of Tainan City (TW) for united microelectronics corp., Feng-Yun Cheng of Kaohsiung City (TW) for united microelectronics corp., Shyan-Liang Chou of Tainan City (TW) for united microelectronics corp.
IPC Code(s): H01L29/78, H01L25/16
CPC Code(s): H01L29/7851
Abstract: the invention provides a semiconductor structure, which comprises a middle/high voltage device region and a low voltage device region, a plurality of fin structures disposed in the low voltage device region, and a protruding part located at a boundary between the middle/high voltage device region and the low voltage device region. a top surface of the protruding part is flat, and the top surface of the protruding part is aligned with a flat top surface of the middle/high voltage device region.
Inventor(s): Kuan-Liang LIU of Hsinchu County (TW) for united microelectronics corp., Chiun-Min CHIOU of Hsinchu County (TW) for united microelectronics corp.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/12
Abstract: a semiconductor device and methods for manufacturing the same are provided. the semiconductor device includes a substrate, a nfet structure on the substrate, and a pfet structure on the substrate. the nfet structure includes a first source region, a first drain region and a first gate structure between the first source region and the first drain region. the first gate structure includes a first high-k dielectric layer and a first gate layer on the first high-k dielectric layer. the pfet structure includes a second source region, a second drain region and a second gate structure between the second source region and the second drain region. the second gate structure includes a second high-k dielectric layer and a second gate layer on the second high-k dielectric layer. a thickness of the first high-k dielectric layer is larger than a thickness of the second high-k dielectric layer.
Inventor(s): Chang-Yih Chen of Tainan City (TW) for united microelectronics corp., Yi-Wen Chen of Chiayi County (TW) for united microelectronics corp., Wei-Chung Sun of Tainan City (TW) for united microelectronics corp.
IPC Code(s): H10B20/00, G06F21/75
CPC Code(s): H10B20/60
Abstract: a method for physically unclonable function through gate height tuning is provided in the present invention, including steps of forming a high-k dielectric layer and a dummy silicon layer on a semiconductor substrate, removing the dummy silicon layer, forming a work function layer and a metal filling layer on the high-k dielectric layer, and performing a cmp process to remove the metal filling layer, so as to form metal gates with heights lower than a critical gate height, and using the metal gates to manufacture pio pairs in an internal bias generator. since the height of metal gates is lower than the critical gate height, a local threshold voltage mismatching of the programmed i/o (pio) pairs becomes larger, so as to achieve random code generation in physically unclonable function (puf).
Inventor(s): Da-Jun Lin of Kaohsiung City (TW) for united microelectronics corp., Yi-AN Shih of Changhua County (TW) for united microelectronics corp., Bin-Siang Tsai of Changhua County (TW) for united microelectronics corp., Fu-Yu Tsai of Tainan City (TW) for united microelectronics corp.
IPC Code(s): H10B61/00, H10N50/01, H10N50/80
CPC Code(s): H10B61/00
Abstract: a method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (mtj) on a substrate, forming a top electrode on the mtj, forming an inter-metal dielectric (imd) layer around the top electrode and the mtj, forming a landing layer on the imd layer and the mtj, and then patterning the landing layer to form a landing pad. preferably, the landing pad is disposed on the top electrode and the imd layer adjacent to one side of the top electrode.
20250017024. SEMICONDUCTOR STRUCTURE_simplified_abstract_(united microelectronics corp.)
Inventor(s): Yi-An HUANG of New Taipei City (TW) for united microelectronics corp., Shu-Hung YU of Kaohsiung City (TW) for united microelectronics corp., Chuan-Fu WANG of Miaoli County (TW) for united microelectronics corp.
IPC Code(s): H10B63/00
CPC Code(s): H10B63/80
Abstract: a semiconductor structure is provided. the semiconductor structure includes a plurality of interconnection layers disposed along a first direction, a memory element in the plurality of interconnection layers, a first conductive structure in the plurality of interconnection layers and electrically connected to the memory element, and a second conductive structure in the plurality of interconnection layers and electrically connected to the memory element. the first conductive structure includes a first conductive line and a second conductive line disposed along the first direction. the second conductive structure includes a third conductive line and a fourth conductive line disposed along the first direction. the second conductive line and the memory element are in the same interconnection layer. the third conductive line and the fourth conductive line are above the first conductive line and the second conductive line.
20250017117. MAGNETIC MEMORY DEVICE_simplified_abstract_(united microelectronics corp.)
Inventor(s): Kuan-Hsiang Chen of Nantou County (TW) for united microelectronics corp., Yi-Ching Wang of Taichung City (TW) for united microelectronics corp., Wei Chen of Tainan City (TW) for united microelectronics corp., Chia-Fu Cheng of Taipei City (TW) for united microelectronics corp., Chun-Yao Yang of Kaohsiung City (TW) for united microelectronics corp.
IPC Code(s): H10N50/80, H10B61/00, H10N50/01, H10N50/20, H10N50/85
CPC Code(s): H10N50/80
Abstract: a magnetic memory device includes a magnetic tunneling junction (mtj) stack and a capping layer on the mtj stack. the mtj stack includes a reference layer, a tunneling barrier layer on the reference layer, and a free layer on the tunneling barrier layer. the capping layer includes a metal under layer that is in direct contact with the free layer, an oxide capping layer on the metal under layer, and a metal protection layer on the oxide capping layer.
Inventor(s): Wen-Jen Wang of Tainan City (TW) for united microelectronics corp., Yu-Huan Yeh of Hsinchu City (TW) for united microelectronics corp., Chuan-Fu Wang of Miaoli County (TW) for united microelectronics corp.
IPC Code(s): H10N70/00, H10B63/00
CPC Code(s): H10N70/068
Abstract: a resistive memory structure including a substrate, a dielectric layer, a conductive plug, a resistive memory device, a spacer, and a protective layer is provided. the dielectric layer is located on the substrate. the conductive plug is located in the dielectric layer. the conductive plug has a protrusion portion located outside the dielectric layer. the resistive memory device is located on the conductive plug. the resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. the first electrode is located on the conductive plug. the variable resistance layer is located on the first electrode. the second electrode is located on the variable resistance layer. the spacer is located on a sidewall of the resistive memory device. the protective layer is located on a sidewall of the protrusion portion and between the first electrode and the dielectric layer.
United Microelectronics Corp. patent applications on January 9th, 2025
- United Microelectronics Corp.
- G03F7/00
- CPC G03F7/70633
- United microelectronics corp.
- G11C11/412
- G11C11/419
- CPC G11C11/412
- G11C17/16
- H10B20/25
- CPC G11C17/16
- H01L21/762
- CPC H01L21/76229
- H01L21/8238
- H01L27/092
- CPC H01L21/823878
- H01L23/522
- H01L23/528
- H01L27/06
- CPC H01L23/5228
- H01L23/00
- H01L23/532
- CPC H01L24/05
- H01L29/20
- H01L29/66
- H01L29/778
- CPC H01L29/2003
- H01L29/49
- H01L29/40
- CPC H01L29/4966
- H01L21/285
- H01L29/423
- H01L29/45
- H01L29/78
- CPC H01L29/665
- CPC H01L29/66628
- H01L21/265
- H01L21/28
- H01L29/205
- H01L29/207
- H01L29/417
- CPC H01L29/7786
- H01L21/8234
- H01L27/088
- H01L29/10
- CPC H01L29/7816
- H01L29/08
- CPC H01L29/7827
- H01L25/16
- CPC H01L29/7851
- H10B10/00
- CPC H10B10/12
- H10B20/00
- G06F21/75
- CPC H10B20/60
- H10B61/00
- H10N50/01
- H10N50/80
- CPC H10B61/00
- H10B63/00
- CPC H10B63/80
- H10N50/20
- H10N50/85
- CPC H10N50/80
- H10N70/00
- CPC H10N70/068