US Patent Application 18446392. STRUCTURES AND METHODS FOR PROCESSING A SEMICONDUCTOR SUBSTRATE simplified abstract

STRUCTURES AND METHODS FOR PROCESSING A SEMICONDUCTOR SUBSTRATE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Ming-Yi Shen of Hsinchu (TW)

Hsin-Lin Wu of Hsinchu (TW)

Yao-Fong Dai of Hsinchu (TW)

Pei-Yuan Tai of Hsinchu (TW)

Chin-Wei Chen of Hsinchu (TW)

Yin-Tun Chou of Hsinchu (TW)

Yuan-Hsin Chi of Hsinchu (TW)

Sheng-Yuan Lin of Hsinchu (TW)

STRUCTURES AND METHODS FOR PROCESSING A SEMICONDUCTOR SUBSTRATE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18446392 titled 'STRUCTURES AND METHODS FOR PROCESSING A SEMICONDUCTOR SUBSTRATE

Simplified Explanation

The present disclosure is about exclusion rings used in processing semiconductor substrates in a processing chamber, specifically a chemical vapor deposition chamber.

• The exclusion ring has an alignment structure that works with an alignment structure on a platen where the exclusion ring will be placed during wafer processing.
• The first alignment structure has a guiding surface that helps position the second alignment structure within it.
• The exclusion rings described in the patent application improve the processing of semiconductor substrates in a chemical vapor deposition chamber.
• The alignment structures on the exclusion ring and platen ensure accurate positioning of the exclusion ring during wafer processing.
• The guiding surface on the first alignment structure aids in the reception and positioning of the second alignment structure.
• The patent application also includes methods for using these exclusion rings in semiconductor substrate processing.

Original Abstract Submitted

The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.