US Patent Application 17946518. MEMORY DEVICE SECURITY AND ROW HAMMER MITIGATION simplified abstract

MEMORY DEVICE SECURITY AND ROW HAMMER MITIGATION

Organization Name

Micron Technology, Inc.

Inventor(s)

Yang Lu of Boise ID (US)

Sujeet Ayyapureddi of Boise ID (US)

Edmund J. Gieske of Boise ID (US)

Cagdas Dirik of Indianola WA (US)

Ameen D. Akel of Rancho Cordova CA (US)

Elliott C. Cooper-balis of San Jose CA (US)

Amitava Majumdar of Boise ID (US)

Robert M. Walker of Raleigh NC (US)

Danilo Caraccio of Milano (IT)

MEMORY DEVICE SECURITY AND ROW HAMMER MITIGATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17946518 titled 'MEMORY DEVICE SECURITY AND ROW HAMMER MITIGATION

Simplified Explanation

- This patent application describes systems, methods, and apparatus for enhancing the security and mitigating the effects of row hammer in memory devices. - The invention involves implementing a control mechanism in the front-end and/or back-end of a memory sub-system to refresh rows of memory. - When a row activation command is received, the control circuitry increments a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system. - The control circuitry then determines if the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC), which is incremented each time the CAM is full. - If the first count is found to be greater than the RHT minus the second count, a refresh command is issued to the row address. - The purpose of this invention is to prevent row hammer attacks, which exploit the vulnerability of memory cells to repeated access, potentially leading to unauthorized access or corruption of data. - By implementing this control mechanism, the invention aims to enhance the security and reliability of memory devices by proactively refreshing rows of memory and preventing row hammer attacks. - This innovation can be applied to various memory devices, such as RAM (Random Access Memory), to protect against potential security threats and ensure data integrity.

Original Abstract Submitted

Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.