Tokyo Electron Limited patent applications on March 6th, 2025
Patent Applications by Tokyo Electron Limited on March 6th, 2025
Tokyo Electron Limited: 26 patent applications
Tokyo Electron Limited has applied for patents in the areas of H01L21/311 (5), H01J37/32 (4), H01L29/66 (3), H01L21/02 (3), H01L21/677 (3) H01L21/67712 (2), B25J11/0095 (1), H01J37/32935 (1), H10D62/121 (1), H01L21/67718 (1)
With keywords such as: substrate, surface, processing, layer, plasma, configured, film, chamber, gas, and inspection in patent application abstracts.
Patent Applications by Tokyo Electron Limited
20250073916. MAINTENANCE DEVICE_simplified_abstract_(tokyo electron limited)
Inventor(s): Norihiko AMIKURA of Miyagi (JP) for tokyo electron limited
IPC Code(s): B25J11/00, B25J9/00
CPC Code(s): B25J11/0095
Abstract: provided is a maintenance device for assisting an exchange of a transfer robot mounted on a transfer module, the maintenance device comprising: a carriage; a housing having an upper opening and a lower opening, wherein the housing is disposed above the carriage; a first lifting unit mounted on the carriage and configured to raise and lower the housing between a first upper position and a first lower position, wherein the housing is connected to the transfer module when the housing is at the first upper position; a lower shutter configured to open and close the lower opening; a support unit configured to support the transfer robot; and a second lifting unit configured to raise and lower the support unit between a second upper position within the housing and a second lower position below the housing when the housing is at the first upper position.
20250075316. METHOD FOR FORMING INSULATION FILM_simplified_abstract_(tokyo electron limited)
Inventor(s): Nobuo MATSUKI of Nirasaki City (JP) for tokyo electron limited
IPC Code(s): C23C16/32, C23C16/458
CPC Code(s): C23C16/325
Abstract: a method of forming an insulation film on a substrate, includes: reacting, as a film-forming gas, an oxygen-containing silicon compound gas represented by formula below with a non-oxidizing hydrogen-containing gas in a state in which at least the non-oxidizing hydrogen-containing gas is plasmarized, to form a film of a flowable silanol compound on the substrate; and subsequently, annealing the substrate to turn the flowable silanol compound into the insulation film. sio(o—ch)�ch(where m, n, and � are arbitrary integers of 1 or more, �, �, x, and y are arbitrary integers of 0 or more, and � and � are not 0 at a same time).
Inventor(s): Yuichi FURUYA of Yamanashi (JP) for tokyo electron limited, Ryuta MOCHIZUKI of Yamanashi (JP) for tokyo electron limited
IPC Code(s): C23C16/448, C23C16/06, C23C16/44, C23C16/455
CPC Code(s): C23C16/448
Abstract: a substrate processing apparatus, includes: a chamber configured to be capable of being depressurized and accommodate a substrate; and an enclosure configured to enclose a supply source of a process gas supplied to the chamber and a connection pipe connecting the supply source and the chamber.
Inventor(s): Takuya HIGUCHI of Iwate (JP) for tokyo electron limited, Kosuke TAKAHASHI of Iwate (JP) for tokyo electron limited, Yasuhiro ONODERA of Iwate (JP) for tokyo electron limited
IPC Code(s): C23C16/54, C23C16/06
CPC Code(s): C23C16/45561
Abstract: a method of monitoring a liquid raw material in a gas supply device, including a raw material storage tank that stores the liquid raw material, a liquid level detector that detects a liquid level of the liquid raw material, a gas inlet provided in the raw material storage tank, a gas outlet provided in the raw material storage tank, and a raw material inlet provided in the raw material storage tank, includes calculating a remaining amount of the liquid raw material based on a usage amount of the raw material and a replenishment amount of the raw material, estimating a detection result of a virtual sensor from the calculated remaining amount of the liquid raw material, and monitoring the liquid raw material based on a detection result of the liquid level detector and the estimated detection result of the virtual sensor.
Inventor(s): Masahide TADOKORO of Kumamoto (JP) for tokyo electron limited, Toyohisa TSURUDA of Kumamoto (JP) for tokyo electron limited
IPC Code(s): G01B11/06
CPC Code(s): G01B11/0625
Abstract: a film thickness analysis method includes: acquiring film thickness values at a plurality of measurement points different from each other along a radial direction for a target film formed on an analysis target substrate by supplying a processing liquid while rotating the target substrate based on predetermined liquid processing conditions; and creating an approximate expression related to a film thickness distribution of the target film by approximating the film thickness values at the plurality of measurement points with respect to one zernike polynomial. the approximate expression is created by specifying a coefficient related to the film thickness of the entire target substrate and one or more coefficients related to concentric curvature components, among a plurality of coefficients included in the zernike polynomial.
20250076215. Testing Apparatus and Testing Method_simplified_abstract_(tokyo electron limited)
Inventor(s): Hiroyuki NAKAYAMA of Yamanashi (JP) for tokyo electron limited
IPC Code(s): G01N21/95, G01M11/02, G01N21/88
CPC Code(s): G01N21/9501
Abstract: an inspection apparatus for inspecting an inspection target device formed on an inspection target object. the inspection apparatus comprises a placing table configured to support the inspection target object. the placing table includes a transparent placing surface and an irradiation part disposed below the placing surface. the irradiation part includes a light guiding plate having a facing surface facing the inspection target object, and a light source part disposed in a region laterally outside from the light guiding plate and configured to emit light toward a lateral edge surface of the light guiding plate. the light guiding plate emits light from the facing surface toward the placing surface. the placing table further includes an optical member that transmits light directed from the facing surface toward the inspection target object. the optical member is divided into a plurality of regions, with light transmittance configured to be variable for each region.
20250076232. Inspection Apparatus and Mounting Base_simplified_abstract_(tokyo electron limited)
Inventor(s): Shigeru KASAI of Yamanashi (JP) for tokyo electron limited, Naoki AKIYAMA of Yamanashi (JP) for tokyo electron limited, Fumiya TAKASE of Yamanashi (JP) for tokyo electron limited, Hiroyuki NAKAYAMA of Yamanashi (JP) for tokyo electron limited, Hajime KUMASAKA of Yamanashi (JP) for tokyo electron limited
IPC Code(s): G01N25/72, G01R31/26, G01R31/265
CPC Code(s): G01N25/72
Abstract: an inspection apparatus for inspecting an inspection target device is presented. the inspection apparatus comprises a placing table that supports the inspection target object while facing the back surface of the imaging device, and the placing table includes: a ceiling plate made of a light transmitting material and having a placing surface on which the inspection target object is placed, an irradiation part that is disposed at a position facing the inspection target object with the ceiling plate interposed therebetween and that irradiates light toward the inspection target object placed on the placing surface; and a temperature controller configured to adjusts a temperature of the inspection target device of the inspection target object placed on the placing surface.
20250076372. INSPECTION METHOD AND INSPECTION APPARATUS_simplified_abstract_(tokyo electron limited)
Inventor(s): Sooraj RAJENDRAN of Yamanashi (JP) for tokyo electron limited
IPC Code(s): G01R31/28, G01R1/073
CPC Code(s): G01R31/2891
Abstract: an adjustment method is provided for an inspection apparatus configured to inspect an inspection object by bringing a tip of a probe disposed on a probe card into contact with an electrode disposed on the inspection object. the method includes projecting, by a projector, an optical dot pattern in which optical dots are arranged, receiving the optical dots by a light receiver, capturing a standard image including the optical dots projected by the projector, capturing a measurement image including at least two of the optical dots of the optical dot pattern received by the light receiver, and adjusting a stage on which the inspection object is disposed, according to the standard image and the measurement image.
Inventor(s): Ankur AGARWAL of Austin TX (US) for tokyo electron limited, Michael CARCASI of Austin TX (US) for tokyo electron limited
IPC Code(s): G03F7/004
CPC Code(s): G03F7/0044
Abstract: a method for fabricating a semiconductor device with organometallic based photoresists and commercial extreme ultraviolet photolithography. the method for fabricating a semiconductor device includes applying organometallic based photoresist to a substrate and exposing the organometallic based photoresist to extreme ultraviolet photolithography. the method may include introducing an additive to the organometallic based photoresist to promote at least one of adhesion, passivation, reactivity and cross-linking of components in the organometallic based photoresist. the method may also include exposing the organometallic based photoresist to microwave radiation. the microwave radiation may couple with molecular motions, such as internal rotations, to enhance organometallic based photoresist cluster mobility or reorientations. in addition, microwave radiation may induce charge polarization and eddy currents in materials, resulting in induced electron transport and heating due to resistive losses.
Inventor(s): Yun Han of Albany NY (US) for tokyo electron limited, Peter Ventzek of Austin TX (US) for tokyo electron limited, Alok Ranjan of Austin TX (US) for tokyo electron limited
IPC Code(s): G03F7/00, H01L21/027, H01L21/311
CPC Code(s): G03F7/70033
Abstract: methods are provided herein for patterning extreme ultraviolet (euv) (or lower wavelength) photoresists, such metal-oxide photoresists. a patterning layer comprising a metal-oxide photoresist is provided on one or more underlying layers provided on a substrate, and portions of the patterning layer not covered by a mask overlying the patterning layer are exposed to euv or lower wavelengths light. a cyclic dry process is subsequently performed to remove portions of the patterning layer defined by the euv or lower wavelength light and develop the metal-oxide photoresist pattern.
Inventor(s): Masakazu YAMAMOTO of Iwate (JP) for tokyo electron limited, Tadashi ENOMOTO of Iwate (JP) for tokyo electron limited
IPC Code(s): G05B19/4065, G05B19/404, G05B19/4069, G05B19/408
CPC Code(s): G05B19/4065
Abstract: an information processing apparatus executes a simulation of a process state, which is being executed in a semiconductor manufacturing apparatus using a physical model of the semiconductor manufacturing apparatus. the information processing apparatus includes a simulation execution unit that executes the simulation by setting operating conditions of the physical model to the same conditions as those of the semiconductor manufacturing apparatus; a physical coefficient change unit that changes a physical coefficient of the physical model such that an output value of the physical model approximates to a corresponding output value of the semiconductor manufacturing apparatus a deterioration state analysis unit that analyzes a deterioration state of the semiconductor manufacturing apparatus, based on a change in the physical coefficient; and a deterioration state output unit that outputs information regarding the deterioration state of the semiconductor manufacturing apparatus, analyzed by the deterioration state analysis unit.
Inventor(s): Ya-Ming Chen of Austin TX (US) for tokyo electron limited, Shyam Sridhar of Austin TX (US) for tokyo electron limited, Peter Lowell George Ventzek of Austin TX (US) for tokyo electron limited, Mitsunori Ohata of Taiwa-cho (JP) for tokyo electron limited
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32449
Abstract: a method for plasma processing a substrate, where the method includes generating a plasma in a plasma chamber within which the substrate is held during processing, where generating the plasma includes: flowing a discharge gas through the plasma chamber; coupling a radio frequency (rf) source signal to a first rf electrode, where the coupling ionizes the discharge gas; and coupling a bias signal to a second rf electrode, the bias signal being a periodic series of bias pulses, each period having a bias-on time and a bias-off time, where a bias voltage waveform is applied during the bias-on time; generating a pulsed dc magnetic field in the plasma chamber, by coupling a magnetizing signal to an electromagnet, the magnetizing signal being a periodic series of current pulses; and prior to coupling the magnetizing signal, synchronizing the periodic series of current pulses with the bias signal to flow a dc magnetizing current during the bias-on time.
Inventor(s): Takashi ARAMAKI of Miyagi (JP) for tokyo electron limited, Lifu LI of Miyagi (JP) for tokyo electron limited, Nobutaka SASAKI of Miyagi (JP) for tokyo electron limited, Toshiki AKAMA of Miyagi (JP) for tokyo electron limited, Shusei KATO of Miyagi (JP) for tokyo electron limited, Gyeong min PARK of Miyagi (JP) for tokyo electron limited, Wataru SHIMIZU of Miyagi (JP) for tokyo electron limited, Ryota KOITABASHI of Miyagi (JP) for tokyo electron limited
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32807
Abstract: a substrate processing system includes a plasma processing apparatus, a decompression transferrer coupled to the plasma processing apparatus, and control circuitry that controls a transfer robot to load an edge ring into a process chamber and to transfer the edge ring to a lift assembly, controls the lift assembly to lower the edge ring onto a ring support surface, controls an electrostatic chuck to electrostatically clamp the edge ring onto the ring support surface, and controls a plasma generator to generate plasma in the process chamber and stabilize the electrostatically clamping of the edge ring onto the electrostatic chuck before performing plasma processing on a product substrate, the stabilizing includes controlling a power source to apply pulsed direct current voltage to the substrate support, including applying a first bias voltage and applying a second bias voltage higher than the first bias voltage after applying the first bias voltage.
Inventor(s): Takeshi KOBAYASHI of Iwate (JP) for tokyo electron limited
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32935
Abstract: an ignition control method includes: providing a substrate processing apparatus including a pair of electrodes in a processing container, a matching box including a variable reactor and an electronic circuit, an rf power supply connected to the electrodes, and a temperature sensor that detects a temperature of the variable reactor; setting the temperature of the variable reactor to a first temperature, and measuring first information indicating a voltage between the electrodes for each adjustment position of the variable reactor when a radio-frequency voltage is applied to the electrodes; determining a preset value of the variable reactor based on the first information; acquiring the detected temperature of the variable reactor as a second temperature; and when the first and second temperatures are different, correcting the current by controlling the electronic circuit such that an adjustment position of the variable reactor becomes the determined preset value.
Inventor(s): Panupong JAIPAN of Albany NY (US) for tokyo electron limited, Matthew BARON of Albany NY (US) for tokyo electron limited, Kandabara TAPILY of Albany NY (US) for tokyo electron limited, Ilseok SON of Albany NY (US) for tokyo electron limited, Arkalgud SITARAM of Albany NY (US) for tokyo electron limited, Yohei YAMASHITA of Kumamoto (JP) for tokyo electron limited, Yasutaka MIZOMOTO of Kumamoto (JP) for tokyo electron limited, Yoshihiro TSUTSUMI of Tokyo (JP) for tokyo electron limited, Yoshihiro KONDO of Kumamoto (JP) for tokyo electron limited
IPC Code(s): H01L21/02, H01L21/306
CPC Code(s): H01L21/02532
Abstract: semiconductor devices and corresponding methods of manufacture are disclosed. the method includes forming a first device structure on a first substrate, a first laser liftoff layer on the first device structure, a protective layer on the first laser liftoff layer, and a second substrate on the protective layer. the method includes de-attaching, through applying radiation on the first laser liftoff layer, the protective layer from the first laser liftoff layer, with a first surface of the second substrate remaining in contact with a second surface of the protective layer. the protective layer is transparent to the radiation.
Inventor(s): Tatsuya MIYAHARA of Yamanashi (JP) for tokyo electron limited, Daisuke SUZUKI of Yamanashi (JP) for tokyo electron limited, Yoshihiro TAKEZAWA of Yamanashi (JP) for tokyo electron limited
IPC Code(s): H01L21/02, C23C16/52, C23C16/56
CPC Code(s): H01L21/02664
Abstract: a substrate-processing method includes: preparing a substrate including an undoped silicon film and a phosphorus-doped silicon film, at least the phosphorus-doped silicon film being exposed on a surface of the substrate; and supplying a halogen gas to the substrate, and, from among the undoped silicon film the phosphorus-doped silicon film, etching and removing the phosphorus-doped silicon film selectively.
Inventor(s): Daisuke YOSHIKOSHI of Miyagi (JP) for tokyo electron limited, Yusuke SHIMIZU of Miyagi (JP) for tokyo electron limited, Shigeru TAHARA of Miyagi (JP) for tokyo electron limited
IPC Code(s): H01L21/033, H01L21/311, H01L21/67
CPC Code(s): H01L21/0337
Abstract: provided is a plasma processing method performed with a plasma processing apparatus including a chamber. this method includes: (a) preparing a substrate on a substrate support in the chamber, the substrate including an etching target film and a metal-containing film provided on the etching target film, the metal-containing film including an exposed first region and an unexposed second region; (b) reforming the metal-containing film using a first plasma formed from a first processing gas, the first processing gas including either a fluorine-containing gas or an oxygen-containing gas; and (c) selectively removing the first region of the reformed metal-containing film with respect to the second region using a second plasma formed from a second processing gas.
Inventor(s): Peter Lowell George Ventzek of Austin TX (US) for tokyo electron limited, Alok Ranjan of Austin TX (US) for tokyo electron limited, Mitsunori Ohata of Taiwa-cho (JP) for tokyo electron limited
IPC Code(s): H01L21/3065, H01J37/32, H01L21/3213
CPC Code(s): H01L21/3065
Abstract: a plasma processing system includes a remote source chamber, a plenum chamber, a plasma process chamber, and a substrate holder disposed within the plasma process chamber. the remote source chamber is configured to contain a remote plasma generated from a first gas within the remote source chamber. the remote plasma includes radicals. the plenum chamber is includes a radical ballast region bounded by a bottom wall and sidewalls. the plenum chamber is configured to receive the radicals from the remote source chamber. the plasma process chamber is configured to receive the radicals through the sidewalls of the plenum chamber as well as to contain a process plasma generated from a second gas within the plasma process chamber. the substrate holder is configured to support a substrate to be processed using the process plasma in the presence of the radicals.
Inventor(s): Tulashi Dahal of Austin TX (US) for tokyo electron limited, Paul Abel of Austin TX (US) for tokyo electron limited, Mengistie Debasu of Austin TX (US) for tokyo electron limited
IPC Code(s): H01L21/311, H01L21/02
CPC Code(s): H01L21/31111
Abstract: systems and methods are provided for etching molybdenum in a wet ale process. the methods disclosed herein use a wide variety of techniques and wet etch chemistries to oxidize a molybdenum surface and form a self-limiting, molybdenum oxide passivation layer in a surface modification step of the wet ale process. for example, the methods use: (a) ultra-violet (uv) photolysis of peroxide oxidizers to create oxidizing radicals, which limit oxidation of the molybdenum surface and provide quasi-self-limiting oxidation behavior, (b) steric hinderance of oxidizers having large reactant molecules to achieve better self-limiting oxidation behavior, and/or (c) ligand-assisted oxidation to change the surface chemistry of the molybdenum oxide passivation layer and ensure self-limiting oxidation behavior. after forming the molybdenum oxide passivation layer using one or more of the oxidation techniques disclosed herein, the passivation layer is selectively removed in a dissolution step of the wet ale process to etch the molybdenum surface.
Inventor(s): Paul Abel of Austin TX (US) for tokyo electron limited
IPC Code(s): H01L21/311
CPC Code(s): H01L21/31116
Abstract: embodiments of processes and methods that provide selective etching of silicon nitride are disclosed herein. more specifically, new processes, methods and etch chemistries are provided to selectively etch silicon nitride layers formed on a substrate, while protecting silicon oxide layers formed on the same substrate. in the method embodiments, a substrate having a silicon nitride (sin) layer and a silicon oxide layer formed on the same substrate is exposed to an alkylating agent, which reacts with the amine groups on the exposed sin surfaces to form an alkylated surface layer on the sin layer. the substrate is exposed to a fluorinating agent to remove the alkylated surface layer and selectively etch the sin layer without significantly etching the silicon oxide layer. the disclosed methods can be used to selectively etch silicon nitride over silicon oxide using a wet or dry process.
Inventor(s): Jason MARION of Albany NY (US) for tokyo electron limited, Alexander KAISER of Albany NY (US) for tokyo electron limited, Yusuke YOSHIDA of Albany NY (US) for tokyo electron limited, Yun HAN of Albany NY (US) for tokyo electron limited
IPC Code(s): H01L21/3213, H01L21/3205, H01L21/321, H01L29/40, H01L29/66
CPC Code(s): H01L21/32139
Abstract: a method includes providing a semiconductor substrate and forming a fin protruding from the semiconductor substrate. the method includes forming a silicon-containing layer over the fin. the method further includes patterning the silicon-containing layer to form a gate structure over the fin, where patterning the silicon-containing layer is implemented using an etchant and a passivant that includes a silicon-containing gas and a nitrogen-containing gas.
Inventor(s): Tsuyoshi WATANABE of Koshi City (JP) for tokyo electron limited, Masashi TSUCHIYAMA of Koshi City (JP) for tokyo electron limited, Suguru ENOKIDA of Koshi City (JP) for tokyo electron limited, Taro YAMAMOTO of Koshi City (JP) for tokyo electron limited
IPC Code(s): H01L21/677, G03F7/16
CPC Code(s): H01L21/67712
Abstract: a substrate processing apparatus includes; a carrier block; a first processing block including first lower and upper processing blocks to deliver a substrate to and from the carrier block; a second processing block including second lower and upper processing blocks provided adjacent to the first lower and upper processing blocks; a relay block including a lifting and transferring mechanism that delivers the substrate between the second lower and upper processing blocks; a controller that controls an operation of each main transfer mechanism such that one of upper and lower processing blocks forms an outward path through which the substrate is transferred from the carrier block to the relay block and the other forms a return path through which the substrate is transferred from the relay block to the carrier block; and a bypass transfer mechanism provided for each of the first and second processing blocks.
Inventor(s): Keisuke KONDOH of Nirasaki City (JP) for tokyo electron limited, Tomonori IWASAKI of Nirasaki City (JP) for tokyo electron limited
IPC Code(s): H01L21/677, B25J19/02, H01L21/67, H01L21/683
CPC Code(s): H01L21/67712
Abstract: a substrate holder for receiving a substrate from a transfer arm and holding the substrate, includes: a stage configured to be raised and lowered in a vertical direction and configured to place the substrate thereon; a measurer configured to measure at least one of a weight, a pressure, and a displacement of the stage; and a controller configured to predict a state of the transfer arm based on measurement results of the measurer.
Inventor(s): Yukiyoshi Saito of Koshi City (JP) for tokyo electron limited, Keita Hirase of Koshi City (JP) for tokyo electron limited, Keisuke Sasaki of Koshi City (JP) for tokyo electron limited
IPC Code(s): H01L21/677
CPC Code(s): H01L21/67718
Abstract: a substrate holder includes a main body having a first arm and a second arm whose leading ends are spaced apart from each other and whose base ends are connected to each other; a first holding guide fixed to the leading end of the first arm, and configured to hold a periphery of the substrate; and a second holding guide fixed to the leading end of the second arm, and configured to hold the periphery of the substrate. a length between the first holding guide and the second holding guide is shorter than a diameter of the substrate. in a state that the substrate is located closer to the base ends than a position where the substrate is held by the first holding guide and the second holding guide, the first arm, the second arm, the first holding guide and the second holding guide are located diametrically outside the substrate.
Inventor(s): H. Jim FULFORD of Marianna FL (US) for tokyo electron limited, Mark I. GARDNER of Cedar Creek TX (US) for tokyo electron limited
IPC Code(s): H01L29/06, H01L21/8238, H01L27/088, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D62/121
Abstract: a semiconductor device is provided. the semiconductor device includes a substrate and channel structures stacked over each other along a first direction substantially perpendicular to a working surface of the substrate and each configured to have a current direction along a second direction substantially parallel to the working surface of the substrate. source/drain (s/d) structures are positioned on opposing sides of the channel structure along the second direction. gate structures are positioned on opposite sides of the channel structures along a third direction substantially parallel to the working surface of the substrate. the channel structures each have a shape of a nanosheet extending substantially perpendicular to the working surface of the substrate.
20250081552. 3D SPACER NANOSHEET FORMATION_simplified_abstract_(tokyo electron limited)
Inventor(s): H. Jim FULFORD of Marianna FL (US) for tokyo electron limited, Mark I. GARDNER of Cedar Creek TX (US) for tokyo electron limited
IPC Code(s): H01L29/06, H01L21/308, H01L21/311, H01L27/088, H01L29/10, H01L29/66, H01L29/778
CPC Code(s): H10D62/122
Abstract: a semiconductor device is provided. the semiconductor device includes a pair of channel structures each configured to have a current direction along a first direction substantially parallel to a working surface of a substrate. the semiconductor device also includes source/drain (s/d) structures on opposing sides of the pair of channel structures along the first direction. the semiconductor device further includes a gate structure between the pair of channel structures. the pair of channel structures includes two-dimensional (2d) semiconductor material oriented substantially perpendicular to the working surface of the substrate.
Tokyo Electron Limited patent applications on March 6th, 2025
- Tokyo Electron Limited
- B25J11/00
- B25J9/00
- CPC B25J11/0095
- Tokyo electron limited
- C23C16/32
- C23C16/458
- CPC C23C16/325
- C23C16/448
- C23C16/06
- C23C16/44
- C23C16/455
- CPC C23C16/448
- C23C16/54
- CPC C23C16/45561
- G01B11/06
- CPC G01B11/0625
- G01N21/95
- G01M11/02
- G01N21/88
- CPC G01N21/9501
- G01N25/72
- G01R31/26
- G01R31/265
- CPC G01N25/72
- G01R31/28
- G01R1/073
- CPC G01R31/2891
- G03F7/004
- CPC G03F7/0044
- G03F7/00
- H01L21/027
- H01L21/311
- CPC G03F7/70033
- G05B19/4065
- G05B19/404
- G05B19/4069
- G05B19/408
- CPC G05B19/4065
- H01J37/32
- CPC H01J37/32449
- CPC H01J37/32807
- CPC H01J37/32935
- H01L21/02
- H01L21/306
- CPC H01L21/02532
- C23C16/52
- C23C16/56
- CPC H01L21/02664
- H01L21/033
- H01L21/67
- CPC H01L21/0337
- H01L21/3065
- H01L21/3213
- CPC H01L21/3065
- CPC H01L21/31111
- CPC H01L21/31116
- H01L21/3205
- H01L21/321
- H01L29/40
- H01L29/66
- CPC H01L21/32139
- H01L21/677
- G03F7/16
- CPC H01L21/67712
- B25J19/02
- H01L21/683
- CPC H01L21/67718
- H01L29/06
- H01L21/8238
- H01L27/088
- H01L29/08
- H01L29/423
- H01L29/775
- H01L29/786
- CPC H10D62/121
- H01L21/308
- H01L29/10
- H01L29/778
- CPC H10D62/122
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