Tokyo Electron Limited patent applications on April 24th, 2025
Patent Applications by Tokyo Electron Limited on April 24th, 2025
Tokyo Electron Limited: 19 patent applications
Tokyo Electron Limited has applied for patents in the areas of H01J37/32 (6), C23C16/455 (5), H01L21/67 (4), H01L21/02 (4), C23C16/52 (4) H01J37/32155 (2), B08B5/023 (1), H01J37/32935 (1), H10B51/20 (1), H01L21/67288 (1)
With keywords such as: substrate, gas, processing, film, discharge, liquid, mechanism, plasma, power, and process in patent application abstracts.
Patent Applications by Tokyo Electron Limited
20250128298. CLEANING METHOD AND FILM-FORMING APPARATUS_simplified_abstract_(tokyo electron limited)
Inventor(s): Hitoshi KATO of Iwate JP for tokyo electron limited
IPC Code(s): B08B5/02, B08B9/00, C23C16/44
CPC Code(s): B08B5/023
Abstract: a cleaning method for cleaning an interior of a process chamber includes (a) carrying a substrate out of the interior of the process chamber, the substrate being subjected to film formation in a state in which the substrate is supported by a substrate support; and (b) after (a), cleaning at least one of the substrate support or a surrounding portion around the substrate support. the cleaning in (b) includes rotating the substrate support and moving one of the substrate support or a nozzle gas discharge mechanism relative to another of the substrate support or the nozzle gas discharge mechanism, in conjunction with discharging a cleaning gas toward at least one of the substrate support or the surrounding portion from the discharge hole of the nozzle gas discharge mechanism, thereby partially cleaning a film-formed region of at least one of the substrate support or the surrounding portion.
Inventor(s): Hitoshi KATO of Iwate JP for tokyo electron limited
IPC Code(s): C23C16/455, C23C16/458, C23C16/52
CPC Code(s): C23C16/45544
Abstract: a film-forming method for forming a film on a substrate includes (a) forming the film on the substrate by, in a process chamber, rotating the substrate, moving one of the substrate or a nozzle gas discharge mechanism relative to another of the substrate or the nozzle gas discharge mechanism such that a discharge hole of the nozzle gas discharge mechanism passes over a center of the substrate, and discharging a processing gas toward the substrate from the discharge hole; and (b) changing a discharge condition of the processing gas from that in (a), and adjusting a film thickness of the film formed on the substrate by, in the process chamber, rotating the substrate, moving one of the substrate or the nozzle gas discharge mechanism relative to another of the substrate or the nozzle gas discharge mechanism, and discharging the processing gas toward the substrate from the discharge hole.
Inventor(s): Ryota IFUKU of Nirasaki-shi JP for tokyo electron limited, Masataka TOIYA of Nirasaki-shi JP for tokyo electron limited, Eiki KAMATA of Nirasaki-shi JP for tokyo electron limited, Hiroki YAMADA of Nirasaki-shi JP for tokyo electron limited, Takashi MATSUMOTO of Nirasaki-shi JP for tokyo electron limited
IPC Code(s): C23C16/455, H01J37/32, H01L21/02
CPC Code(s): C23C16/45557
Abstract: a method of processing a substrate includes placing the substrate on a stage in a process container, supplying a plasma generating gas into the process container to generate plasma of first power at a first pressure, controlling an inside of the process container to a second pressure lower than the first pressure, and supplying a carbon-containing gas into the process container to form a graphene film on the substrate.
20250129475. MULTIPLE INPUT POST MIX SHOWERHEAD_simplified_abstract_(tokyo electron limited)
Inventor(s): Norman JACOBSON of Albany NY US for tokyo electron limited, Ronald NASMAN of Albany NY US for tokyo electron limited, Kandabara TAPILY of Mechanicsville NY US for tokyo electron limited
IPC Code(s): C23C16/455, C23C16/458
CPC Code(s): C23C16/45565
Abstract: aspects of the present disclosure provide an apparatus, which includes first gas channels distributing a first process gas and second gas channels alternating with the first gas channels and distributing a second process gas. the apparatus further includes first feed tubes each including first outlets configured to deliver the first process gas to a row of the first gas channels via the first outlets along different first flow paths of a same first length, and second feed tubes each including second outlets corresponding to a row of the second gas channels and configured to deliver the second process gas to the row of the second gas channels via the second outlets along different second flow paths of a same second length. the apparatus further includes vertical gas conduits each vertically extending from a respective one of the array of gas channels configured to transmit the first or second process gas.
Inventor(s): Hitoshi KATO of Iwate JP for tokyo electron limited
IPC Code(s): C23C16/458, C23C16/455, C23C16/52, H01L21/02
CPC Code(s): C23C16/4584
Abstract: a film-forming method for forming a film on a substrate, the film-forming method includes: (a) forming a film on a substrate by a first film-forming apparatus, and (b) moving the substrate provided with the film formed in the (a) to a second film-forming apparatus different from the first film-forming apparatus and forming a film over the substrate by the second film-forming apparatus. in the (b), the substrate is rotated inside a process chamber, one of the substrate or a nozzle gas discharge mechanism is moved relative to another of the substrate or the nozzle gas discharge mechanism such that a discharge hole of the nozzle gas discharge mechanism passes over a center of the substrate, and a processing gas is discharged from the discharge hole toward the substrate, thereby adjusting a film thickness of the film to be formed over the substrate.
Inventor(s): Hitoshi KATO of Iwate JP for tokyo electron limited
IPC Code(s): C23C16/52, C23C16/455
CPC Code(s): C23C16/52
Abstract: a film-forming method for forming a film on a substrate includes: (a) forming the film on the substrate by, in a process chamber, rotating the substrate, moving one of the substrate or a nozzle gas discharge mechanism relative to another of the substrate or the nozzle gas discharge mechanism, and discharging a film-forming gas toward the substrate from the discharge hole of the nozzle gas discharge mechanism; and (b) after (a), adjusting a film thickness of the film formed on the substrate by, in the process chamber, rotating the substrate, moving one of the substrate or the nozzle gas discharge mechanism relative to another of the substrate or the nozzle gas discharge mechanism, and discharging an etching gas toward the substrate from the discharge hole of the nozzle gas discharge mechanism.
Inventor(s): So OSADA of Kikuchi-gun JP for tokyo electron limited, Katsuya OKUDA of Kumamoto JP for tokyo electron limited, Naohiro IWANAGA of Koshi City JP for tokyo electron limited, Kazuki KOSAI of Koshi City JP for tokyo electron limited, Toshiyuki SHIOKAWA of Koshi City JP for tokyo electron limited
IPC Code(s): G05D7/06, H01L21/67
CPC Code(s): G05D7/0617
Abstract: a liquid supply device includes: a processing liquid line through which a processing liquid is supplied to a liquid processor for performing liquid processing on a substrate; a heating mechanism provided in the processing liquid line to heat the processing liquid flowing through the processing liquid line; a filter provided downstream of the heating mechanism in the processing liquid line; a drain line provided downstream of the filter in the processing liquid line and through which the processing liquid flowing through the processing liquid line is drained; a first temperature sensor configured to respectively detect a temperature of the filter, the processing liquid line, the drain line, or the processing liquid; and a controller configured to determine whether to drain the processing liquid from the drain line based on a detection result by the first temperature sensor.
20250132128. Method and System for Plasma Process_simplified_abstract_(tokyo electron limited)
Inventor(s): Evrim Solmaz of Austin TX US for tokyo electron limited, Du Zhang of Albany NY US for tokyo electron limited, Barton Lane of Austin TX US for tokyo electron limited
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32155
Abstract: a method for a plasma process includes generating plasma within a process chamber with a source power pulse and applying a bias power pulse to a substrate holder within the process chamber. a frequency of the bias power pulse increases from a first frequency value to a second frequency value during the bias power pulse. the bias power pulse occurs after the source power pulse.
Inventor(s): Chishio KOSHIMIZU of Kurokawa-gun JP for tokyo electron limited
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32155
Abstract: a disclosed plasma processing apparatus includes a chamber, a radio frequency power supply, and circuitry. the radio frequency power supply is configured to supply a source radio frequency power to generate a plasma from a gas in the chamber. the circuitry is configured to set a source frequency of the source radio frequency power when the source radio frequency power is supplied alone to suppress a degree of reflection of the source radio frequency power in accordance with the source frequency and the degree of reflection of the source radio frequency power when the source radio frequency power is supplied alone beforehand.
20250132130. PLASMA PROCESSING APPARATUS_simplified_abstract_(tokyo electron limited)
Inventor(s): Nozomu NAGASHIMA of Miyagi JP for tokyo electron limited, Daisuke YOSHIKOSHI of Miyagi JP for tokyo electron limited, Kunihiko YAMAGATA of Miyagi JP for tokyo electron limited
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32174
Abstract: a plasma processing apparatus comprises a first plasma processing apparatus and a second plasma processing apparatus. each of the first plasma processing apparatus and the second plasma processing apparatus comprises a plasma processing chamber, a substrate support, a high frequency power supply, an electrode or an antenna, a power consuming member, a ground frame, an electricity storage unit, a power receiving coil and a rectifying and smoothing unit. the ground frame is grounded and surrounding the substrate support together with the plasma processing chamber. each of the first plasma processing apparatus and the second plasma processing apparatus is configured such that, with respect to the power consuming member thereof, the electricity storage unit thereof and the electricity storage unit of a remaining one of the first plasma processing apparatus and the second plasma processing apparatus are connectable in parallel.
Inventor(s): Hajime TAMURA of Kurokawa-gun JP for tokyo electron limited, Yasuharu SASAKI of Kurokawa-gun JP for tokyo electron limited, Shin YAMAGUCHI of Kurokawa-gun JP for tokyo electron limited, Tsuguto SUGAWARA of Kurokawa-gun JP for tokyo electron limited, Katsuyuki KOIZUMI of Kurokawa-gun JP for tokyo electron limited
IPC Code(s): H01J37/32, H02N13/00
CPC Code(s): H01J37/32715
Abstract: the disclosed substrate support includes a first region, a second region, a first electrode, and a second electrode. the first region is configured to hold a substrate placed thereon. the second region is provided to surround the first region and configured to hold an edge ring placed thereon. the first electrode is provided in the first region to receive a first electrical bias. the second electrode is provided in at least the second region to receive a second electrical bias. the second electrode extends below the first electrode to face the first electrode within the first region.
Inventor(s): Zhiying Chen of Austin TX US for tokyo electron limited, Megan Carruth of Austin TX US for tokyo electron limited, Joel Blakeney of Austin TX US for tokyo electron limited, Shyam Sridhar of Austin TX US for tokyo electron limited, Peter Lowell George Ventzek of Austin TX US for tokyo electron limited
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32935
Abstract: a detector for a plasma measurement system, where the detector includes an insulating substrate including a cavity; a conductive plate spanning an entrance to the cavity; a first aperture through the conductive plate; an iris diaphragm including movable blades around a second aperture, the second aperture being aligned to the first aperture; an ion current collector disposed in the cavity, the iris diaphragm being disposed between the ion current collector and the conductive plate; and a rotatable gear coupled to the movable blades of the iris diaphragm.
Inventor(s): Joshua Baillargeon of Albany NY US for tokyo electron limited, Jinying Lin of Watervliet NY US for tokyo electron limited
IPC Code(s): H01L21/033, H01L21/02, H01L21/311, H01L21/768
CPC Code(s): H01L21/0337
Abstract: a method for fabricating semiconductor devices is disclosed. the method includes forming a stack over a substrate. the method includes forming a hardmask layer over the stack, the hardmask layer comprising a first tungsten containing sub-layer, and at least one compressive sub-layer and at least one tensile sub-layer. the method includes forming a patternable layer over the hardmask layer. the method includes etching the hardmask layer according to the patternable layer.
Inventor(s): Koji Kagawa of Koshi-shi, Kumamoto JP for tokyo electron limited
IPC Code(s): H01L21/311, C09K13/08, H01L21/67
CPC Code(s): H01L21/31111
Abstract: a technique enabling wet etching of a first silicon oxide film with high selectivity with respect to a metal film and a second silicon oxide film is provided. a substrate processing method of wet-etching a substrate having a stacked structure including a metal film, a first silicon oxide film, and a second silicon oxide film having a moisture content lower than that of the first silicon oxide film is provided. the substrate processing method includes performing an etching while increasing etching selectivity of the first silicon oxide film with respect to the second silicon oxide film and the metal film by supplying an etching liquid, which is prepared by diluting sulfuric acid, hydrogen peroxide and hydrofluoric acid in an anhydrous organic solvent, to the substrate such that the metal film, the first silicon oxide film, and the second silicon oxide film are simultaneously exposed to the etching liquid.
20250132167. FILM FORMING METHOD AND PROCESSING SYSTEM_simplified_abstract_(tokyo electron limited)
Inventor(s): Shinya OKABE of Nirasaki City JP for tokyo electron limited, Atsushi MATSUMOTO of Nirasaki City JP for tokyo electron limited, Toshiaki ARIMA of Nirasaki City JP for tokyo electron limited
IPC Code(s): H01L21/3205, C23C16/52, H01L21/02
CPC Code(s): H01L21/32053
Abstract: a film forming method includes: (a) preparing a substrate having a doped region, which contains silicon with an added impurity, formed on a surface; (b) forming a diffusion prevention layer, which contains the impurity, on the doped region; and (c) forming a metal film on the doped region where the diffusion prevention layer is formed, and forming a metal silicide film by a reaction between the metal film and the silicon of the doped region, wherein (b) includes supplying an impurity-containing gas that contains the impurity to the substrate without converting the impurity-containing gas into a plasma.
Inventor(s): So OSADA of Kikuchi-gun JP for tokyo electron limited, Katsuya OKUDA of Kumamoto JP for tokyo electron limited, Naohiro IWANAGA of Koshi City JP for tokyo electron limited, Kazuki KOSAI of Koshi City JP for tokyo electron limited
IPC Code(s): H01L21/67
CPC Code(s): H01L21/67023
Abstract: a liquid supply device includes a tank storing a processing liquid, a circulation line, a pump, and a supply line for supplying the processing liquid to a liquid processor. the circulation line includes a main line, and first and second branch lines branching from the main line. the supply line includes first and second supply lines connected to the first and second branch lines, respectively. the first and second branch lines includes first and second heating mechanisms, first and second filters, first and second drain lines for draining the processing liquid, first and second branch circulation lines for returning the processing liquid to the tank, and first and second valves provided to switch a destination of the processing liquid, respectively.
20250132180. WAFER BOW METROLOGY SYSTEM_simplified_abstract_(tokyo electron limited)
Inventor(s): Hoyoung KANG of Albany NY US for tokyo electron limited
IPC Code(s): H01L21/67, G01B11/25
CPC Code(s): H01L21/67288
Abstract: aspects of the present disclosure provide a metrology system for measuring wafer bow of a wafer. for example, the metrology system can include a wafer support configured to position a wafer for wafer bow measurement, a first light source configured to illuminate a first side of the wafer during the wafer bow measurement, and a first pinhole mask disposed between the first light source and the wafer support. the first pinhole mask can include a plurality of first pinholes that are arranged to pass first light from the first light source and project onto the first side of the wafer a plurality of first dots that correspond to the first pinholes in the first pinhole mask. the metrology system can also include a first camera arranged to capture an image of the first dots from the first side of the wafer during the wafer bow measurement.
Inventor(s): Partha MUKHOPADHYAY of Oviedo FL US for tokyo electron limited, Henry Jim FULFORD of Albany NY US for tokyo electron limited, Mark I. GARDNER of Albany NY US for tokyo electron limited
IPC Code(s): H10B51/20, H10B51/30
CPC Code(s): H10B51/20
Abstract: a semiconductor device includes a first gate structure, a second gate structure, and a semiconductor layer. the first gate structure, the semiconductor layer, and the second gate structure are arranged concentrically. the first gate structure includes a first gate electrode and a ferroelectric layer. the second gate structure includes a second gate electrode and a gate dielectric layer. the semiconductor layer is disposed between the ferroelectric layer and the gate dielectric layer.
20250133743. FERROELECTRIC 3D MEMORY BLOCK UNIT_simplified_abstract_(tokyo electron limited)
Inventor(s): Partha MUKHOPADHYAY of Oviedo FL US for tokyo electron limited, Henry Jim FULFORD of Albany NY US for tokyo electron limited, Mark I. GARDNER of Albany NY US for tokyo electron limited
IPC Code(s): H10B51/30
CPC Code(s): H10B51/30
Abstract: fefet memory devices are provided. a semiconductor device includes a first metal structure of a first gate electrode. the semiconductor device includes a gate dielectric structure extending along a bottom surface of the first metal structure and surrounding a sidewall of the first metal structure. the semiconductor device includes a semiconductor-behaving structure extending along a bottom surface of the gate dielectric structure and surrounding a sidewall of the gate dielectric structure. the semiconductor device includes a ferroelectric structure surrounding a sidewall of the semiconductor-behaving structure. the semiconductor device includes a second gate electrode comprising a second metal structure in contact with the semiconductor-behaving structure.
Tokyo Electron Limited patent applications on April 24th, 2025
- Tokyo Electron Limited
- B08B5/02
- B08B9/00
- C23C16/44
- CPC B08B5/023
- Tokyo electron limited
- C23C16/455
- C23C16/458
- C23C16/52
- CPC C23C16/45544
- H01J37/32
- H01L21/02
- CPC C23C16/45557
- CPC C23C16/45565
- CPC C23C16/4584
- CPC C23C16/52
- G05D7/06
- H01L21/67
- CPC G05D7/0617
- CPC H01J37/32155
- CPC H01J37/32174
- H02N13/00
- CPC H01J37/32715
- CPC H01J37/32935
- H01L21/033
- H01L21/311
- H01L21/768
- CPC H01L21/0337
- C09K13/08
- CPC H01L21/31111
- H01L21/3205
- CPC H01L21/32053
- CPC H01L21/67023
- G01B11/25
- CPC H01L21/67288
- H10B51/20
- H10B51/30
- CPC H10B51/20
- CPC H10B51/30
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