Texas Instruments Incorporated patent applications on February 6th, 2025
Patent Applications by Texas Instruments Incorporated on February 6th, 2025
Texas Instruments Incorporated: 32 patent applications
Texas Instruments Incorporated has applied for patents in the areas of H01L23/00 (3), H01L23/495 (3), H01L29/66 (3), H02M3/158 (2), H01L29/78 (2) B81B3/0075 (1), H01S5/06246 (1), H01L29/7803 (1), H01L29/7787 (1), H01L29/778 (1)
With keywords such as: control, coupled, device, terminal, transistor, semiconductor, layer, circuitry, current, and output in patent application abstracts.
Patent Applications by Texas Instruments Incorporated
Inventor(s): Jeffrey S. Solas of Iloilo City (PH) for texas instruments incorporated, Rujuta Munje of McKinney TX (US) for texas instruments incorporated, Sophia Delpak of Richardson TX (US) for texas instruments incorporated
IPC Code(s): B81B3/00, B81C1/00
CPC Code(s): B81B3/0075
Abstract: a microelectronic device includes a copper structure over an electronic component. the copper structure includes copper having an average grain size greater than 1 micron. the copper structure has a corrosion barrier, which includes primarily cuprous oxide, directly on the copper. the corrosion barrier is exposed at an exterior surface. the microelectronic device is formed by plating copper over a substrate of the microelectronic device. the copper structure with the corrosion barrier is annealed at a temperature of 125� c. to 200� c. in a non-reducing ambient.
Inventor(s): Anil Dowleswarapu of Hyderabad (IN) for texas instruments incorporated, Subramanian Narayan of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G01R31/27, G01R19/165
CPC Code(s): G01R31/27
Abstract: an integrated circuit includes a current sense circuit having an input, an output, and a correction current input terminal between the input and output. a first transistor has a first control input and a first terminal. the first terminal is coupled to the input of the current sense circuit. a second transistor has a second control input and a second terminal. the second control input is coupled to the first control input, and the second terminal is coupled to the correction current input terminal.
Inventor(s): Patrick Ian Oden of McKinney TX (US) for texas instruments incorporated, James Norman Hall of Parker TX (US) for texas instruments incorporated
IPC Code(s): G02B26/08, G02B6/35
CPC Code(s): G02B26/0833
Abstract: in accordance with at least one example of the description, a microelectromechanical systems (mems) device includes a hinge. the mems device also includes a spring tip. additionally, the mems device includes a top layer including a recessed shelf and a top surface, where the recessed shelf is coupled to the hinge.
Inventor(s): Alexander Lyubarsky of Dallas TX (US) for texas instruments incorporated
IPC Code(s): G02B30/35, G02B3/08, G02B26/08, G02B27/01, G02B27/18, G02B30/36, H04N13/32, H04N13/324, H04N13/351
CPC Code(s): G02B30/35
Abstract: an example device includes a screen, a first light source configured to emit a first light at a first angle during a first time period and a second light source configured to emit a second light at a second angle during a second time period. the second angle is different than the first angle. the second time period is different than the first time period. the device includes a spatial light modulator configured to provide a first view of digital content based on the first angle of the first light emitted during the first time period and a second view of the digital content based on the second angle of the second light emitted during the second time period and projection optics configured to project the first view and the second view for presentation via the screen.
Inventor(s): Alexander LYUBARSKY of Dallas TX (US) for texas instruments incorporated
IPC Code(s): G03B21/20, G03B33/08
CPC Code(s): G03B21/2073
Abstract: in an example, a system includes a light splitter configured to reflect first light having a first wavelength and a first polarization, to transmit light having the first wavelength and a second polarization, to transmit light having a second wavelength, and to transmit light having a third wavelength. the system also includes a quarter wave plate optically coupled to the light splitter. the system includes a color wheel optically coupled to the quarter wave plate, the color wheel having a first filter segment, a second filter segment, and a third filter segment. the system also includes a phosphor optically coupled to the color wheel, the phosphor configured to produce second light responsive to receiving the first light, and the color wheel configured to receive the second light and produce light having the second wavelength or the third wavelength.
20250044975. QUICK CLEARING OF REGISTERS_simplified_abstract_(texas instruments incorporated)
Inventor(s): Timothy David ANDERSON of University Park TX (US) for texas instruments incorporated, Duc Quang BUI of Grand Prairie TX (US) for texas instruments incorporated, Soujanya NARNUR of Austin TX (US) for texas instruments incorporated
IPC Code(s): G06F3/06, G06F13/16, G06F15/80
CPC Code(s): G06F3/0652
Abstract: a method of clearing of registers and logic designs with and and or logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.
Inventor(s): Seth Rickard of Dallas TX (US) for texas instruments incorporated, Kristopher Ryan Burney of Garland TX (US) for texas instruments incorporated, Alexander D'Abreu of Dallas TX (US) for texas instruments incorporated, Suyash Jain of Irving TX (US) for texas instruments incorporated, Kumaran Vijayasankar of Allen TX (US) for texas instruments incorporated
IPC Code(s): G06F8/654, G06F8/658
CPC Code(s): G06F8/654
Abstract: an example apparatus includes: interface circuitry; machine-readable instructions; and programmable circuitry configured to at least one of instantiate or execute the machine-readable instructions to: determine a number of memory sectors to shift an original image based on a length of extra data in an updated image in differential image data; shift the original image by the number of memory sectors to create a swap area, the swap area including the number of memory sectors; and construct the updated image based on the differential image data and the original image.
Inventor(s): Venkatesh Natarajan of Bangalore (IN) for texas instruments incorporated, Saya Goud Langadi of Sugar Land TX (US) for texas instruments incorporated, Alexander Tessarolo of Lindfield (AU) for texas instruments incorporated
IPC Code(s): G06F9/30, G06F9/38
CPC Code(s): G06F9/30058
Abstract: an example apparatus includes: address generation circuitry configured to generate a first address associated with a first packet, a second address associated with a second packet, and a third address associated with a third packet, wherein: the first packet includes a branch instruction; the branch instruction includes a first field that specifies a branch target, and a second field that is different from the first field; and the third packet includes the branch target of the branch instruction; buffer circuitry configured to receive the first packet, the second packet, and the third packet; decoder circuitry coupled to the buffer circuitry, the decoder circuitry configured to decode the first packet, the second packet, and the third packet; discontinuity controller circuitry coupled to the buffer circuitry and the decoder circuitry and configured to determine whether to cause the address generation circuitry to generate the second address.
Inventor(s): Sverre BRUBAK of Oslo (NO) for texas instruments incorporated, Ruchi SHANKAR of Bengaluru (IN) for texas instruments incorporated, Praveen KUMAR N of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): G06F12/14
CPC Code(s): G06F12/1408
Abstract: an apparatus includes: a hardware security module; a processor; a memory subsystem; and a controller. the memory subsystem includes a write interface and a memory. the memory includes a first region that is a one-time programmable (otp) region, and a second region that is a shared region. the controller is between the hardware security module, the processor, and the memory subsystem. the controller is configured to: receive an otp write request from the hardware security module; inhibit the providing of shared memory operations by the processor responsive to the otp write request and an acknowledgment from the processor; cause otp data related to the otp write request to be written to the first region of the memory; clear storage of the write interface after writing the otp data is complete; and cease to inhibit the providing of shared memory operations after the storage of the write interface is cleared.
Inventor(s): David M. Thompson of Dallas TX (US) for texas instruments incorporated, Timothy D. Anderson of University Park TX (US) for texas instruments incorporated, Joseph R.M. Zbiciak of San Jose TX (US) for texas instruments incorporated, Abhijeet A. Chachad of Plano TX (US) for texas instruments incorporated, Kai Chirca of Dallas TX (US) for texas instruments incorporated, Matthew D. Pierson of Murphy TX (US) for texas instruments incorporated
IPC Code(s): G06F13/40, G06F13/364, G06F13/42, H04L47/10, H04L47/215
CPC Code(s): G06F13/404
Abstract: this invention is a bus communication protocol. a master device stores bus credits. the master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. upon transmission, the master device decrements the number of stored bus credits. the bus credits correspond to resources on a slave device for receiving bus transactions. the slave device must receive the bus transaction if accompanied by the proper credits. the slave device services the transaction. the slave device then transmits a credit return. the master device adds the corresponding number and types of credits to the stored amount. the slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. in many types of interactions a bus agent may act as both master and slave depending upon the state of the process.
20250045572. QUANTIZATION FOR NEURAL NETWORKS_simplified_abstract_(texas instruments incorporated)
Inventor(s): Varun Tripathi of Gurgaon (IN) for texas instruments incorporated, Manu Mathew of Bangalore (IN) for texas instruments incorporated, Pramod Swami of Bangalore (IN) for texas instruments incorporated, Kumar Desappan of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06N3/0495
CPC Code(s): G06N3/0495
Abstract: disclosed herein are systems and methods for performing post training quantization. a processor obtains fixed-point output values from a layer of an artificial neural network (ann) wherein the layer includes fixed-point weights determined based on floating-point weights and a weight scaling factor determined based on an output scaling factor. next, the processor converts the fixed-point output values to floating-point output values based on the output scaling factor. then, the processor expands a range of floating-point values. next, the processor calculates a new output scaling factor based on the expanded range of floating-point output values. finally, the processor stores the new output scaling factor in an associated memory.
Inventor(s): Giulio Albini of Draper UT (US) for texas instruments incorporated, Jonathan Lane of Sandy UT (US) for texas instruments incorporated
IPC Code(s): G11C16/08, H10B41/30
CPC Code(s): G11C16/08
Abstract: an integrated circuit (ic) including flash memory and cmos logic circuitry and a method of fabrication thereof is disclosed. the ic comprises a substrate including a recessed area of a first region, a flash memory cell gate stack formed in the recessed area, a wordline (wl) transistor formed in the recessed area and coupled with the flash memory cell gate stack, the wl transistor including a wl gate formed over a first gate oxide layer exclusive of nitridation, and a transistor formed in a second area of the substrate separate from the recessed area, the transistor forming at least a portion of logic circuitry of the ic and including a second gate oxide layer having nitridation.
Inventor(s): Nazila Dadvand of Santa Clara CA (US) for texas instruments incorporated, Xuan Mo Li of Chengdu (CN) for texas instruments incorporated, Huo Yun Duan of Chengdu (CN) for texas instruments incorporated
IPC Code(s): H01L21/48, H01L21/683, H01L23/495
CPC Code(s): H01L21/4828
Abstract: a method for forming integrated circuit (ic) packages includes mounting tape on a mold compound of a strip of flat no-leads ic packages. the method also includes sawing the mold compound of the strip of flat no-leads ic packages to form singulated ic packages mounted on the tape. the method further includes immersing the singulated ic packages in a bath of immersion tin to form immersion tin plating on a flank of leads of the singulated ic packages.
Inventor(s): Gail Edselle S. REYES of Angeles City (PH) for texas instruments incorporated, Emerson M. ENIPIN of Angeles City (PH) for texas instruments incorporated
IPC Code(s): H01L23/367, H01L23/00
CPC Code(s): H01L23/3672
Abstract: in some examples, a wafer chip scale package (wcsp) comprises a semiconductor die having a device side in which circuitry is formed and a non-device side opposite the device side, a solder bump electrically coupled to the circuitry, and a mold compound in contact with the device side, the solder bump, and four lateral sides of the semiconductor die. the package also comprises a thermal pad in contact with the non-device side of the semiconductor die and the mold compound.
Inventor(s): Steven Kummerl of Carrollton TX (US) for texas instruments incorporated
IPC Code(s): H01L23/495, H01L21/56, H01L23/00, H01L23/31
CPC Code(s): H01L23/49541
Abstract: an electronic device with a small outline no-lead package having a molded package structure and conductive leads with plated sidewalls exposed along opposite lateral sides of the package structure, a semiconductor die at least partially enclosed by the molded package structure, a first bond wire enclosed by the molded package structure and connected between a first one of the conductive leads and the semiconductor die, and a second bond wire having a first end and an unterminated second end exposed along a further side of the package structure.
Inventor(s): Makoto Shibuya of Tokyo (JP) for texas instruments incorporated, Yasmine Yan of San Jose CA (US) for texas instruments incorporated, Masamitsu Matsuura of Beppu-shi (JP) for texas instruments incorporated, Anindya Poddar of Sunnyvale CA (US) for texas instruments incorporated
IPC Code(s): H01L23/495, H05K1/18
CPC Code(s): H01L23/49555
Abstract: a semiconductor package comprises an integrated circuit die covered by a mold compound to form a four-sided package with a top surface and a bottom surface. a first group of no-lead contacts are exposed on a first side and on the bottom surface of the package. a second group of no-lead contacts are exposed on a second side and on the bottom surface of the package, wherein the second side is opposite the first side. a first external lead extends from a third side of the package. a second external lead extends from a fourth side of the package opposite the third side. the first and second external leads bent to extend above the top surface of the package. the first and second external leads have a gull-wing shape or a j-shape.
Inventor(s): Jaimal Mallory Willamson of McKinney TX (US) for texas instruments incorporated, Michael Todd Wyant of Dallas TX (US) for texas instruments incorporated, Yutaka Suzuki of Allen TX (US) for texas instruments incorporated
IPC Code(s): H01L23/00, H01L21/78, H01L23/31
CPC Code(s): H01L23/562
Abstract: an example device includes: a semiconductor die formed on a semiconductor substrate and having a device side surface, a backside surface opposite the device side surface, and having sides between the device side surface and the backside surface at edges of the semiconductor die; the semiconductor die having a device area comprising electrical devices formed on the semiconductor die, and having a scribe spacing area between the device area and the edges of the semiconductor die; the semiconductor die having polymeric anchors in the scribe spacing area, the polymeric anchors being recesses that extend through a protective overcoat dielectric layer that is over the device side surface of the semiconductor die, and extending into the semiconductor substrate of the semiconductor die; and polymeric material covering at least a portion of the semiconductor die, the polymeric material filling the recesses of the polymeric anchors.
Inventor(s): James Norman Hall of Parker TX (US) for texas instruments incorporated, Terry Alan Bartlett of Dallas TX (US) for texas instruments incorporated, William Craig McDonald of Allen TX (US) for texas instruments incorporated
IPC Code(s): H01S5/062, G02B5/08, H01S5/00
CPC Code(s): H01S5/06246
Abstract: described examples include a device includes a first post and a spring supported by the first post. the device also includes a second post coupled to the spring and a mirror on the second post. additionally, the device includes a movable layer coupled to the spring and to the mirror and a fixed layer, where the movable layer is between the fixed layer and the mirror. the mirror has a width and a length and the length is greater than the width. the mirror is configured to move based on a voltage difference between the movable layer and the fixed layer.
Inventor(s): Janne Pahkala of Oulu (FI) for texas instruments incorporated, Juha Hauru of Oulu (FI) for texas instruments incorporated, Ari Vaananen of Oulu (FI) for texas instruments incorporated
IPC Code(s): H02M1/088, H02M3/158
CPC Code(s): H02M1/088
Abstract: an example apparatus includes: switch control circuitry; and mode control circuitry configured to: in response to a determination that the switch control circuitry is to be operated in a fixed frequency mode, signal a switch control circuitry transition to the switch control circuitry configured to transition the switch control circuitry to an on-time control mode to transmit an on-time control pulse signal to a switch; and in response to the switch control circuitry transition to the on-time control mode, signal the switch control circuitry configured to transmit a fixed frequency mode clock signal to the switch.
20250047199. CHARGE PUMP RECTIFIER_simplified_abstract_(texas instruments incorporated)
Inventor(s): Arvind GUPTA of New Delhi (IN) for texas instruments incorporated, Kashyap BAROT of Bangalore (IN) for texas instruments incorporated, Sreeram Nasum S of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H02M3/07
CPC Code(s): H02M3/07
Abstract: a circuit includes a charge pump stage and a common-mode filter. the charge pump stage includes first and second transistors, and first and second capacitors. the second transistor has a first terminal coupled to a control terminal of the first transistor, has a second terminal, and has a control terminal coupled to a first terminal of the first transistor. the first capacitor is coupled between a second terminal of the first transistor and the control terminal of the first transistor. the second capacitor is coupled between the second terminal of the second transistor and the control terminal of the second transistor. the common-mode filter includes third and fourth capacitors. the third capacitor is coupled between the second terminal of the first transistor and the control terminal of the first transistor. the fourth capacitor is coupled between the third capacitor and the control terminal of the second transistor.
Inventor(s): Karthik Nandimandalam Venkata of Dallas TX (US) for texas instruments incorporated, Siew Kuok Hoon of Plano TX (US) for texas instruments incorporated, Daniel Andrew Mavencamp of Rockwall TX (US) for texas instruments incorporated, Jairo Daniel Olivares of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H02M3/158, G01R19/165, H02J7/00
CPC Code(s): H02M3/1582
Abstract: a device includes a battery current sense circuit configured to generate a battery current feedback voltage based on a current provided to a battery, a current regulation feedback loop configured to regulate the current provided to the battery based on the battery current feedback voltage and a configurable battery current reference voltage, and a precharge regulation feedback loop configured to regulate the current provided to the battery based on the battery current feedback voltage and a configurable precharge reference voltage. the device also includes a processor configured to set the battery current reference voltage to a first value and set the precharge current reference voltage to a second value. the first value is less than the second value during a transition state.
20250047246. AMPLIFIER CIRCUIT_simplified_abstract_(texas instruments incorporated)
Inventor(s): Rajendrakumar JOISH of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03F1/26, H03F3/45
CPC Code(s): H03F1/26
Abstract: an amplifier circuit includes first and second transistors, and a first current source. the first current source is coupled to first terminals of the first and second transistors. the first current source includes a second current source, and third, fourth, fifth, and sixth transistors. the third transistor has a first terminal coupled to a first terminal of the fourth transistor, and a control terminal coupled to a control terminal of the first transistor. the fourth transistor has a control terminal coupled to a control terminal of the second transistor. the fifth transistor has a first terminal coupled to a first terminal of the sixth transistor, a second terminal coupled to the second current source and to the second terminals of the third, fourth, and sixth transistors, and a control terminal coupled to a control terminal of the sixth transistor.
Inventor(s): Gaetano Maria Walter Petrina of Kirchdorf an der Amper (DE) for texas instruments incorporated, Michael Lueders of Freising (DE) for texas instruments incorporated, Nicola Rasera of Unterschleißheim (DE) for texas instruments incorporated
IPC Code(s): H03K5/1534, H02M1/08, H02M1/38, H03K5/00, H03K5/13
CPC Code(s): H03K5/1534
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. an example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.
Inventor(s): Ryan Alexander SMITH of Lucas TX (US) for texas instruments incorporated
IPC Code(s): H03L7/099, H03L7/093
CPC Code(s): H03L7/099
Abstract: systems and methods for controlling a charge pump current in response to a control voltage provided to a voltage-controlled oscillator (vco) are disclosed. an example system includes a phase-locked loop including a charge pump and a vco coupled to the charge pump. current adjusting circuitry receives the control voltage and controls the charge pump current. the current adjusting circuitry is configurable to cause the charge pump current to increase by a first amount responsive to the control voltage being in a first range, and cause the charge pump current to decrease by a second amount responsive to the control voltage being in a second range. a chirp signal output by the phase-locked loop has a bandwidth defined by a first bandwidth segment that corresponds to the control voltage being in the first range and a second bandwidth segment that corresponds to the control voltage being in the second range.
Inventor(s): Veeramanikandan Raju of Bangalore (KA) for texas instruments incorporated, Anand Kumar G of Bangalore (KA) for texas instruments incorporated
IPC Code(s): H04L9/06
CPC Code(s): H04L9/0662
Abstract: a network-communicating device with a signal input adapted to receive a sensor-derived signal; an analog-to-digital converter (adc) having an input coupled to the signal input and an output; a data scrambling circuit having an input coupled to the output of the adc and an output; a watermark insertion circuit having an input coupled to the output of the data scrambling circuit and an output; and a signal output coupled to the output of the watermark insertion circuit.
Inventor(s): Jaiganesh Balakrishnan of Bangalore (IN) for texas instruments incorporated, Aswath VS of Kannur (IN) for texas instruments incorporated, Sriram Murali of Bangalore (IN) for texas instruments incorporated, Sreenath Narayanan Potty of Bangalore (IN) for texas instruments incorporated, Raju Kharataram Chaudhari of Bangaluru (IN) for texas instruments incorporated, Kapil Kumar of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H04L25/03, H04L27/26
CPC Code(s): H04L25/03343
Abstract: an example apparatus described herein to implement cancellation pulse generation includes a first memory storing first subsets of data samples of a single pulse cancellation waveform. the example apparatus includes a second memory storing second subsets of data samples of the single pulse cancellation waveform, the second subsets including different data samples of the single pulse cancellation waveform than the first subsets. the example apparatus includes first circuitry coupled to the first memory and to the second memory in parallel. the example apparatus includes a plurality of buffers. the example apparatus includes second circuitry coupled to the plurality of buffers.
Inventor(s): Pourya Assem of Santa Clara CA (US) for texas instruments incorporated, Kevin Scoones of San Jose CA (US) for texas instruments incorporated, Pavol Balaz of Santa Clara CA (US) for texas instruments incorporated, Tim Merkin of Dallas TX (US) for texas instruments incorporated, Zejian Wang of Shanghai (CN) for texas instruments incorporated, Jianquan Liao of Shanghai (CN) for texas instruments incorporated
IPC Code(s): H04R3/02
CPC Code(s): H04R3/02
Abstract: an apparatus includes a first power stage circuit having a first output and a power terminal, and a second power stage circuit having a second output and the power terminal. the apparatus further includes a control circuit having a control input, a first control output, and a second control output. in an example, the control input is coupled to the power terminal, the first control output is coupled to the first output, and the second control output is coupled to the second output. in an example, the control circuit is configured to, responsive to a first voltage at the power terminal being below a threshold voltage, set the first and second outputs to a second voltage.
20250048656. MULTIPLE STATE PROGRAMMABLE MEMORY_simplified_abstract_(texas instruments incorporated)
Inventor(s): Jack Qian of Plano TX (US) for texas instruments incorporated, Kemal Tamer San of Plano TX (US) for texas instruments incorporated, Guruvayurappan S. Mathur of Allen TX (US) for texas instruments incorporated
IPC Code(s): H10B99/00, H10B20/20
CPC Code(s): H10B99/14
Abstract: described examples include an integrated circuit having a plurality of nominally identical polycrystalline silicon resistors over a semiconductor substrate. each of the polysilicon resistors has a resistor body with a first end and a second end, wherein the first end is connected to a current source and the second end is connected to a resistance discriminator. a first proper subset of the resistors have a first resistance, and a second first proper subset of the resistors have a difference second resistance.
Inventor(s): Ujwal Radhakrishna of San Jose CA (US) for texas instruments incorporated, Zhikai Tang of Sunnyvale CA (US) for texas instruments incorporated, Johan Strydom of Saratoga CA (US) for texas instruments incorporated, Jungwoo Joh of Allen TX (US) for texas instruments incorporated
IPC Code(s): H01L29/778, H01L29/40, H01L29/423, H01L29/45, H01L29/47, H01L29/872
CPC Code(s): H01L29/778
Abstract: the present disclosure generally relates to a semiconductor device that includes a gate electrical contact that forms junctions with different energy barrier heights to a gate layer. in an example, a semiconductor device includes a semiconductor substrate, a drain electrical contact, a source electrical contact, a barrier layer, a gate layer, and a gate electrical contact. the drain and source electrical contacts are on the semiconductor substrate. the barrier layer is over a channel region of the semiconductor substrate between the drain and source electrical contacts. the gate layer is over the barrier layer. the gate layer includes first and second semiconductor portions. the gate electrical contact contacts the gate layer. the gate electrical contact includes first and second metal portions. the first and second metal portions form first and second junctions with the first and second semiconductor portions, respectively. the first and second junctions have different energy barrier heights.
Inventor(s): Nicholas S. DELLAS of Dallas TX (US) for texas instruments incorporated, Qhalid Fareed RANGOON SAYEED of Plano TX (US) for texas instruments incorporated
IPC Code(s): H01L29/778, H01L21/02, H01L29/66
CPC Code(s): H01L29/7787
Abstract: in some examples, a gallium-based device comprises a substrate layer; a first group-iii nitride layer supported by the substrate layer; a second group-iii nitride layer supported by the first group-iii nitride layer; a tunnel barrier layer supported by the second group-iii nitride layer; a passivation layer supported by the tunnel barrier layer; and source, gate, and drain contact structures supported by the first group-iii nitride layer.
Inventor(s): Eung Jung Kim of Allen TX (US) for texas instruments incorporated, Thomas Grebs of Fishkill NY (US) for texas instruments incorporated, Sunglyong Kim of Allen TX (US) for texas instruments incorporated, Sungho Beck of CARROLLTON TX (US) for texas instruments incorporated, Wei Fu of Allen TX (US) for texas instruments incorporated, Xiaochun Zhao of Allen TX (US) for texas instruments incorporated, Arjun Pankaj of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H01L29/78, H01L27/06, H01L27/092, H01L29/06, H01L29/40, H01L29/66, H01L29/786
CPC Code(s): H01L29/7803
Abstract: described examples include an integrated circuit having first and second transistors. the first transistor includes a plurality of trenches extending into a semiconductor substrate and a plurality of source regions, each source region located between a pair of adjacent trenches. a first source terminal is connected to the plurality of source regions. the second transistor includes a central source region between a pair of the trenches and a second source terminal connected to the central source region. the second source terminal is conductively isolated from the first source terminal.
Inventor(s): Mahalingam Nandakumar of Richardson TX (US) for texas instruments incorporated, Brian Edward Hornung of Richardson TX (US) for texas instruments incorporated
IPC Code(s): H01L27/088, H01L21/225, H01L21/265, H01L21/266, H01L21/8234, H01L29/08, H01L29/66, H01L29/78
CPC Code(s): H01L27/088
Abstract: the present disclosure provides a method for forming a semiconductor device containing mos transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. in devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. the diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.
Texas Instruments Incorporated patent applications on February 6th, 2025
- Texas Instruments Incorporated
- B81B3/00
- B81C1/00
- CPC B81B3/0075
- Texas instruments incorporated
- G01R31/27
- G01R19/165
- CPC G01R31/27
- G02B26/08
- G02B6/35
- CPC G02B26/0833
- G02B30/35
- G02B3/08
- G02B27/01
- G02B27/18
- G02B30/36
- H04N13/32
- H04N13/324
- H04N13/351
- CPC G02B30/35
- G03B21/20
- G03B33/08
- CPC G03B21/2073
- G06F3/06
- G06F13/16
- G06F15/80
- CPC G06F3/0652
- G06F8/654
- G06F8/658
- CPC G06F8/654
- G06F9/30
- G06F9/38
- CPC G06F9/30058
- G06F12/14
- CPC G06F12/1408
- G06F13/40
- G06F13/364
- G06F13/42
- H04L47/10
- H04L47/215
- CPC G06F13/404
- G06N3/0495
- CPC G06N3/0495
- G11C16/08
- H10B41/30
- CPC G11C16/08
- H01L21/48
- H01L21/683
- H01L23/495
- CPC H01L21/4828
- H01L23/367
- H01L23/00
- CPC H01L23/3672
- H01L21/56
- H01L23/31
- CPC H01L23/49541
- H05K1/18
- CPC H01L23/49555
- H01L21/78
- CPC H01L23/562
- H01S5/062
- G02B5/08
- H01S5/00
- CPC H01S5/06246
- H02M1/088
- H02M3/158
- CPC H02M1/088
- H02M3/07
- CPC H02M3/07
- H02J7/00
- CPC H02M3/1582
- H03F1/26
- H03F3/45
- CPC H03F1/26
- H03K5/1534
- H02M1/08
- H02M1/38
- H03K5/00
- H03K5/13
- CPC H03K5/1534
- H03L7/099
- H03L7/093
- CPC H03L7/099
- H04L9/06
- CPC H04L9/0662
- H04L25/03
- H04L27/26
- CPC H04L25/03343
- H04R3/02
- CPC H04R3/02
- H10B99/00
- H10B20/20
- CPC H10B99/14
- H01L29/778
- H01L29/40
- H01L29/423
- H01L29/45
- H01L29/47
- H01L29/872
- CPC H01L29/778
- H01L21/02
- H01L29/66
- CPC H01L29/7787
- H01L29/78
- H01L27/06
- H01L27/092
- H01L29/06
- H01L29/786
- CPC H01L29/7803
- H01L27/088
- H01L21/225
- H01L21/265
- H01L21/266
- H01L21/8234
- H01L29/08
- CPC H01L27/088
