MEMORY DEVICE STRUCTURE AND METHOD

Organization Name

taiwan semiconductor manufacturing company, ltd.

Inventor(s)

MEMORY DEVICE STRUCTURE AND METHOD

This abstract first appeared for US patent application 20250016983 titled 'MEMORY DEVICE STRUCTURE AND METHOD

Original Abstract Submitted

memory cells, semiconductor devices, semiconductor stacked structures, and fabrication methods are provided. an example memory cell includes a capacitor and a transistor stacked over the capacitor in a compact configuration. the capacitor includes a floating gate, a high-k dielectric layer, and a metal gate. the metal gate extends horizontally from a first sidewall to a second sidewall and vertically from a bottom surface to a top surface. the transistor includes the metal gate and a gate dielectric layer disposed on the metal gate. the gate dielectric layer includes two side portions respectively disposed on the two sidewalls of the metal gate and, and a top portion disposed on the top surface of the metal gate. the transistor further includes two separate s/d regions respectively formed on the two side portions of the gate dielectric layer, and a channel region formed on the top portion of the gate dielectric layer.