INTEGRATED CIRCUIT PACKAGES

Organization Name

taiwan semiconductor manufacturing company, ltd.

Inventor(s)

INTEGRATED CIRCUIT PACKAGES - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240282720 titled 'INTEGRATED CIRCUIT PACKAGES

The abstract describes a device with an integrated circuit die encapsulated by an encapsulant, a conductive via extending through the encapsulant, and a redistribution structure on the encapsulant.

The redistribution structure includes a metallization pattern electrically coupled to the integrated circuit die and the conductive via.
A dielectric layer with a specific thickness is on the metallization pattern.
A first under-bump metallurgy (UBM) is physically and electrically coupled to the metallization pattern, with a specific width and ratio to the dielectric layer thickness.

Potential Applications: - This technology can be used in semiconductor devices, electronic components, and integrated circuits. - It can be applied in various industries such as telecommunications, consumer electronics, and automotive electronics.

Problems Solved: - Provides a reliable and efficient way to electrically connect components in a device. - Enhances the performance and durability of integrated circuits.

Benefits: - Improved electrical connectivity and signal transmission. - Enhanced overall functionality and longevity of electronic devices.

Commercial Applications: - This technology can be utilized in the manufacturing of advanced electronic devices, leading to improved product performance and reliability in the market.

Questions about the technology: 1. How does the specific thickness of the dielectric layer impact the performance of the device? 2. What are the advantages of using a conductive via in the encapsulation process?

Frequently Updated Research: - Stay updated on the latest advancements in semiconductor packaging technologies to ensure the competitiveness and relevance of this innovation in the market.

Original Abstract Submitted

in an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a conductive via extending through the encapsulant; a redistribution structure on the encapsulant, the redistribution structure including: a metallization pattern electrically coupled to the conductive via and the integrated circuit die; a dielectric layer on the metallization pattern, the dielectric layer having a first thickness of 10 �m to 30 �m; and a first under-bump metallurgy (ubm) having a first via portion extending through the dielectric layer and a first bump portion on the dielectric layer, the first ubm being physically and electrically coupled to the metallization pattern, the first via portion having a first width, a ratio of the first thickness to the first width being from 1.33 to 1.66.