MEMORY ARRAY WITH ASYMMETRIC BIT-LINE ARCHITECTURE

Organization Name

taiwan semiconductor manufacturing company, ltd.

Inventor(s)

Hung-Li Chiang of Taipei City TW

Chao-Ching Cheng of Hsinchu City TW

Jung-Piao Chiu of Kaohsiung City TW

Tzu-Chiang Chen of Hsinchu City TW

Yu-Sheng Chen of Taoyuan City TW

MEMORY ARRAY WITH ASYMMETRIC BIT-LINE ARCHITECTURE

This abstract first appeared for US patent application 20240260279 titled 'MEMORY ARRAY WITH ASYMMETRIC BIT-LINE ARCHITECTURE

Original Abstract Submitted

the present disclosure relates to an integrated chip structure. the integrated chip structure includes a plurality of memory stacks disposed over a substrate and respectively having a plurality of conductive segments stacked onto one another. one or more data storage structures are on the plurality of memory stacks, one or more selectors are over the one or more data storage structures, and an upper conductor over the one or more selectors. the plurality of memory stacks include a first memory stack, a second memory stack, and a third memory stack. the first memory stack and the third memory stack are closest memory stacks to opposing sides of the second memory stack. the first memory stack is closer to the second memory stack than the third memory stack.