Taiwan semiconductor manufacturing co., ltd. (20250112137). INTEGRATED CIRCUIT PACKAGE AND METHOD
INTEGRATED CIRCUIT PACKAGE AND METHOD
Organization Name
taiwan semiconductor manufacturing co., ltd.
Inventor(s)
Po-Yao Lin of Zhudong Township TW
INTEGRATED CIRCUIT PACKAGE AND METHOD
This abstract first appeared for US patent application 20250112137 titled 'INTEGRATED CIRCUIT PACKAGE AND METHOD
Original Abstract Submitted
a method of manufacturing a device includes bonding a first die and a second die to a first side of a substrate, forming a stress buffer structure over the first die and the second die, where the stress buffer structure includes a first portion of a first via extending through a first insulating layer, a second portion of the first via extending through a second insulating layer, and a third portion of the first via extending through a third insulating layer, where the second portion of the first via is disposed between the first portion of the first via and the third portion of the first via, and where a diameter of the second portion of the first via is smaller than diameters of the first portion of the first via and the third portion of the first via, and depositing a metal layer over the stress buffer structure.