SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Organization Name

taiwan semiconductor manufacturing co., ltd.

Inventor(s)

Wei-Yip Loh of Hsinchu City (TW)

Hung-Hsu Chen of Tainan City (TW)

Chih-Chien Chi of Hsinchu City (TW)

Harry Chien of Chandler AZ (US)

Chih-Wei Chang of Hsinchu County (TW)

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

This abstract first appeared for US patent application 20240429102 titled 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Original Abstract Submitted

a method includes forming a bottom-tier transistor and a top-tier transistor over the bottom-tier transistor, the top-tier transistor comprising a first channel layer, a first gate structure around the first channel layer, and a plurality of first source/drain regions on opposite sides of the first channel layer; forming a first dielectric layer over the first source/drain regions of the top-tier transistor; etching the first dielectric layer to form a first opening exposing one of the first source/drain regions of the top-tier transistor; selectively forming a first metal silicide on the one of the first source/drain regions; selectively forming a first metal cap on the first metal silicide and not on the first dielectric layer; forming a front-side contact on the first metal cap.