Patent Applications by Taiwan Semiconductor Manufacturing Company Ltd on 21st August 2025

Taiwan Semiconductor Manufacturing Company Ltd: 52 patent applications

Taiwan Semiconductor Manufacturing Company Ltd has applied for patents in the areas of H10D64/017 (Technology classification, 11), H10D30/6735 (Technology classification, 9), H10D30/6757 (Technology classification, 9), H10D62/121 (Technology classification, 9), H10D84/038 (Technology classification, 8)

Patent Applications by Taiwan Semiconductor Manufacturing Company Ltd

20250264793. EUV PHOTO MASKS AND MANUFACTURING METHOD THEREOF

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed over the substrate, a capping layer disposed over the reflective multilayer, an intermediate layer disposed over the capping layer, an absorber layer disposed over the intermediate layer, and a cover layer disposed over the abs...

20250264816. LEVELING SYSTEM FOR CANTILEVER CALIBRATION

Abstract: In a micro-electromechanical system (MEMS) structure, leveling of a cantilever is performed using a dual-capacitor leveling system. One capacitor is used to determine the amount or degree of deformation. The other capacitor is used in conjunction with a diode to determine the direction of the deform...

20250265399. ANALYSIS METHOD AND ANALYSIS DEVICE

Abstract: An analysis method and an analysis device are provided. The analysis method includes the following. A static timing analysis is performed on a circuit model under test to select multiple selected signal paths violating timing constraints in the circuit model under test. Multiple timing information o...

20250265405. Locating Instances in a Layout

Abstract: Systems and methods for finding instances in a circuit layout are described. A method of finding instances comprises assigning an initial name and an initial position to a tracking cell in a bottom instance of a plurality of instances determining whether the initial name corresponds to a name of a t...

20250265406. REDUCED AREA STANDARD CELL ABUTMENT CONFIGURATIONS

Abstract: A method of designing a semiconductor device includes: analyzing, in a first layout design, a first abutment between a first cell block and a second cell block having a topographic mismatch in one or more of cell height, line width, or line spacing between the first and second cell blocks; selecting...

20250266064. SYSTEM FOR CONTROLLING TEMPERATURES OF MEMORY AND METHOD OF OPERATING SAME

Abstract: A system (for controlling temperatures in a memory) includes: a high bandwidth memory (HBM) including core dies, the HBM being arranged into portions, each of the portions including memory cells, the HBM further including: a first sensing unit configured to generate a first environmental signal corr...

20250266073. EMBEDDED FERROELECTRIC MEMORY CELL

Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first select gate and a second select gate disposed over a substrate. A first ferroelectric random access memory (FeRAM) stack and a second FeRAM stack disposed over the substrate and laterally b...

20250266085. INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD OF THE SAME

Abstract: A device is provided, including a latch circuit, a first pass-gate transistor, and a second pass-gate transistor. The latch circuit stores a bit data and is arranged in a first layer. The first pass-gate transistor and the second pass-gate transistor are arranged in a second layer separated from the...

20250266086. MEMORY CIRCUITS WITH DYNAMICALLY ADJUSTABLE PULSE WIDTHS AND METHODS FOR OPERATING THE SAME

Abstract: A circuit includes an array including a plurality of memory cells; a driver operatively coupled to the array and configured to provide an access signal controlling an access to one or more of the plurality of memory cells; and a timing controller operatively coupled to the driver. The timing control...

20250266113. MEMORY CIRCUIT AND METHOD OF OPERATING SAME

Abstract: A method of operating a memory circuit includes turning on a first programming device and turning on a first selection device thereby causing a first current to flow through a first fuse element. The first fuse element is coupled between the first selection device and the first programming device. T...

20250266275. AUTOMATED SEMICONDUCTOR WAFER TRANSFER MONITORING

Abstract: Semiconductor wafer transfer monitoring includes measuring vibration of a component during a transfer of a semiconductor wafer. The measured vibration is analyzed to detect a collision or scratching of the semiconductor wafer during the transfer. At least one remedial action is performed in response...

20250266290. Multigate Device Structure with Engineered Cladding and Method Making the Same

Abstract: The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor...

20250266299. SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION AND METHOD FOR MANUFACTURING THE SAME

Abstract: A semiconductor device includes a semiconductor substrate, active elements, first insulating film, an electrode pad, a second insulating film, a ring-shaped dummy portion, island-shaped dummy portions, and a Through Silicon VIA electrode. The semiconductor substrate has an obverse surface, which is ...

20250266300. METHOD FOR FORMING SEMICONDUCTOR STRUCTURE

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first passivation layer over an interconnect structure. The first passivation exposes a conductive feature electrically connected to the interconnect structure. The method includes performing an electrical test...

20250266303. DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF

Abstract: A method includes bonding a first package component to a substrate; forming a first dielectric material laterally surrounding the first package components; forming a first probe pad over the first dielectric material, a first bond pad on the first package component, and a first metal line connecting...