Patent Applications by Taiwan Semiconductor Manufacturing Company Ltd on 18th September 2025

Taiwan Semiconductor Manufacturing Company Ltd: 71 patent applications

Taiwan Semiconductor Manufacturing Company Ltd has applied for patents in the areas of H10D84/038 (Technology classification, 10), H10D30/6735 (Technology classification, 8), H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS, 6), H10D30/6757 (Technology classification, 6), H10D64/017 (Technology classification, 6)

Patent Applications by Taiwan Semiconductor Manufacturing Company Ltd

20250289089. HIGH-THROUGHPUT, PRECISE SEMICONDUCTOR SLURRY BLENDING TOOL

Abstract: A slurry blending tool may include a blending tank to receive and blend one or more materials into a slurry, and at least one inlet pipe connected to the blending tank and to provide the one or more materials to the blending tank. The at least one inlet pipe may vertically enter the blending tank an...

20250289093. SYSTEM AND METHOD FOR REAL TIME INLINE MIXING CMP SLURRY

Abstract: An inline CMP slurry mixing system includes a mixing device having a container and a blender, a removal rate sensor disposed adjacent to a CMP platen, a signal processor, and a process controller. The container is in fluid connection to a base slurry supply and additive supplies. The blender mixes a...

20250290807. TEMPERATURE COEFFICIENT CALIBRATION OF RESISTOR THERMAL SENSORS

Abstract: A method of calibrating a temperature coefficient of a thermal sensor. The method includes determining a resistance temperature coefficient function (RTCF) based on resistance measurements of resistors on a plurality of semiconductor die at a first temperature and temperature coefficients for the pl...

20250290819. DETECTION OF CHAMBER SEALING LEAKAGE

Abstract: A sealing monitoring device for a chamber includes a support attached to a front of a sputtering target, and a pressure sensor attached to the support. The sensor is positioned vertically between the front of the target and a parallel top of a shield of the chamber parallel, and laterally positioned...

20250290981. SCAN CHAIN CONTROL

Abstract: Embodiments of the present disclosure are directed to scan chain systems and methods for inputting repeated sequences of bits to a sequence of flip flops that include multi-bit flip flops and single bit flip flops. One example includes a control circuit that includes a bit counter, a multiplexer, a ...

20250291091. EMBEDDED LENS STRUCTURES AND THE METHODS OF FORMING THE SAME

Abstract: A method includes forming sacrificial blocks on a substrate, reflowing the sacrificial blocks, performing a first etching process to etch both of the sacrificial blocks and the substrate until parts of the substrate that are etched to form micro lenses, forming a patterned etching mask, and performi...

20250291118. MULTILAYER STRUCTURE FOR OPTICAL COUPLING AND FABRICATION METHOD THEREOF

Abstract: An apparatus for optical coupling according to the present disclosure includes a substrate, a reflecting layer disposed on the substrate, a lower grating layer above the reflecting layer, and an upper grating layer above the lower grating layer. The lower grating layer includes a base layer and a lo...

20250291263. SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION

Abstract: An extreme ultraviolet (EUV) source includes a collector associated with the vessel. The extreme ultraviolet (EUV) source includes a plurality of vanes along walls of the vessel. Each vane includes a stacked vane segment, and the stacked vane segments for each vane are stacked in a direction of drai...

20250291549. GENERATING MULTIPLY AND ACCUMULATION CALCULATION RESULTS WHILE REDUCING POWER CONSUMPTION AND INCREASING PERFORMANCE

Abstract: A system and method of operating the system are disclosed. In one aspect, a system includes a memory circuit storing data for a compute-in-memory (CIM) operation. The system includes an adder circuit receiving a plurality of inputs from a plurality of input devices and the memory circuit. The system...

20250291989. Circuit Synthesis Optimization for Implements on Integrated Circuit

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined ...

20250291992. MEMORY CELL ARRAY CIRCUIT AND METHOD OF FORMING THE SAME

Abstract: A memory cell array includes a first and a second column of memory cells, a first and a second bit line, a source line and a first set of vias. The second bit line includes a first conductive line located on a first metal layer, and a second conductive line located on a second metal layer. The first...

20250291993. MEMORY DEVICE, COMPUTER-READABLE RECORDING MEDIUM AND SYSTEM

Abstract: A memory device includes bit lines, word lines, and memory cells each including a capacitor and a transistor. The transistor has a gate terminal coupled to a corresponding word line among the word lines, a first terminal, and a second terminal. The capacitor has a first end coupled to the first term...

20250291994. INTEGRATED CIRCUIT, SYSTEM AND METHOD OF FORMING THE SAME

Abstract: An integrated circuit includes a first power rail, a first and second active region in in a front-side of a substrate, a first contact and a first via. The first power rail is configured to supply a first supply voltage, and is on a back-side of the substrate. The first active region overlaps the fi...

20250291996. INTEGRATED CIRCUIT FIN STRUCTURE MANUFACTURING METHOD

Abstract: A method of manufacturing an integrated circuit (IC) device includes constructing a first row of fin field-effect transistors (FinFETs) by forming a first total number of one of n-type fins or p-type fins, constructing a second row of FinFETs adjacent to the first row of FinFETs by forming a second ...

20250292810. INTEGRATED CIRCUIT, SYSTEM AND METHOD OF FORMING THE SAME

Abstract: A memory cell includes a first, second, third, and fourth transistor, a first and a second inverter, and a first conductor and first word line bar. The second transistor is below the first transistor, and is configured as a first pass-gate transistor. The fourth transistor is below the third transis...