Patent Applications by Taiwan Semiconductor Manufacturing Company Ltd on 17th July 2025

Taiwan Semiconductor Manufacturing Company Ltd: 65 patent applications

Taiwan Semiconductor Manufacturing Company Ltd has applied for patents in the areas of H10D30/6735 (Technology classification, 19), H10D30/43 (Technology classification, 18), H10D30/6757 (Technology classification, 18), H10D62/121 (Technology classification, 18), H10D30/014 (Technology classification, 14)

Patent Applications by Taiwan Semiconductor Manufacturing Company Ltd

20250230039. MEMS ARM FOR MICROELECTROMECHANICAL SYSTEM

Abstract: To fabricate a microelectromechanical (MEMS) arm, a release structure is disposed on a base structure having an anchor structure. A lower protective dielectric layer is deposited on the release structure. An arm structure is formed on the lower protective dielectric layer and on the anchor structure...

20250230536. DEPOSITION SYSTEM FOR HIGH ACCURACY PATTERNING

Abstract: The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes...

20250231233. REPACKAGING IC CHIP FOR FAULT IDENTIFICATION

Abstract: A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT...

20250231235. SCAN CHAINS WITH MULTI-BIT CELLS AND METHODS FOR TESTING THE SAME

Abstract: A circuit includes a scan chain comprising a cell structure, wherein the cell structure comprises a first plural number (N) of stages, and each of the stages is configured to store a bit. The circuit includes a second plural number(S) of multiplexers operatively coupled to the scan chain, wherein th...

20250231340. SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a dielectric layer, an etching stop layer, a silicide layer, and a contact metal. The semiconductor substrate has a groove. The dielectric layer and the etching stop layer are disposed in the groov...

20250231474. APPARATUSES AND METHODS FOR ASSESSING DEEP ULTRAVIOLET REFLECTIVITY OF A PELLICLE FOR AN EXTREME ULTRAVIOLET PHOTOLITHOGRAPHY MASK

Abstract: A two-dimensional deep ultraviolet (DUV) reflectivity map of an extreme ultraviolet (EUV) pellicle is acquired using a DUV reflectance measurement assembly having a DUV light source and a DUV spectrophotometer. A representation of the two-dimensional DUV reflectivity map may be displayed. Additional...

20250231475. PELLICLE STRUCTURE FOR EUV LITHOGRAPHY AND METHODS OF MANUFACTURING THEREOF

Abstract: A method of manufacturing a semiconductor device includes heating a pellicle disposed over a photomask. Actinic radiation is passed through the pellicle to selectively expose a photoresist layer on a substrate. The selectively exposed photoresist layer is developed to form a pattern in the photoresi...

20250231490. WAFER HOLDER APPARATUS, SYSTEM AND METHOD OF FORMING SAME

Abstract: A coating and developing tool includes a coater to coat a semiconductor wafer with a photoresist layer, a developer to develop a latent image formed in a photoresist layer coating a semiconductor wafer, and a robotic transfer arm to transfer a semiconductor wafer between the coating and developing t...

20250231501. EUV WAFER DEFECT IMPROVEMENT AND METHOD OF COLLECTING NONCONDUCTIVE PARTICLES

Abstract: An EUV lithographic apparatus includes a wafer stage and a particle removing assembly for cleaning a wafer for an extreme ultraviolet (EUV) lithographic apparatus. The wafer stage includes a measurement side and an exposure side. The particle removing assembly includes particle removing electrodes, ...

20250231740. SYSTEMS AND METHODS FOR CONFIGURABLE ADDER CIRCUIT

Abstract: A system includes a computation circuit, a memory array operably coupled with the computation circuit, and a controller configured to input a plurality of input data bits to the computation circuit, identify a number of accumulation associated with the plurality of input data bits, based on the numb...

20250231863. COMPUTE-IN-MEMORY CIRCUITS AND METHODS FOR OPERATING THE SAME

Abstract: A memory circuit includes a first memory array comprising a plurality of first memory cells, the plurality of first memory cells configured to store a first data element; a second memory array comprising a plurality of second memory cells, the plurality of second memory cells configured to store a s...

20250232101. INTEGRATED CIRCUIT DESIGN SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT

Abstract: A method is performed at least partially by a processor and includes, based on design specifications of a voltage regulator, determining parameters of the voltage regulator. The method further includes, based on the parameters of the voltage regulator, determining model parameters of a voltage regul...

20250232105. SYSTEMS AND METHODS OF ESTIMATING THERMAL PROPERTIES OF SEMICONDUCTOR DEVICES

Abstract: A method includes: receiving a layout of an integrated circuit; identifying, based on the layout, at least a first net and at least a second net, wherein the first net extends through the integrated circuit along a vertical direction, and the second net terminates at a middle portion of the integrat...

20250232163. MEMORY CIRCUITS WITH MULTI-ROW STORAGE CELLS AND METHODS FOR OPERATING THE SAME

Abstract: A memory circuit includes a first buffer configured to store a plurality of first data elements; a second buffer configured to store a plurality of second data elements; a controller configured to generate a control signal based on a layer type; an array comprising a plurality of processing elements...

20250232804. MEMORY DEVICES WITH RC TRACKING AND METHODS FOR OPERATING THE SAME

Abstract: A memory circuit includes a memory array comprising a plurality of memory cells arranged over a plurality of word lines and along a bit line, and a controller operatively coupled to the memory array and comprising an RC detector. The RC detector is configured to advance a timing for a first tracking...