Patent Applications by Taiwan Semiconductor Manufacturing Company Ltd on 14th August 2025

Taiwan Semiconductor Manufacturing Company Ltd: 33 patent applications

Taiwan Semiconductor Manufacturing Company Ltd has applied for patents in the areas of H10D84/038 (Technology classification, 9), H10D30/6735 (Technology classification, 7), H10D30/6757 (Technology classification, 6), H10D62/121 (Technology classification, 4), H10D84/0158 (Technology classification, 4)

Patent Applications by Taiwan Semiconductor Manufacturing Company Ltd

20250258336. STRESS STRUCTURES FOR MODULATING OPTICAL DEVICES

Abstract: A photonic integrated circuit (PIC) includes a stress structure that produces a stress field that enhances an optical device. The enhancement may enlarge an optical mode of the optical device, control an optical mode of the optical device, induce a transition between TM mode preferred and TE mode pr...

20250258990. HARD-TO-FIX (HTF) DESIGN RULE CHECK (DRC) VIOLATIONS PREDICTION

Abstract: A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among t...

20250259292. SEMICONDUCTOR TOPOGRAPHY SIMULATION OF NON-REMOVAL TYPE PROCESSES

Abstract: The present disclosure provides a method for topography simulation of a physical structure under a topography-changing process. The method includes initializing a voxel mesh as a three-dimensional (3D) representation of a physical structure by a general-purpose processor, generating a plurality of p...

20250259667. Word Line Delay Interlock Circuit for Write Operation

Abstract: Systems, methods, and devices are described herein for a word line interlock circuit. A device includes a first logic gate, an interlock circuit, and a delay circuit. The first logic gate is configured to receive a reset signal. The interlock circuit is coupled to an output of the first logic gate a...

20250259675. Bit Line Pre-Charge Circuit for Power Management Modes in Multi Bank SRAM

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior...

20250259836. PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN

Abstract: A method of forming a photoresist pattern includes forming an upper layer including a floating additive polymer over a photoresist layer formed on a substrate. The photoresist layer is selectively exposed to actinic radiation. The photoresist layer is developed to form a pattern in the photoresist l...

20250259843. DUAL CRITICAL DIMENSION PATTERNING

Abstract: A patterning process is performed on a semiconductor wafer coated with a bottom layer, a middle layer and a photoresist layer having a starting thickness. The patterning process includes: performing an exposure step including exposing the semiconductor wafer using a mask that includes a feature whic...

20250259844. METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND COMPOSITION INCLUDING FLOATING ADDITIVE

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer including a photoresist composition over a substrate and forming a floating additive layer comprising a floating additive polymer. The floating additive polymer includes a pendant fluorine substituted organic group...

20250259847. Threshold Voltage Tuning Using Aluminum Layer as Dipole Material

Abstract: Dipole engineering techniques are disclosed herein that may be implemented when fabricating gate stacks, such as a gate stack of a transistor. An exemplary method for forming a gate stack of a transistor includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high...

20250259904. SEMICONDUCTOR PACKAGE STRUCTURE HAVING RING PORTION WITH RECESS FOR ADHESIVE

Abstract: A package structure is provided. The package structure includes a substrate, a cover element disposed on the substrate and having a recess formed from a first surface of the cover element, a semiconductor device disposed on the substrate, a protruding element extending from a second surface of the s...

20250259911. SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a first conductive feature disposed between two substrate portions, a second conductive feature disposed over the first conductive feature, a third conductive feature...

20250259913. SEMICONDUCTOR PACKAGE HAVING COMPOSITE SEED-BARRIER LAYER AND METHOD OF FORMING THE SAME

Abstract: A semiconductor package includes a substrate, a composite seed-barrier layer, a routing via, and a semiconductor die. The substrate has a through hole formed therethrough. The composite seed-barrier layer extends on sidewalls of the through hole and includes a first barrier layer, a seed layer, and ...

20250259930. INTEGRATED CIRCUIT DEVICE AND METHOD

Abstract: An integrated circuit (IC) device includes a first conductive line on a front side of a semiconductor wafer, a first power rail on a back side of the semiconductor wafer, a first gate structure extending in a first direction on the front side of the semiconductor wafer, first and second active regio...

20250259932. DIELECTRIC ON WIRE STRUCTURE TO INCREASE PROCESSING WINDOW FOR OVERLYING VIA

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect ...

20250259939. PHOTONICS INTEGRATED CIRCUIT PACKAGE

Abstract: An integrated circuit package integrates a photonic die (oDie) and an electronic die (eDie). More specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the oDie and/or the eDie, where molded material at least partiall...