Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on September 5th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on September 5th, 2024
Taiwan Semiconductor Manufacturing Company, Ltd.: 56 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L29/66 (15), H01L21/8234 (11), H01L29/06 (11), H01L23/00 (9), H01L29/786 (8) H01L24/13 (2), H01L21/823814 (2), H01L29/785 (2), B29C45/14655 (1), H01L29/4991 (1)
With keywords such as: layer, structure, semiconductor, dielectric, forming, region, fin, gate, portion, and substrate in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Sheng-Feng Weng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Shi Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hsiang Chiu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Tong Lai of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Min Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B29C45/14, B29C45/00, B29C45/03, H01L21/56
CPC Code(s): B29C45/14655
Abstract: a molded semiconductor device includes a semiconductor device and a molding material encapsulating the semiconductor device, wherein an upper surface of the molding material is substantially coplanar with an upper surface of the semiconductor device and comprises a groove at least partially surrounding the upper surface of the semiconductor device.
Inventor(s): Yueh-Sheng HSU of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Kun Zhu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B62B5/00, B62B3/00, B62B3/04, B62B3/10
CPC Code(s): B62B5/0006
Abstract: the present disclosure provides a transporting apparatus. the transporting apparatus can include the following components: a first frame support configured to support an object; a second frame support configured to roll the transporting apparatus and to move relative to the first frame support; and a plurality of shock absorbing elements positioned between the first frame support and the second frame support.
Inventor(s): Chia-En Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Che Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ku-Feng Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yih Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01R31/3177, G01R31/317, G01R31/3185, H03K19/173
CPC Code(s): G01R31/3177
Abstract: a circuit includes a plurality of first inputs corresponding to a first i/o of an i/o circuit and configured to receive at least a first input signal or a second input signal; a multiplexer compressor coupled to the plurality of first inputs, and configured to alternately form a first testing path for the first input signal and a second testing path for the second input signal; a first output configured to provide a first output signal, through one of the first testing path or the second testing path, as a shifted version of a third input signal; and a second output configured to provide a second output signal, through one of the first testing path or the second testing path, as a captured version of the first input signal or the second input signal.
Inventor(s): Wei-Han HUANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hao Yuan CHANG of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Hwan KAO of Baoshan Shiang (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, G03F7/16, G03F7/32
CPC Code(s): G03F7/0025
Abstract: a method for manufacturing a semiconductor device includes forming a photoresist layer comprising a photoresist composition over a substrate to form a photoresist-coated substrate. the photoresist layer is selectively exposed to actinic radiation to form a latent pattern in the photoresist layer. the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a patterned photoresist layer exposing a portion of the substrate, and a purge gas is applied to the patterned photoresist layer.
Inventor(s): Chih-Tsung SHIH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Ming WANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yahru CHENG of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Tsun LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung Chuan LEE of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/11, G03F7/16, G03F7/20, G03F7/38
CPC Code(s): G03F7/11
Abstract: a method of generating a layout pattern includes disposing a photoresist layer of a resist material on a substrate and disposing a top layer over of the photoresist layer. the top layer is transparent for extreme ultraviolet (euv) radiation and the top layer is opaque for deep ultraviolet (duv) radiation. the method further includes irradiating the photoresist layer with radiation generated from an euv radiation source. the radiation passes through the top layer to expose the photoresist layer.
Inventor(s): Wei-Chun Yen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chi Yang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Kang Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Chieh Chien of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jui Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Heng-Hsin Liu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, H05G2/00
CPC Code(s): G03F7/70033
Abstract: in an embodiment, a method includes: heating a byproduct transport ring of an extreme ultraviolet source, the byproduct transport ring disposed beneath vanes of the extreme ultraviolet source; after heating the byproduct transport ring for a first duration, heating the vanes; after heating the vanes, cooling the vanes; and after cooling the vanes for a second duration, cooling the byproduct transport ring.
Inventor(s): Shih-Jui HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., ShinAn KU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Hao HSU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chang LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, G03F1/66, G03F1/82
CPC Code(s): G03F7/70608
Abstract: a method of inspecting an outer surface of a mask pod includes moving a stage holding a mask pod such that the stage stops at each location of a plurality of locations under an outer surface of the mask pod for a predefined amount of time. at each location of the plurality of locations, the method further includes directing a stream of air to the outer surface of the mask pod, capturing an image of scattered air from each location of the plurality of locations of the outer surface of the mask pod, and determining a number of particles in the scattered air as a sampled number of particles based on the captured image. the method also includes generating a map of particles on the outer surface of the mask pod based on the sampled number of particles at each of the plurality of locations.
Inventor(s): Ming-Hsun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang HO of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hung LIAO of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Teng Kuei CHUANG of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Jhun Hua CHEN of Changhua (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00
CPC Code(s): G03F7/7085
Abstract: a method is described. the method includes obtaining a relationship between a thickness of a contamination layer formed on a mask and an amount of compensation energy to remove the contamination layer, obtaining a first thickness of a first contamination layer formed on the mask from a thickness measuring device, and applying first compensation energy calculated from the relationship to a light directed to the mask.
Inventor(s): Fong-Yuan CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui Yu LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hao CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tian-Jian WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tien-Chien HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Manjo Kumar ENUGULA of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Lin WEI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jyun-Hao CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/31, G06F30/323, G06F30/327
CPC Code(s): G06F30/31
Abstract: a method includes tagging source pdk devices (spds) in a source-circuit design (scd); generating a source design simulation database (sdsd) based on source design key performance indicator (kpi) simulation data of the spds in the scd; generating a target process design kit (pdk) simulation database (tpsd) based on target design kpi simulation data of a plurality of target-pdk devices (tpds); creating a matching table based on the sdsd and the tpsd; matching, based on the matching table, one or more tpds from the tpsd with each spd in the sdsd based on spd kpis; ranking the one or more tpds matched from the tpsd with each spd in the sdsd based on the spd kpis; and exchanging, based on a migration mapping table that includes a one-to-one relationship for tpds to the spds in the scd, one or more spds in the scd with one-to-one relational tpds.
Inventor(s): Pin-Dai SUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiang HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fong-Yuan CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yu LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hsiung CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Chou LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lee-Chung LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Hung LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Chun TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Kan CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F30/373, G06F30/394, G06F111/20
CPC Code(s): G06F30/392
Abstract: a method includes forming a transistor layer; forming a first metallization layer, including: forming first conductors, aligned along alpha tracks, and representing input pins of a cell region including first and second input pins; and cutting lengths of the first and second input pins to accommodate at most two access points, each aligned to a different one of first to fourth beta tracks, the beta tracks to which are aligned the access points of the first input pin being different than the beta tracks to which are aligned the access points of the second input pin; and forming a second metallization layer, including: forming second conductors representing routing segments and a representing a power grid segment aligned with one of the beta tracks of access points of the first input pin or the access points of the second input pin.
Inventor(s): Jung-Chan YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Wei CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jerry Chang-Jui KAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lee-Chung LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Chun TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Hung SHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Chih HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yu LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/394, H01L23/522, H01L23/528, H01L27/02, H01L27/118
CPC Code(s): G06F30/394
Abstract: an integrated circuit includes a first power rail extending in a first direction, and configured to supply a first supply voltage, and a first region next to the first power rail. the first region includes a first conductive structure extending in the first direction, a first set of conductive structures extending in a second direction, and a first set of vias between the first set of conductive structures and the first conductive structure. the first set of conductive structures overlaps the first conductive structure and the first power rail, and is located on a second level. each conductive structure of the first set of conductive structures is separated from each other in the first direction. each via of the first set of vias is located where the first set of conductive structures overlaps the first conductive structure and couples the first set of conductive structures to the first conductive structure.
Inventor(s): Elia Ambrosi of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Hsien Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hengyuan Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Xinyu Bao of Fremont CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C13/00, H10B63/00, H10N70/00, H10N70/20
CPC Code(s): G11C13/003
Abstract: a method includes applying a first voltage pulse across a memory cell, wherein the memory cell includes a selector, wherein the first voltage pulse switches the selector into an on-state; after applying the first voltage pulse, applying a second voltage pulse across the memory cell, wherein before applying the second voltage pulse the selector has a first voltage threshold, wherein after applying the second voltage pulse the selector has a second voltage threshold that is less than the first voltage threshold; and after applying the second voltage pulse, applying a third voltage pulse across the memory cell, wherein the third voltage pulse switches the selector into an on-state; wherein the selector remains continuously in an off-state between the first voltage pulse and the third voltage pulse.
Inventor(s): Perng-Fei Yuh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yih Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ku-Feng Lin of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Che Tsai of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Hiroki Noguchi of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fu-An Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C14/00, G11C11/16, G11C11/419
CPC Code(s): G11C14/0081
Abstract: disclosed herein is an integrated circuit including multiple magnetic tunneling junction (mtj) cells coupled to a static random access memory (sram). in one aspect, the integrated circuit includes a sram having a first port and a second port, and a set of pass transistors coupled to the first port of the sram. in one aspect, the integrated circuit includes a set of mtj cells, where each of the set of mtj cells is coupled between a select line and a corresponding one of the set of pass transistors.
Inventor(s): An-Ren ZI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yuansun Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, C11D1/02, C11D1/66, C11D1/72, C11D3/43, G03F7/16, G03F7/20, G03F7/30, G03F7/42, H01L21/027, H01L21/308
CPC Code(s): H01L21/02057
Abstract: a cleaning solution includes a solvent having hansen solubility parameters: 25>�>13, 25>�>3, 30>�>4; an acid having an acid dissociation constant pka: −11<pka<4, or a base having pka of 40>pka>9.5; and a surfactant. the surfactant is an ionic or non-ionic surfactant, selected from
Inventor(s): An-Ren ZI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yuansun Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, C11D1/02, C11D1/66, C11D1/72, C11D3/43, G03F7/16, G03F7/20, G03F7/30, G03F7/42, H01L21/027, H01L21/308
CPC Code(s): H01L21/02057
Abstract:
Inventor(s): An-Ren ZI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yuansun Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, C11D1/02, C11D1/66, C11D1/72, C11D3/43, G03F7/16, G03F7/20, G03F7/30, G03F7/42, H01L21/027, H01L21/308
CPC Code(s): H01L21/02057
Abstract: r is substituted or unsubstituted aliphatic, alicyclic, or aromatic group, and non-ionic surfactant has a-x or a-x-a-x structure, where a is unsubstituted or substituted with oxygen or halogen, branched or unbranched, cyclic or non-cyclic, saturated c2-c100 aliphatic or aromatic group, x includes polar functional groups selected from —oh, ═o, —s—, —p—, —p(o), —c(═o)sh, —c(═o)oh, —c(═o)or—, —o—, —n—, —c(═o)nh, —sooh, —sosh, —soh, —so—, —co—, —cn—, —so—, —con—, —nh—, —sonh—, and sonh.
Inventor(s): Marcus Johannes Henricus van Dal of Linden (BE) for taiwan semiconductor manufacturing company, ltd., Peter Ramvall of Lund (SE) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01L27/12, H01L29/417, H01L29/786
CPC Code(s): H01L21/02181
Abstract: structures and methods of forming the same are provided. a structure according to the present disclosure includes an interconnect structure, an aluminum oxide layer over the interconnect structure, and a transistor formed over the aluminum oxide layer. the transistor includes cuprous oxide.
Inventor(s): Yi-Chen HO of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., You-Hua CHOU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Hao LIAO of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Lun CHANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Zhen-Cheng WU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01L21/311, H01L21/768, H01L23/532
CPC Code(s): H01L21/02203
Abstract: the present disclosure provides a method. in some embodiments, the method includes forming a first porogen over a dielectric film; depositing a first dielectric monolayer over the first porogen and in contact with the dielectric film; removing the first porogen. in some embodiments, the method includes forming a first porogen over a substrate; forming a first dielectric film over the first porogen; after forming the first dielectric film, performing an uv treatment on the first porogen.
Inventor(s): An-Ren ZI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yilang County (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hsiang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/027, H01L21/67
CPC Code(s): H01L21/0274
Abstract: a method of manufacturing a semiconductor device includes forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. a metal-containing photoresist layer is formed over the first main surface of the semiconductor substrate. the first protective layer is removed, and the metal-containing photoresist layer is selectively exposed to actinic radiation. a second protective layer is formed over the edge portion of the first main surface of the semiconductor substrate. the selectively exposed photoresist layer is developed to form a patterned photoresist layer, and the second protective layer is removed.
Inventor(s): Chih-Min HSIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Wen LAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-chun HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Sung YEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Ming LAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Gun LIU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/033, H10B10/00
CPC Code(s): H01L21/0337
Abstract: a method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. a plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. the first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. a spacer layer is formed on the first layer and the first portions. a second plurality of openings is formed within the spacer layer to expose second portions of the second layer. the spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.
Inventor(s): Yu Shih Wang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-I Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shian Wei Mao of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ken-Yu Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsing Tsai of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Jung Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/3213, H01L23/485, H01L23/532
CPC Code(s): H01L21/76847
Abstract: generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. in an embodiment, a barrier layer is formed along a sidewall. a portion of the barrier layer along the sidewall is etched back. after etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. a conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.
Inventor(s): Yu-Chan Yen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Feng Fu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Ying Lee of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/8234, H01L23/485, H01L23/522, H01L23/532, H01L29/165, H01L29/66
CPC Code(s): H01L21/76897
Abstract: an integrated circuit structure includes a first inter-layer dielectric (ild), a gate stack in the first ild, a second ild over the first ild, a contact plug in the second ild, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. the contact plug and the dielectric protection layer are in the second ild. a dielectric capping layer is over and in contact with the contact plug.
Inventor(s): Wei-Barn CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Huang KUO of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shiu-Ko JANGJIAN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Cherng JENG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Yao LO of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/265, H01L21/308, H01L27/088, H01L29/08, H01L29/66
CPC Code(s): H01L21/823412
Abstract: a device includes a finfet on a first region of a substrate and a planar-fet on a second region of the substrate. the finfet includes a finfet source region, a finfet drain region, and a finfet gate between the finfet source region and the finfet drain region. the planar-fet includes a planar-fet source region, a planar-fet drain region, and a planar-fet gate between the planar-fet source region and the planar-fet drain region. a bottommost position of the finfet source region is lower than a bottommost position of the planar-fet source region.
Inventor(s): Hsin-Yi Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ji-Cheng Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lung Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Weng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, C23C16/34, C23C16/455, H01L21/28, H01L21/285, H01L21/764, H01L27/088, H01L29/06, H01L29/08, H01L29/417, H01L29/45, H01L29/49, H01L29/66
CPC Code(s): H01L21/82345
Abstract: a method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. after the recessing, a portion of a semiconductor material between the isolation region protrudes higher than top surfaces of the isolation regions to form a semiconductor fin. the method further includes forming a gate stack, which includes forming a gate dielectric on sidewalls and a top surface of the semiconductor fin, and depositing a titanium nitride layer over the gate dielectric as a work-function layer. the titanium nitride layer is deposited at a temperature in a range between about 300� c. and about 400� c. a source region and a drain region are formed on opposing sides of the gate stack.
Inventor(s): Kuan-Ting Pan of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ruei JHAN of Keelung (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shi Ning JU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L21/823468
Abstract: embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. the sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. the fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.
Inventor(s): Shahaji B. More of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/78
CPC Code(s): H01L21/823814
Abstract: an embodiment device includes: first fins protruding from an isolation region; second fins protruding from the isolation region; a first fin spacer on a first sidewall of one of the first fins, the first fin spacer disposed on the isolation region, the first fin spacer having a first spacer height; a second fin spacer on a second sidewall of one of the second fins, the second fin spacer disposed on the isolation region, the second fin spacer having a second spacer height, the first spacer height greater than the second spacer height; a first epitaxial source/drain region on the first fin spacer and in the first fins, the first epitaxial source/drain region having a first width; and a second epitaxial source/drain region on the second fin spacer and in the second fins, the second epitaxial source/drain region having a second width, the first width greater than the second width.
Inventor(s): Shih-Cheng Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hsiung Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L27/092, H01L29/161
CPC Code(s): H01L21/823814
Abstract: a semiconductor device includes a first epitaxial feature disposed in a first device region of the semiconductor device, a second epitaxial feature disposed in a second device region of the semiconductor device, a first silicide layer disposed on the first epitaxial feature, a second silicide layer disposed on the second epitaxial feature, a metal layer disposed on the first silicide layer, a first contact plug landing on the metal layer, and a second contact plug landing on the second silicide layer. the metal layer and the second silicide layer each include a first metal element. the first silicide layer includes a second metal element different from the first metal element.
Inventor(s): Cheng-Hao Hou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Che-Hao Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Da-Yuan Lee of Jhubei (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/28, H01L27/092
CPC Code(s): H01L21/823857
Abstract: a method includes depositing a first high-k dielectric layer over a first semiconductor region, performing a first annealing process on the first high-k dielectric layer, depositing a second high-k dielectric layer over the first high-k dielectric layer; and performing a second annealing process on the first high-k dielectric layer and the second high-k dielectric layer.
Inventor(s): Chih-Wei CHOU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Hsin CHI of Longjing Township (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Yuan LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yin-Tun CHOU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Chih WANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chi LIU of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, H01L21/02, H01L21/67
CPC Code(s): H01L22/14
Abstract: a deposition tool includes a power cable pedestal including a pedestal body with a first surface and a second surface and a guide hole that extends through the pedestal body from the first surface to the second surface, where at least a portion of a sidewall of the guide hole has a slanted surface, and where the pedestal body is formed from a first material with a melting point that is higher than a melting point of polyoxymethylene (pom). the deposition tool includes a bushing arranged over the guide hole, where the bushing is formed from a second material with a melting point that is higher than the melting point of pom.
Inventor(s): Po-Chen LAI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Chih YEW of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Ling LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hua WANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao LIN of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Po-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L23/00, H01L23/498, H01L25/065
CPC Code(s): H01L23/3178
Abstract: a package structure is provided. the package structure includes a package component over a redistribution structure, a substrate under the redistribution structure, and an underfill material over the redistribution structure and including a first extending portion in the structure. the package component has a first sidewall and a second sidewall connected to the first sidewall at a first corner. in a plan view, the first extending portion has a first sidewall passing through the first sidewall of the package component and a second sidewall opposite to the first sidewall of the first extending portion and passing through the second sidewall of the package component.
Inventor(s): Kuo Lung Pan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Rong Chun of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Teng-Yuan Lo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Yi Kuo of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Horng Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tin-Hao Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/48, H01L21/56, H01L21/768, H01L23/00, H01L23/29, H01L23/31, H01L23/498, H01L25/065
CPC Code(s): H01L23/5226
Abstract: in an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.
Inventor(s): Chia-Chung Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Sheng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Sheng Yuan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Kan Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/525, G11C17/16, H01L23/522, H01L23/528, H10B20/25
CPC Code(s): H01L23/5256
Abstract: a semiconductor structure includes a substrate having a first surface and a second surface opposite the first surface. the semiconductor structure includes a semiconductor device disposed on the first surface. the semiconductor structure includes a metallization layer disposed on the second surface. the semiconductor structure includes a first conductive via and a second conductive via coupled in parallel to the metallization layer, the first conductive via and the second conductive via extending from the second side toward the first side. the semiconductor structure further includes an electrical fuse disposed over the semiconductor device and coupled to the first and second conductive vias.
Inventor(s): Chung-Hao Tsai of Huatan Township (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Chia Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Chiang Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chuei-Tang Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L23/14, H01L23/31, H01L23/48, H01L23/498, H01L23/522, H01L23/525, H01L23/66, H01L25/065, H01L25/07
CPC Code(s): H01L24/04
Abstract: an embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.
Inventor(s): Yen-Kun Lai of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hao Hsu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Hsiang Tu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chin Chang of Chiayi City (TW) for taiwan semiconductor manufacturing company, ltd., Mirng-ji Lii of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/522
CPC Code(s): H01L24/13
Abstract: a semiconductor die includes a semiconductor substrate, an interconnect structure, and a conductive bump. the interconnect structure is disposed on and electrically connected to the semiconductor substrate. the interconnect structure includes stacked interconnect layers. each of the stacked interconnect layers includes a dielectric layer and an interconnect wiring embedded in the dielectric layer. the interconnect wiring of a first interconnect layer among the stacked interconnect layers further includes a first via and second vias. the first via electrically connected to the interconnect wiring. the second vias connected to the interconnect wiring, and the first via and the second vias are located on a same level height. the conductive bump is disposed on the interconnect structure. the conductive bump includes a base portion and a protruding portion connected to the base portion, and the base portion is between the protruding portion and the first via.
Inventor(s): Cheng-Hung CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Nu HSU of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Chen LIU of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Heng-Chi HUANG of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chen LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Yen CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Nan HSIEH of Chubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chio LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Shien CHEN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Yu KU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Te-Hsun PANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Feng WU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Sen-Chi CHIANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/498
CPC Code(s): H01L24/13
Abstract: package structures and methods for manufacturing the same are provided. the package structure includes a first substrate and through vias formed through the first substrate. the package further includes redistribution layers formed over the first substrate and connected to the through vias and a first pillar layer formed over the redistribution layers. the package further includes a first barrier layer formed over the first pillar layer and a first cap layer formed over the first barrier layer. the package further includes an underfill layer formed over the redistribution layers and surrounding the first pillar layer, the first barrier layer, and the first cap layer. in addition, the first barrier layer has a first protruding portion laterally extending outside a first sidewall surface of the first pillar layer and a second sidewall surface of the first cap layer.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Wen Shih of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Min-Chien Hsiao of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Nien-Fang Wu of Chiayi City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzuan-Horng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/304, H01L21/78, H01L23/00, H01L23/31, H01L23/48
CPC Code(s): H01L25/0657
Abstract: a die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. the first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. the first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. the second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. the insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die. the redistribution circuit structure is electrically connected with the first and second semiconductor dies, and the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure.
Inventor(s): Chih-Hsuan Tai of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chih Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hung Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Ting Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ban-Li Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Cheng Tseng of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hui Lai of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/10, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/498, H01L25/00
CPC Code(s): H01L25/105
Abstract: a package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. the first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. the dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. the first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. the semiconductor die is disposed on the second surface of the dielectric layer. the through insulator vias are connected to the conductive layer. the insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. the second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
Inventor(s): Shang-Yun Hou of Jubei (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Hui Huang of Dongshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Yu Huang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Pin Hu of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Yushun Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Heh-Chang Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Kuo Hsia of Jhubei (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chieh Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ching Shih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Fu Kao of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsin Wei of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Chung Kuo of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hsi Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/00, H01L21/48, H01L23/00, H01L23/24, H01L23/31, H01L23/498, H01L25/065, H01L25/18
CPC Code(s): H01L25/50
Abstract: an integrated circuit package and a method of forming the same are provided. the method includes attaching an integrated circuit die to a first substrate. a dummy die is formed. the dummy die is attached to the first substrate adjacent the integrated circuit die. an encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. the encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. an interior portion of the dummy die is removed. a remaining portion of the dummy die forms an annular structure.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon-Jhy Liaw of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234
CPC Code(s): H01L27/088
Abstract: semiconductor structures and methods for manufacturing the same are provided. the semiconductor structure includes first nanostructures formed over a substrate along a first direction, and a first gate structure formed over the first nanostructures along a second direction. the semiconductor structure includes a gate spacer layer formed adjacent to the first gate structure, and a first number of the nanostructures directly below the gate spacer layer is greater than a second number of the nanostructures directly below the first gate structure.
Inventor(s): Hong-Chih CHEN of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Sheng LIANG of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Hsiang SU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/768, H01L21/8234, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a method for forming a semiconductor structure is provided. the method includes forming an active region including a lower fin element and first semiconductor layers and second semiconductor layers alternately stacked over the lower fin element, forming a fin spacer layer along a sidewall of the active region, forming a dielectric wall over the fin spacer layer, forming a dummy gate structure over the active region, the fin spacer layer and the dielectric wall, and etching the active region, the fin spacer layer, and the first dielectric wall to form a first recess. the method also includes laterally recessing, from the first recess, the first semiconductor layers of the active region and the fin spacer layer to form a notch, forming an inner spacer layer in the notch, and forming a source/drain feature on the lower fin element of the active region.
Inventor(s): Hsu Ming HSIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shen WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kung-Shu HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hong Pin LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shiang-Bau WANG of Pingzchen City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Fu CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/40, H01L21/3105, H01L21/311, H01L21/66, H01L29/66
CPC Code(s): H01L29/401
Abstract: in a method of manufacturing a semiconductor device, a sacrificial gate structure including sacrificial gate electrode is formed over a substrate. a first dielectric layer is formed over the sacrificial gate structure. a second dielectric layer is formed over the first dielectric layer. the second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed. a third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. a fourth dielectric layer is formed over the third dielectric layer. the fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. the recessing the first dielectric layer comprises a first etching operation and a second etching operation using a different etching as from the first etching operation.
Inventor(s): Wei-Yip Loh of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hong-Mao Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Harry Chien of Chandler AZ (US) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Chang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/49, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L29/41733
Abstract: semiconductor structures and methods of forming the same are provided. a method of the present disclosure includes receiving a workpiece that includes a bottom source/drain feature over a substrate, a first dielectric layer over the bottom source/drain feature, a top source/drain feature over the first dielectric layer, and a second dielectric layer over the top source/drain feature, forming a frontside opening through the second dielectric layer to expose a portion of the top source/drain feature, selectively depositing a first silicide layer on the exposed portion of the top source/drain feature, forming a top metal fill layer over the first silicide layer to fill the frontside opening, forming a backside opening through the substrate to expose a portion of the bottom source/drain feature, selectively depositing a second silicide layer on the exposed portion of the bottom source/drain feature, and forming a bottom metal fill layer on the second silicide layer.
Inventor(s): Hsin Hsiang Tseng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Nung CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8238, H01L27/092, H01L29/06, H01L29/417, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a semiconductor device and a method of fabricating the semiconductor device are disclosed. the method includes forming a fin base on a substrate, epitaxially growing a s/d region on the fin base, depositing a dielectric layer on the s/d region, forming a contact structure on the s/d region through the dielectric layer, removing a portion of the dielectric layer to expose sidewalls of the contact structure, forming a barrier layer on the dielectric layer and to cover the exposed sidewalls of the contact structure, and forming a via structure on the contact structure through the barrier layer. the formation of the barrier layer includes depositing an insulating layer with a dielectric constant and a material density higher than a dielectric constant and a material density of the dielectric layer.
Inventor(s): Chen-Huang Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Jhe Sie of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Yih-Ann Lin of Jhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., An Chyi Wei of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ryan Chia-Jen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/49, H01L21/285, H01L21/764, H01L29/45, H01L29/66, H01L29/78
CPC Code(s): H01L29/4991
Abstract: a method includes forming an opening in a first dielectric layer. a region underlying the first dielectric layer is exposed to the opening. the method further includes depositing a dummy silicon layer extending into the opening, and depositing an isolation layer. the isolation layer and the dummy layer include a dummy silicon ring and an isolation ring, respectively, in the opening. the opening is filled with a metallic region, and the metal region is encircled by the isolation ring. the dummy silicon layer is etched to form an air spacer. a second dielectric layer is formed to seal the air spacer.
Inventor(s): Chun-Han Chen of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Ming Lee of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Kai Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Yun Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/51, H01L21/02, H01L21/3105, H01L29/40, H01L29/78
CPC Code(s): H01L29/511
Abstract: a semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.
Inventor(s): Wen-Kai Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Cheng Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Che-Hao Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/311, H01L21/8234, H01L29/06, H01L29/423, H01L29/49, H01L29/786
CPC Code(s): H01L29/66553
Abstract: a method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.
Inventor(s): Shen-Yang LEE of Miaoli (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Fu Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Pi Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L29/06, H01L29/08, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L29/6656
Abstract: a semiconductor device and a method of fabricating the semiconductor device are disclosed. the method includes forming a fin base on a substrate, forming a superlattice structure including first and second nanostructured layers on the fin base, forming a polysilicon structure on the superlattice structure, epitaxially growing a s/d region on the fin base and adjacent to the first nanostructured layer, forming an oxygen-rich outer gate spacer including a first dielectric material with a first non-stoichiometric composition on a sidewall of the polysilicon structure, forming an oxygen-rich inner gate spacer including a second dielectric material with a second non-stoichiometric composition on a sidewall of the second nanostructured layer, and replacing the polysilicon structure with a gate structure.
Inventor(s): I-Ming Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Sheng Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Pi Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ruei Jhan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin Chao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/775, H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/66
CPC Code(s): H01L29/775
Abstract: a method for fabricating semiconductor devices includes forming a stack structure protruding from a substrate and including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked on top of one another. the method includes forming an isolation structure overlaying the substrate and a lower portion of the stack structure. the method includes implanting dopants into at least an upper portion of the isolation structure.
Inventor(s): Ming-Yen Chuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Katherine H. CHIANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/8234, H01L29/423, H01L29/786
CPC Code(s): H01L29/7827
Abstract: a semiconductor die includes semiconductor substrate and interconnection structure. interconnection structure includes first conductive lines, first conductive patterns, first pillar stacks, second pillar stacks, gate patterns. first conductive lines extend parallel to each other in first direction and are embedded in interlayer dielectric layer. first conductive patterns are disposed in row along first direction and are embedded in interlayer dielectric layer beside first conductive lines. first pillar stacks include first pairs of metallic blocks separated by first dielectric material blocks. second pillar stacks include second pairs of metallic blocks separated by second dielectric material blocks. each second pillar stack is electrically connected to respective first conductive pattern. gate patterns extend substantially perpendicular to first conductive lines. each gate pattern directly contacts one respective second pillar stack and extends over a group of first pillar stacks.
Inventor(s): Kun-Mu LI of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Tsz-Mei KWOK of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hua YU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chan-Lon YANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L21/3115, H01L21/84, H01L27/12, H01L29/06, H01L29/165, H01L29/66
CPC Code(s): H01L29/7848
Abstract: a fin field effect transistor (fin fet) device includes fin structure extending in first direction and protruding from isolation insulating layer disposed over substrate. the fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. the fin fet device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. the fin fet device includes a source and a drain. each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. the stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. the fin fet device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.
Inventor(s): Yan-Ting SHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Chi YU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Teng LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Li LIN of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chih Hsuan CHENG of Houlong Township (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Chan WENG of Kaoshiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/8234, H01L29/06, H01L29/417, H01L29/66
CPC Code(s): H01L29/785
Abstract: a semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. the gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.
Inventor(s): Wen-Hsien TU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Fan LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L21/768, H01L29/66
CPC Code(s): H01L29/785
Abstract: a method of manufacturing a semiconductor device includes forming a fin structure protruding from a first isolation insulating layer disposed over a substrate, and forming a dummy gate structure over an upper portion of the fin structure. the method further includes forming a second isolation insulating layer over the first isolation insulating layer and forming gate sidewall spacers on opposing side faces of the dummy gate structure. the method also includes after the gate sidewall spacers are formed, forming a trench by etching a source/drain region of the fin structure and forming a base semiconductor epitaxial layer in the trench. the method further includes forming a cap semiconductor epitaxial layer on the base semiconductor epitaxial layer , removing the dummy gate structure to expose the fin structure, and forming a gate dielectric layer over a channel region of the fin structure.
Inventor(s): Po-Yao Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hao Tsai of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01Q1/22, H01L21/48, H01L21/56, H01L21/683, H01L21/82, H01L23/00, H01L23/31, H01L23/498, H01L23/538, H01L23/66, H01L25/065, H01Q9/04, H01Q19/10
CPC Code(s): H01Q1/2283
Abstract: a method includes bonding an antenna substrate to a redistribution structure. the antenna substrate has a first part of a first antenna, and the redistribution structure has a second part of the first antenna. the method further includes encapsulating the antenna substrate in an encapsulant, and bonding a package component to the redistribution structure. the redistribution structure includes a third part of a second antenna, and the package component includes a fourth part of the second antenna.
Inventor(s): Chun-Lin Louis Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Henry Tong Yee Shian of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Alan Tu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Han-Lung Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzung-Chi Fu of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Tsun Liu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jui Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chung Cheng of Chiayi County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01S3/104, H01S3/00, H01S3/04, H01S3/041, H01S3/10, H01S3/1123, H01S3/223, H01S3/23, H05G2/00
CPC Code(s): H01S3/104
Abstract: the present disclosure provides a method for aligning a master oscillator power amplifier (mopa) system. the method includes ramping up a pumping power input into a laser amplifier chain of the mopa system until the pumping power input reaches an operational pumping power input level; adjusting a seed laser power output of a seed laser of the mopa system until the seed laser power output is at a first level below an operational seed laser power output level; and performing a first optical alignment process to the mopa system while the pumping power input is at the operational pumping power input level, the seed laser power output is at the first level, and the mopa system reaches a steady operational thermal state.
Inventor(s): Tao Yi HUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wun-Jie LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jam-Wen LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ji CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H02H9/04, H02H1/00
CPC Code(s): H02H9/046
Abstract: an esd clamp circuit has an esd detection circuit connected between a first terminal and a second terminal, with a first output node and a second output node. the esd detection circuit is configured to output respective first and second control signals at the first and second output nodes in response to an esd event. a discharge circuit includes a p-type transistor having a source, a drain and a gate, with the gate connected to the first output node. an n-type transistor has a source, a drain and a gate, with the gate connected to the second output node. the drain is connected to the drain of the p-type transistor. the discharge circuit is configured to establish a first esd discharge path from the first terminal, through the p-type transistor and the n-type transistor, to the second terminal, and to further establish a second esd discharge path in parallel with the first esd discharge path. the second esd discharge path includes a parasitic silicon controlled rectifier (scr).
Inventor(s): Po-Chia LAI of Fremont CA (US) for taiwan semiconductor manufacturing company, ltd., Meng-Hung SHEN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Lin LIU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Stefan RUSU of Sunnyvale CA (US) for taiwan semiconductor manufacturing company, ltd., Yan-Hao CHEN of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Jerry Chang-Jui KAO of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K3/012, H03K3/0233, H03K3/037, H03K3/289, H03K3/356, H03K3/3562
CPC Code(s): H03K3/012
Abstract: a flip-flop circuit configured to latch an input signal to an output signal is disclosed. the circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. in some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.
Inventor(s): Yi Yang of Fremont CA (US) for taiwan semiconductor manufacturing company, ltd., Dongna Shen of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Yu-Jen Wang of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/01, G11C11/16, H01F10/32, H01F41/34, H10N50/10, H10N50/80
CPC Code(s): H10N50/01
Abstract: a magnetic tunneling junction (mtj) structure comprises a pinned layer on a bottom electrode. a barrier layer on the pinned layer, wherein a second metal re-deposition layer is on sidewalls of the barrier layer and the pinned layer, a free layer on the barrier layer wherein the free layer has a first width smaller than a second width of the pinned layer, a top electrode on the free layer having a same first width as the free layer wherein a first metal re-deposition layer is on sidewalls of the free layer and top electrode, and dielectric spacers on sidewalls of the free layer and top electrode covering the first metal re-deposition layer wherein the free layer and the top electrode together with the dielectric spacers have a same the second width as the pinned layer wherein the dielectric spacers prevent shorting between the first and second metal re-deposition layers.
Inventor(s): Sheng-Siang Ruan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wen Zhong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Yu Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Wen Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching Ju Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin I Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/00, H10N70/20
CPC Code(s): H10N70/8416
Abstract: a semiconductor device that includes a semiconductor substrate, a bottom electrode over the semiconductor substrate, a switching layer over the bottom electrode, a metal ion source layer over the switching layer, and a top electrode over the metal ion source layer. the switching layer includes a compound having aluminum, oxygen, and nitrogen.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on September 5th, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- B29C45/14
- B29C45/00
- B29C45/03
- H01L21/56
- CPC B29C45/14655
- Taiwan semiconductor manufacturing company, ltd.
- B62B5/00
- B62B3/00
- B62B3/04
- B62B3/10
- CPC B62B5/0006
- G01R31/3177
- G01R31/317
- G01R31/3185
- H03K19/173
- CPC G01R31/3177
- G03F7/00
- G03F7/16
- G03F7/32
- CPC G03F7/0025
- G03F7/11
- G03F7/20
- G03F7/38
- CPC G03F7/11
- H05G2/00
- CPC G03F7/70033
- G03F1/66
- G03F1/82
- CPC G03F7/70608
- CPC G03F7/7085
- G06F30/31
- G06F30/323
- G06F30/327
- CPC G06F30/31
- G06F30/392
- G06F30/373
- G06F30/394
- G06F111/20
- CPC G06F30/392
- H01L23/522
- H01L23/528
- H01L27/02
- H01L27/118
- CPC G06F30/394
- G11C13/00
- H10B63/00
- H10N70/00
- H10N70/20
- CPC G11C13/003
- G11C14/00
- G11C11/16
- G11C11/419
- CPC G11C14/0081
- H01L21/02
- C11D1/02
- C11D1/66
- C11D1/72
- C11D3/43
- G03F7/30
- G03F7/42
- H01L21/027
- H01L21/308
- CPC H01L21/02057
- H01L27/12
- H01L29/417
- H01L29/786
- CPC H01L21/02181
- H01L21/311
- H01L21/768
- H01L23/532
- CPC H01L21/02203
- H01L21/67
- CPC H01L21/0274
- H01L21/033
- H10B10/00
- CPC H01L21/0337
- H01L21/3213
- H01L23/485
- CPC H01L21/76847
- H01L21/8234
- H01L29/165
- H01L29/66
- CPC H01L21/76897
- H01L21/265
- H01L27/088
- H01L29/08
- CPC H01L21/823412
- C23C16/34
- C23C16/455
- H01L21/28
- H01L21/285
- H01L21/764
- H01L29/06
- H01L29/45
- H01L29/49
- CPC H01L21/82345
- H01L29/423
- CPC H01L21/823468
- H01L21/8238
- H01L27/092
- H01L29/78
- CPC H01L21/823814
- H01L29/161
- CPC H01L21/823857
- H01L21/66
- CPC H01L22/14
- H01L23/31
- H01L23/00
- H01L23/498
- H01L25/065
- CPC H01L23/3178
- H01L21/48
- H01L23/29
- CPC H01L23/5226
- H01L23/525
- G11C17/16
- H10B20/25
- CPC H01L23/5256
- H01L23/14
- H01L23/48
- H01L23/66
- H01L25/07
- CPC H01L24/04
- CPC H01L24/13
- H01L21/304
- H01L21/78
- CPC H01L25/0657
- H01L25/10
- H01L25/00
- CPC H01L25/105
- H01L23/24
- H01L25/18
- CPC H01L25/50
- CPC H01L27/088
- H01L29/775
- CPC H01L29/0673
- H01L29/40
- H01L21/3105
- CPC H01L29/401
- CPC H01L29/41733
- CPC H01L29/42392
- CPC H01L29/4991
- H01L29/51
- CPC H01L29/511
- CPC H01L29/66553
- CPC H01L29/6656
- CPC H01L29/775
- CPC H01L29/7827
- H01L21/3115
- H01L21/84
- CPC H01L29/7848
- CPC H01L29/785
- H01Q1/22
- H01L21/683
- H01L21/82
- H01L23/538
- H01Q9/04
- H01Q19/10
- CPC H01Q1/2283
- H01S3/104
- H01S3/00
- H01S3/04
- H01S3/041
- H01S3/10
- H01S3/1123
- H01S3/223
- H01S3/23
- CPC H01S3/104
- H02H9/04
- H02H1/00
- CPC H02H9/046
- H03K3/012
- H03K3/0233
- H03K3/037
- H03K3/289
- H03K3/356
- H03K3/3562
- CPC H03K3/012
- H10N50/01
- H01F10/32
- H01F41/34
- H10N50/10
- H10N50/80
- CPC H10N50/01
- CPC H10N70/8416
