Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on September 12th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on September 12th, 2024
Taiwan Semiconductor Manufacturing Company, Ltd.: 60 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L29/66 (12), H01L29/06 (11), H01L21/768 (9), H01L29/78 (9), H01L29/423 (9) H01L23/5226 (3), H10B10/18 (2), H01L29/41775 (2), H10B10/125 (2), G06F30/392 (2)
With keywords such as: layer, structure, semiconductor, gate, substrate, dielectric, conductive, surface, region, and direction in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Wen-Yi LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hao CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chuan-Hsiang SUN of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Mill-Jer WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chen LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Shien CHEN of Zhubei City, Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01R1/067, G01R31/28
CPC Code(s): G01R1/06761
Abstract: a probe head structure is provided. the probe head structure includes a flexible substrate having a top surface and a bottom surface. the probe head structure includes a first probe pillar passing through the flexible substrate. the probe head structure includes a redistribution structure on the top surface of the flexible substrate and the first probe pillar. the probe head structure includes a wiring substrate over the redistribution structure. the probe head structure includes a first conductive bump connected between the wiring substrate and the redistribution structure.
Inventor(s): Tao-Cheng LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Hao HUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chi KUO of Yangmei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/136, G02B5/18, G02B6/122, H01L21/306, H01L21/308
CPC Code(s): G02B6/136
Abstract: a method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
20240302731. REFLECTIVE MASK_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Pei-Cheng HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Cheng LIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chang LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/24
CPC Code(s): G03F1/24
Abstract: a reflective mask includes a substrate, a reflective multilayer disposed over the substrate, a capping layer disposed over the reflective multilayer, an intermediate layer disposed over the capping layer, an absorber layer disposed over the intermediate layer, and a cover layer disposed over the absorber layer. the intermediate layer includes a material having a lower hydrogen diffusivity than a material of the capping layer.
Inventor(s): Chia-Tung KUO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Cheng HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chang LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hsiang LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/64
CPC Code(s): G03F1/64
Abstract: a pellicle for an extreme ultraviolet (euv) reflective mask includes a membrane attached to a frame. the membrane includes a plurality of nanotube bundles, each including a plurality of multi-wall nanotubes made of a first nanotube material and bonded together, and a plurality wrapping layers of a second nanotube material on the plurality of nanotube bundles, the second nanotube material being different from the first nanotube material. the pellicle advantageously has good euv light transmittance, increased strength under euv exposure environment, and thereby prolonged lifetime.
Inventor(s): Hidehiro FUJIWARA of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kao-Cheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen Lin CHUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei Min CHAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Huei CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0638
Abstract: a memory cell array includes a first bank of memory cells, a second bank of memory cells adjacent to the first bank of memory cells, a first set of bit lines and a second set of bit lines. the first set of bit lines extend in a first direction, is coupled to the first bank of memory cells, and is on at least a first metal layer above a front-side of a substrate. the second set of bit lines extend in the first direction, is coupled to the second bank of memory cells, and is on at least a second metal layer below a back-side of the substrate opposite from the front-side of the substrate.
Inventor(s): Wei-Cheng TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Wei PENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Guo-Huei WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lee-Chung LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chin HOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F30/373, G06F30/394
CPC Code(s): G06F30/392
Abstract: an ic structure includes first and second complementary field-effect transistors (cfets) positioned in a semiconductor wafer, each of the first and second cfets including a gate structure extending in a first direction, an n-type channel extending through the gate structure in a second direction perpendicular to the first direction, and a p-type channel extending through the gate structure in the second direction and aligned with the n-type channel in a third direction perpendicular to each of the first and second directions. a metal line extends in the first direction, is aligned with each of the first and second cfets in the third direction, and is configured to distribute a power supply or reference voltage to each of the first and second cfets. the metal line is a metal line closest to each of the first and second cfets along the third direction and extending in the first direction.
Inventor(s): Shin-Chi Chen of Shinchu (TW) for taiwan semiconductor manufacturing company, ltd., King-Ho Tam of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ze Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Yu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F30/31, G06F30/327, G06F119/18
CPC Code(s): G06F30/392
Abstract: a method in certain embodiments includes using a computer system that includes an eda tool to generate a layout of an ic device; searching, using a statistical method such as bayesian optimization process, for one or more input variable parameters, such as the dimensions of the ic device and the dimensions of the voltage areas in the ic device, that results in an optimal characteristic, such as power, performance or area (ppa) of the ic device, subject to a limiting condition, such as one determined using a cost function. a computer system including one or more edas configured to perform the method is also disclosed.
Inventor(s): Shih-Lien Linus LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/22, G11C7/10
CPC Code(s): G11C11/2255
Abstract: a system for processing a data array, such as transposing a matrix, includes a two-dimensional array of memory cells, such as fefets, each having an input end, an output end and a control end. the system also includes an input interface is adapted to supply signals indicative of a subset of the data array, such as a row of a matrix, and output control signals to the input ends of a selected column of the memory cells. the system further includes an output interface adapted to receive the data stored in the memory array from the output ends of a selected row of the memory cells. a method of processing a data array, such as transposing a matrix, include writing subsets of the data array to the memory array column-by-column, and reading from the memory cells, row-by-row.
Inventor(s): Ping-Wei Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Ming Chang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Lin Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/412, G11C11/419, H10B10/00
CPC Code(s): G11C11/412
Abstract: a memory cell includes first and second active regions extending lengthwise in a first direction, and first, second, third, and fourth gate structures arranged in order from first to fourth along the first direction. each of the first, second, third, and fourth gate structures extends lengthwise in a second direction that is perpendicular to the first direction. the first, second, third, and fourth gate structures are configured to engage the first and second active regions in forming first, second, third, fourth, fifth, and sixth transistors of a write-port of the memory cell. the memory cell also includes a fifth gate structure configured to engage the second active region in forming a seventh transistor of a read-port of the memory cell.
Inventor(s): Sheng-chun YANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wei LIANG of Luodong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Hung WAN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ming LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Liu Che KANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32651
Abstract: a radio frequency (rf) screen for a microwave powered ultraviolet (uv) lamp system is disclosed. in one example, a disclosed rf screen includes: a sheet comprising a conductive material; and a frame around edges of the sheet. the conductive material defines a predetermined mesh pattern of individual openings across substantially an operative area of the screen. each of the individual openings has a triangular shape.
Inventor(s): Te-Yang Lai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yen Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Cheras (MY) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/28, H01L21/3115, H01L21/8234, H01L27/088, H01L29/51
CPC Code(s): H01L21/28185
Abstract: a method includes forming an oxide layer on a semiconductor region, and depositing a first high-k dielectric layer over the oxide layer. the first high-k dielectric layer is formed of a first high-k dielectric material. the method further includes depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material, depositing a dipole film over and contacting a layer selected from the first high-k dielectric layer and the second high-k dielectric layer, performing an annealing process to drive-in a dipole dopant in the dipole film into the layer, removing the dipole film, and forming a gate electrode over the second high-k dielectric layer.
Inventor(s): Yu-Ping TSENG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ren-Hao JHENG of Hsinch County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/321, B24B9/06, B24B37/04, B24B37/24, B24B37/26
CPC Code(s): H01L21/3212
Abstract: the present disclosure provides an apparatus and a method for polishing a semiconductor substrate in semiconductor device manufacturing. the apparatus can include: a carrier configured to hold the substrate; a polishing pad configured to polish a first surface of the substrate; a chemical mechanical polishing (cmp) slurry delivery arm configured to dispense a cmp slurry onto the first surface of the substrate; and a pad conditioner configured to condition the polishing pad. in some embodiments, the pad conditioner can include: a conditioning disk configured to scratch the polishing pad; a conditioning arm configured to rotate the conditioning disk; a plurality of magnetic screws configured to secure the conditioning disk onto the conditioning arm and including a respective plurality of screw heads; and a plurality of blocking devices respectively positioned beneath the plurality of screw heads and configured to block debris particles from entering a respective plurality of screw holes.
Inventor(s): Tsung-Fu TSAI of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hsuan TSAI of Taitung City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Chieh TING of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Ting LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei LU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/56, H01L23/00, H01L23/48, H01L25/065
CPC Code(s): H01L21/563
Abstract: a method of fabricating a semiconductor device is provided. the method includes providing a die stacking unit that includes a plurality of dies stacked on each other, and a plurality of conductive joints connected between each two adjacent dies. the method includes providing a plurality of dummy micro bumps and dummy pads between the two adjacent dies and between the conductive joints. the dummy micro bumps and the dummy pads are connected to one of the two adjacent dies but not to the other, and the dummy micro bumps are formed on some of the dummy pads but not on all of the dummy pads. the method includes dispensing an underfill material into gaps between the plurality of dies, the conductive joints, the dummy micro bumps, and the dummy pads.
Inventor(s): Kai-Wen WU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Ta CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Shen HSIEH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yi HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, F27B17/00, F27D3/00, F27D5/00, H01L21/324
CPC Code(s): H01L21/67103
Abstract: in an embodiment, an apparatus comprising: a heater configured to heat a wafer located on a wafer staging area of the heater, the heater comprising a heater shaft extending below the wafer staging area; and a heater lift assembly comprising: a lift shaft configured to move the heater shaft in a vertical direction; a clamp that connects the heater shaft to the lift shaft; and a damper disposed on top of the clamp.
Inventor(s): Jen-Chun Liao of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao-Chung Liang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Jui Huang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, H01L21/683
CPC Code(s): H01L21/67132
Abstract: a pickup apparatus for separating a semiconductor package from an adhesive film includes a platform, a roller, a moving mechanism, and a collector element. the platform has a surface disposed with the adhesive film, where the adhesive film is disposed between the platform and the semiconductor package. the roller is disposed inside the platform and under the adhesive film, where the roller includes a body and a plurality of protrusions distributed over the body. the moving mechanism is connected to the roller to control a movement of the roller. the collector element is disposed over the platform and the adhesive film, where the collector element is configured to remove the semiconductor package from the adhesive film.
Inventor(s): Bo Chen CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Wei Wu of Hsinchu County 302 (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Li Tsai of Miaoli County 356 (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, B08B5/02, H01L21/677
CPC Code(s): H01L21/67288
Abstract: the present disclosure relates to a contamination controlled semiconductor processing system. the contamination controlled semiconductor processing system includes a processing chamber, a contamination detection system, and a contamination removal system. the processing chamber is configured to process a wafer. the contamination detection system is configured to determine whether a contamination level on a surface of the door is greater than a baseline level. the contamination removal system is configured to remove contaminants from the surface of the door in response to the contamination level being greater than the baseline level.
Inventor(s): Yu-Chi TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chueh-Chi KUO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/683, G03F7/00, G03F7/20
CPC Code(s): H01L21/6833
Abstract: an electrostatic substrate holder for use in an extreme ultraviolet radiation lithography system includes a substrate receiving surface having a plurality of gas passages in fluid communication with a variable gas pressure pump. varying the pressure in a void space between the backside of the substrate and the substrate receiving surface of the substrate holder promotes removal of non-gaseous materials within the void space between the backside of the substrate and the substrate receiving surface of the substrate holder.
Inventor(s): Chung-Ting Ko of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Tai-Chun Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jr-Hung Li of Chupei City (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088, H01L29/66
CPC Code(s): H01L21/823431
Abstract: a method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. the isolation regions extend into a semiconductor substrate. a portion of the semiconductor fin is etched to form a trench, which extends lower than bottom surfaces of the isolation regions, and extends into the semiconductor substrate. the method further includes filling the trench with a first dielectric material to form a first fin isolation region, recessing the first fin isolation region to form a first recess, and filling the first recess with a second dielectric material. the first dielectric material and the second dielectric material in combination form a second fin isolation region.
Inventor(s): Keng-Yao CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Yun CHANG of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Chang WEN of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/02, H01L21/762, H01L21/764, H01L27/088
CPC Code(s): H01L21/823481
Abstract: the embodiments described herein are directed to a method for mitigating the fringing capacitances generated by patterned gate structures. the method includes forming a gate structure on fin structures disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first section and a second section, where the first and second sections are spaced apart by the opening. the method also includes forming a fill structure in the opening, where forming the fill structure includes depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening and depositing silicon oxide on the silicon nitride liner.
Inventor(s): Peng-Wei Chu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Li Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yasutoshi Okuno of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/285, H01L27/092
CPC Code(s): H01L21/823814
Abstract: a semiconductor device and a method of making the same are provided. a method according to the present disclosure includes forming a first type epitaxial layer over a second type source/drain feature of a second type transistor, forming a second type epitaxial layer over a first type source/drain feature of a first type transistor, selectively depositing a first metal over the first type epitaxial layer to form a first metal layer while the first metal is substantially not deposited over the second type epitaxial layer over the first type source/drain feature, and depositing a second metal over the first metal layer and the second type epitaxial layer to form a second metal layer.
Inventor(s): Wei-Chih Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang Hu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Han Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Chun Cho of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L23/48, H01L23/544
CPC Code(s): H01L23/3157
Abstract: a semiconductor package and a method of forming the same are provided. the semiconductor package includes a semiconductor die and a redistribution structure disposed on the semiconductor die. the redistribution structure includes an alignment auxiliary layer, a plurality of dielectric layers and a plurality of conductive patterns. the alignment auxiliary layer has a light transmittance for a light with a wavelength range of about 350-550 nm lower than that of one of the plurality of dielectric layers.
Inventor(s): Kuan Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yen LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Wei PENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/8238, H01L27/092
CPC Code(s): H01L23/481
Abstract: a device includes: an active region extending in a first direction; a first metal-to-s/d (md) contact structure extending in a perpendicular second direction, and over and coupled to the active region; a first layer of metallization over the first md contact structure and having m_1st segments extending in the first direction and each having a substantially same width relative to the second direction, the m_1st segments including m_1st routing segments, and an m_1st power grid (pg) segment having a portion over and coupled to the first md contact structure; a second layer of metallization over the first layer of metallization and having m_2nd segments that extend in the second direction and include an m_2nd pg rail configured for a first reference voltage, a portion thereof being over and coupled to the m_1st pg segment. the m_2nd pg rail extending across multiple cell regions.
Inventor(s): RUI-WEN SONG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yuan Teng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hung Liu of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Wei Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L21/56, H01L23/29, H01L23/544
CPC Code(s): H01L23/49811
Abstract: a semiconductor device includes a die, a redistribution layer (rdl) structure including a first polymer layer, a second polymer layer and a ubm layer. the die is encapsulated by an encapsulant. the rdl structure is disposed over the encapsulant. the second polymer layer is disposed on the first polymer layer, wherein a transmittance of the second polymer layer is smaller than a transmittance of the first polymer layer. the ubm layer is disposed over and electrically connected to the rdl structure, wherein the ubm layer is disposed in the first polymer layer and the second polymer layer.
Inventor(s): Po-Yao Lin of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, G06F30/3953, G06F119/18, H01L23/00
CPC Code(s): H01L23/49816
Abstract: a structure includes a first package component including a first conductive pad, and a second package component overlying the first package component. the second package component includes a surface dielectric layer, and a conductive bump protruding lower than the surface dielectric layer. the first conductive bump includes a first sidewall facing away from a center of the first package component, and a second sidewall facing toward the center. a solder bump joins the first conductive pad to the first conductive bump. the solder bump contacts the first sidewall. an underfill is between the first package component and the second package component, and the underfill contacts the second sidewall.
Inventor(s): Chen-Shien Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ting Hao Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Chun Chiang of Miaoli (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chia Lai of Zhunan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L21/768, H01L23/00
CPC Code(s): H01L23/49827
Abstract: a device includes: a first integrated circuit (ic) die; a first dielectric material around first sidewalls of the first ic die; a second ic die over and electrically coupled to the first ic die; and a second dielectric material over the first dielectric material and around second sidewalls of the second ic die, where in a top view, the second sidewalls of the second ic die are disposed within, and are spaced apart from, the first sidewalls of the first ic die.
Inventor(s): Hsin-Yen Huang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Ya Lo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Kuan Lee of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Lin Teng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chin Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin Shue of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768
CPC Code(s): H01L23/5226
Abstract: some embodiments of the present disclosure relate to an integrated chip, including a semiconductor substrate and a dielectric layer disposed over the semiconductor substrate. a pair of metal lines are disposed over an upper surface of the dielectric layer. a barrier layer structure extends along nearest neighboring sidewalls of the pair of metal lines, where the barrier layer structure includes a different material than the dielectric layer. a dielectric liner isdisposed between inner sidewalls of the barrier layer structure. a cavity is defined by surfaces of the dielectric liner, the barrier layer structure, and the dielectric layer.
Inventor(s): Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Jung Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jyun-Siang Peng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/56, H01L21/768, H01L23/00, H01L23/31, H01L23/48, H01L23/528, H01L23/532, H01L23/544, H01L25/065
CPC Code(s): H01L23/5226
Abstract: a package structure includes at least one semiconductor die, an insulating encapsulant and a redistribution structure. the at least one semiconductor die has a plurality of conductive posts, wherein a top surface of the plurality of conductive posts has a first roughness. the insulating encapsulant is encapsulating the at least one semiconductor die. the redistribution structure is disposed on the insulating encapsulant in a build-up direction and is electrically connected to the at least one semiconductor die. the redistribution structure includes a plurality of conductive via portions and a plurality of conductive body portions embedded in dielectric layers, wherein a top surface of the plurality of conductive body portions has a second roughness, and the second roughness is greater than the first roughness.
Inventor(s): Te-Hsin CHIU of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Wei PENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng LIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528, H01L27/02
CPC Code(s): H01L23/5226
Abstract: an integrated circuit structure is provided, including a gate, a first conductive line and a pair of second conductive lines, and a first feed-through via. the gate is disposed on a front side of the integrated circuit structure and extends in a first direction on a first side of a dielectric layer. the first conductive line and a pair of second conductive lines are disposed on a second side, opposite of the first side, of the dielectric layer and on a back side, opposite of the front side, of the integrated circuit structure. the first conductive line is interposed between the pair of second conductive lines in a layout view. the first feed-through via extends through the dielectric layer in a second direction different from the first direction. the first feed-through via couples the gate to the first conductive line.
Inventor(s): Chia-Pang Kuo of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Sean Yang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Yue-Guo Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsai Hsi-Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Feng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Wen Su of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/768, H01L23/528
CPC Code(s): H01L23/53223
Abstract: devices with aluminum structures and methods of fabrication are provided. an exemplary device includes an interconnect structure and an aluminum structure electrically connected to the interconnect structure. the aluminum structure includes a first aluminum layer, a migration barrier layer over the first aluminum layer, and a second aluminum layer over the migration barrier layer.
Inventor(s): Chin-Hua WANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chen LAI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Tai CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Chia YANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Sheng LIN of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/60, H01L21/768, H01L23/00, H01L25/065
CPC Code(s): H01L23/5384
Abstract: a chip package structure is provided. the chip package structure includes a substrate. the chip package structure includes a buffer structure penetrating into the substrate. a first young's modulus of the buffer structure is less than a second young's modulus of the substrate. the chip package structure includes a first wiring structure over the buffer structure and the substrate. the first wiring structure includes a first dielectric structure and a first wiring layer in the first dielectric structure. the chip package structure includes a chip package bonded to the first wiring structure. the chip package has an interposer substrate and a chip structure over the interposer substrate, and a first corner of the interposer substrate and a second corner of the chip structure overlap the buffer structure in a top view of the chip package and the buffer structure.
Inventor(s): Sen-Kuei Hsu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yu Pan of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chang Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L23/66, H01P3/08, H03H7/01
CPC Code(s): H01L23/5386
Abstract: a semiconductor package is provided. the semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. the polymer layers cover a front surface of the semiconductor die. the redistribution elements and the passive filter are disposed in the stack of polymer layers. the passive filter includes a ground plane and conductive patches. the ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. the ground plane is electrically coupled to a reference voltage. the conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (dc) voltage.
Inventor(s): Mingni Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Chin Tsou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Jing Wu of Zaoqiao Township (TW) for taiwan semiconductor manufacturing company, ltd., Shiou-Fan Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Yih Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/58, H01L21/768, H01L23/48, H01L23/522, H01L25/065
CPC Code(s): H01L23/585
Abstract: a method includes forming a plurality of low-k dielectric layers over a semiconductor substrate, forming a first plurality of dummy stacked structures extending into at least one of the plurality of low-k dielectric layers, forming a plurality of non-low-k dielectric layers over the plurality of low-k dielectric layers, and forming a second plurality of dummy stacked structures extending into the plurality of non-low-k dielectric layers. the second plurality of dummy stacked structures are over and connected to corresponding ones of the first plurality of dummy stacked structures. the method further includes etching the plurality of non-low-k dielectric layers, the plurality of low-k dielectric layers, and the semiconductor substrate to form a via opening. the via opening is encircled by the first plurality of dummy stacked structures and the second plurality of dummy stacked structures. the via opening is then filled to form a through-via.
Inventor(s): Po-Hao Tsai of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Chih Yew of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/66, H01L21/56, H01L23/00, H01L23/31, H01L23/48, H01L23/498, H01L23/538, H01Q1/22, H01Q9/04, H01Q9/28, H01Q21/06
CPC Code(s): H01L23/66
Abstract: a device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.
Inventor(s): Jiun Yi Wu of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/20
Abstract: in an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.
Inventor(s): Meng-Han LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Sheng CHANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L21/82
CPC Code(s): H01L27/0288
Abstract: an integrated circuit (ic) structure includes a semiconductor substrate, a shallow trench isolation, and a capacitor. the sti is in the semiconductor substrate. the capacitor is over the sti. the capacitor includes first a dummy gate strip, a second dummy gate strip extending in parallel with the first dummy gate strip, a plurality of first metal contacts landing on the first dummy gate strip, and a plurality of second metal contacts landing on the second dummy gate strip.
Inventor(s): Yi-Chun Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jih-Jse Lin of Sijhih City (TW) for taiwan semiconductor manufacturing company, ltd., Ryan Chia-Jen Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/306, H01L21/8234, H01L29/06, H01L29/66, H01L29/78
CPC Code(s): H01L27/0886
Abstract: a semiconductor device includes a substrate; a first fin structure extending along a first lateral direction; a second fin structure extending along the first lateral direction; a first gate structure extending along a second lateral direction and straddles the first fin structure; a second gate structure extending along the second lateral direction and straddles the second fin structure. the semiconductor device further includes a dielectric cut structure that separates the first and second gate structures from each other. the dielectric cut structure extends into the substrate and comprises a first portion and a second portion. a width of the first portion along the second lateral direction increases with increasing depth into the substrate and a width of the second portion along the second lateral direction decreases with increasing depth into the substrate. the second portion is located below the first portion.
Inventor(s): Wan-Yi Kao of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Ping Lee of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Che-Hao Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Heng Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Cheng Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8234, H01L29/06, H01L29/66, H01L29/78
CPC Code(s): H01L27/0924
Abstract: in an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.
Inventor(s): Chun-Liang LU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hao CHOU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng LEE of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Lin CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14689
Abstract: some implementations described herein provide an optoelectronic device and methods of formation. the optoelectronic device is fabricated using a series of operations that includes a patterning operation using a layer of a negative photoresist material, followed by a single dry etch operation, a single wet strip operation, and a single wet etch operation. the series of operations may include a reduced number of operations relative to another series of operations that include a patterning operation using a layer of a positive photoresist material. through the reduced number of operations, handling-induced damage to the device may be reduced. additionally, the high absorption structure may include a quantum efficiency that is greater relative to another quantum efficiency of another high absorption structure formed through the series of operations that include the patterning operation using the layer of the positive photoresist material.
Inventor(s): Chun-Tsung Kuo of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jiech-Fun Lu of Madou Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768
CPC Code(s): H01L28/24
Abstract: various embodiments of the present disclosure are directed towards an integrated chip including a resistor layer over a substrate. an isolation structure contacts a first pair of opposing sidewalls of the first resistor layer. the isolation structure includes a body structure and a liner layer disposed on opposing sidewalls of the body structure.
Inventor(s): Hsing-Lien Lin of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Lin Chu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yuan Tsai of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01G4/06
CPC Code(s): H01L28/60
Abstract: various embodiments of the present disclosure are directed towards an amorphous bottom electrode structure (bes) for a metal-insulator-metal (mim) capacitor. the mim capacitor comprises a bottom electrode, an insulator layer overlying the bottom electrode, and a top electrode overlying the insulator layer. the bottom electrode comprises a crystalline bes and the amorphous bes, and the amorphous bes overlies the crystalline bes and forms a top surface of the bottom electrode. because the amorphous bes is amorphous, instead of crystalline, a top surface of the amorphous bes may have a small roughness compared to that of the crystalline bes. because the amorphous bes forms the top surface of the bottom electrode, the top surface of the bottom electrode may have a small roughness compared to what it would otherwise have if the crystalline bes formed the top surface. the small roughness may improve a lifespan of the mim capacitor.
Inventor(s): Yingkit Felix Tsui of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01G4/30, H01L23/522
CPC Code(s): H01L28/91
Abstract: various embodiments of the present disclosure are directed towards an integrated chip including a conductive base layer overlying a semiconductor substrate. a plurality of conductive pillar structures vertically extending from the conductive base layer in a direction away from the semiconductor substrate. the conductive pillar structures are laterally offset from one another. a plurality of conductive layers and a plurality of capacitor dielectric layers are disposed over the conductive pillar structures. the conductive layers and the capacitor dielectric layers are stacked alternatingly with one another. the conductive layers and the capacitor dielectric layers laterally wrap around outer perimeters of the conductive pillar structures.
Inventor(s): Huang-Lin Chao of Hillsboro OR (US) for taiwan semiconductor manufacturing company, ltd., Shen-Yang Lee of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Pi Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/423, H01L29/51, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a method for fabricating a semiconductor device is disclosed. the method includes exposing one or more surfaces of a conduction channel of a transistor, overlaying the one or more surfaces with a first high-k dielectric layer; overlaying the first high-k dielectric layer with a second high-k dielectric layer; depositing a ruthenium-containing layer over the second high-k dielectric layer; and performing a first annealing process with a temperature not greater than a threshold so as to remove oxygen vacancies from at least the first high-k dielectric layer.
Inventor(s): Pei-Yu Chou of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Ku Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/40, H01L21/02, H01L21/768, H01L29/423, H01L29/51
CPC Code(s): H01L29/401
Abstract: a method for semiconductor fabrication includes forming a metal gate surrounded by a first silicon oxide layer, wherein a metallic surface of the metal gate is exposed. the method further includes selectively depositing a silicon nitride layer on the metallic surface and not on the first silicon oxide layer, and depositing a second silicon oxide layer on the first silicon oxide layer and on the silicon nitride layer.
Inventor(s): Yung-Chin Hou of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Lee-Chung Lu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng Tzeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Lin of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yen Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L29/41733
Abstract: a device includes a first transistor layer comprising a first gate electrode and a second transistor layer comprising a second gate electrode that is stacked with the first transistor layer. n intermetal structure comprising a conductive line is disposed between the first transistor layer and the second transistor layer. a first gate contact extends along a sidewall of the first gate electrode from a top surface of the first gate electrode to the conductive line g. a second gate contact extends along a sidewall of the second gate electrode from a top surface of the second gate electrode to the conductive line. the first gate electrode is electrically connected to the second gate electrode by the first gate contact, the second gate contact, and the conductive line.
Inventor(s): Chien Ning Yao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Cheng Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Cheng Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Zhi-Chang Lin of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Hung Chang of Yuanlin City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Han Chuang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/41775
Abstract: a semiconductor device and a method of fabricating the semiconductor device are disclosed. the method includes forming a polysilicon structure on a substrate, depositing a first spacer layer on the polysilicon structure, depositing a second spacer layer on the first spacer layer, forming a s/d region on the substrate, removing the second spacer layer, depositing a third spacer layer on the first spacer layer and on the s/d region, depositing an esl on the third spacer layer, depositing an ild layer on the etch stop layer, and replacing the polysilicon structure with a gate structure surrounding the nanostructured layer.
Inventor(s): Kai-Hsuan Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Ming Lee of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Kai Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Yun Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ming Chen of Hsin-Chu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L29/06, H01L29/423, H01L29/51, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H01L29/41775
Abstract: a semiconductor device includes a fin-shape structure protruding from a substrate, a gate stack disposed above the fin-shape structure, an epitaxial feature disposed above the fin-shape structure, and a gate spacer disposed on a sidewall of the gate stack. the gate spacer includes an air gap. the air gap exposes a portion of the epitaxial feature.
Inventor(s): Huan-Chieh Su of Changua County (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yuan Chen of HsinChu (TW) for taiwan semiconductor manufacturing company, ltd., Lo-Heng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Zhen Yu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Lin-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L29/06, H01L29/786
CPC Code(s): H01L29/42392
Abstract: semiconductor structures and methods of forming the same are provided. a semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. a bottom surface of the first gate structure is in direct contact with the backside gate contact.
Inventor(s): Zheng Long CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/06, H01L29/08, H01L29/10, H01L29/66
CPC Code(s): H01L29/7816
Abstract: a semiconductor device includes a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type. the semiconductor device also includes a channel region, in the second semiconductor region, located laterally between a source region and the first semiconductor region, and a gate electrode above the channel region. the semiconductor device further includes a spacer, overlying the source region, having a first side laterally adjacent to the gate electrode and vertically aligned with a first side surface of the source region.
Inventor(s): Shahaji B. MORE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Huai-Tei Yang of Hsin-Chu Ciry (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chieh Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Han Lee of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L21/8238, H01L27/092, H01L29/161, H01L29/165, H01L29/167, H01L29/66
CPC Code(s): H01L29/7848
Abstract: the present disclosure describes a method to form silicon germanium (sige) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained sige channel. the method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. the method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. the method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.
Inventor(s): Yu-Sheng Wang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Cheng Hung of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Ching Lee of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Chiang Wu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hwanq Su of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/49, H01L29/51, H01L29/66
CPC Code(s): H01L29/7851
Abstract: a method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. the method also includes forming source and drain regions adjacent the gate stack.
Inventor(s): Marcus Johannes Henricus Van Dal of Linden (BE) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L27/12, H01L29/06, H01L29/41, H01L29/423, H01L29/66, H01L29/78, H10B61/00, H10B63/00
CPC Code(s): H01L29/78696
Abstract: a transistor includes a first gate structure, a channel layer, and source/drain contacts. the first gate structure includes metallic nanosheets. each of the metallic nanosheets includes a top surface, a bottom surface opposite to the top surface, and sidewalls connecting the top surface and the bottom surface. the channel layer surrounds the top surfaces, the bottom surfaces, and the sidewalls of the metallic nanosheets. the source/drain contacts are electrically connected to the channel layer. a portion of the channel layer is located between the source/drain contacts and the metallic nanosheets.
Inventor(s): Chin-Hua Wen of Toufen Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03H11/28
CPC Code(s): H03H11/28
Abstract: an impedance matching circuit is provided. the impedance matching circuit includes a reference voltage generator configured to generate a reference voltage. a code generator is configured to generate a first calibration code by comparing the reference voltage with a first voltage associated with a first node and a second calibration code by comparing the reference voltage with a second voltage associated with a second node. a first resistance unit is configured to supply the first voltage to the first node in response to the first calibration code to calibrate its resistance to be equal to a reference resistance. a second resistance unit is configured to supply the second voltage to the second node in response to the second calibration code to thereby calibrate its resistance to the reference resistance.
Inventor(s): Shenggao Li of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K5/134, H03K3/03, H03K19/0185
CPC Code(s): H03K5/134
Abstract: systems and methods are provided for a delay line circuit that comprises a delay line core and a first current mirror circuit. the delay line core includes a plurality of inverters connected in series. each of the plurality of inverters is coupled to a first common node. the first current mirror circuit includes a first current source configured to generate a first digital-to-analog (dac) current, a first transistor coupled to the first current source, and a plurality of first controlling transistors coupled to the first transistor and the first common node. the plurality of first controlling transistors generates a first mirror current at the first common node based on the first dac current. a delay time of the delay line core is controlled based on the first mirror current.
Inventor(s): Wei Shuo Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K5/156, H03L7/081, H03L7/095
CPC Code(s): H03K5/1565
Abstract: one embodiment of a duty-cycle corrector phase shift (dccps) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and dc sampler circuits. another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, dc sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. in some instances, the dccps circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.
Inventor(s): Shih-Lien Linus Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Che Tsai of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-En Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H04L9/32, H01L21/8238, H03K19/096, H04L9/08
CPC Code(s): H04L9/3278
Abstract: a puf generator includes a difference generator circuit with first and second transistors having a first predetermined vt. the difference generator circuit is configured to provide a first output signal for generating a puf signature based on respective turn on times of the first and second transistors. an amplifier includes a plurality of transistors having a second predetermined vt. the amplifier is configured to receive the first output signal and output the puf signature.
Inventor(s): Ping-Wei Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Ming Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Lin Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, G11C11/412, G11C11/419, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10B10/12
Abstract: a memory cell includes a first active region providing a plurality of first nano-structures for a write-port pass-gate transistor, a second active region providing a plurality of second nano-structures for a write-port pull-up transistor, and a third active region providing a plurality of third nano-structures for a read-port pull-down transistor. the first active region has a first width, the second active region has a second width, and the third active region having a third width. the third width is larger than the first width, and the first width is larger than the second width.
Inventor(s): Ping-Wei Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Ming Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Lin Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/125
Abstract: a memory cell includes a device layer including a plurality of transistors and an interconnect structure disposed over the device layer. each of the transistors includes a gate structure extending lengthwise in a first direction. the interconnect structure includes a bottommost metal line layer electrically coupled to the transistors in the device layer. the bottommost metal line layer includes metal lines arranged in first, second, third, fourth, fifth, and sixth metal tracks in order from first to sixth along the first direction. a distance between any adjacent two of the first, second, third, fourth, fifth, and six metal tracks measured along the first direction is uniform. the first metal track includes a metal line electrically coupled to an electric ground of the memory cell. the sixth metal track includes a metal line electrically coupled to a power supply of the memory cell.
Inventor(s): Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, H01L29/06, H01L29/423, H01L29/78
CPC Code(s): H10B10/125
Abstract: semiconductor device and the manufacturing method thereof are disclosed. an exemplary semiconductor device includes a substrate including top portions isolated by an isolation structure, first semiconductor layers over a first top portion of the substrate in a first region, and a first gate structure wrapping each of the first semiconductor layers and covering a top surface and sidewalls of the first top portion of the substrate extending above the isolation structure. the first semiconductor layers are stacked up and separated from each other, and each first semiconductor layer has a first width. a bottom surface of the first gate structure is below the top surface of the substrate for a first depth which is at least half of the first width.
Inventor(s): Ping-Wei Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Lien-Jung Hung of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Lin Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/18
Abstract: a semiconductor structure includes a memory cell, a logic cell, and a transition region between the memory cell and the logic cell. the memory cell includes a first active region and a plurality of first gate structures with a gate pitch. the logic cell includes a second active region and a plurality of second gate structures with the gate pitch. the transition region includes a first dielectric feature and a second dielectric feature. the first dielectric feature divides the first active region into a first segment partially in the transition region and a second segment fully in the transition region. the second dielectric feature divides the second active region into a third segment partially in the transition region and a fourth segment fully in the transition region.
Inventor(s): Ping-Wei Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Ming Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Lin Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/18
Abstract: a semiconductor structure includes a memory cell, one or more logic cells configured to provide logic function to the memory cell, and an interconnect structure disposed over the memory cell and the one or more logic cells. the interconnect structure includes a bit line, a bit line bar, a first voltage line, and a second voltage line located in a same metal line layer of the interconnect structure. at least one of the bit line and the bit line bar extends from inside a boundary of the one or more logic cells and into a boundary of the memory cell. at least one of the first and second voltage lines extends from inside the boundary of the one or more logic cells and into the boundary of the memory cell.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on September 12th, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- G01R1/067
- G01R31/28
- CPC G01R1/06761
- Taiwan semiconductor manufacturing company, ltd.
- G02B6/136
- G02B5/18
- G02B6/122
- H01L21/306
- H01L21/308
- CPC G02B6/136
- G03F1/24
- CPC G03F1/24
- G03F1/64
- CPC G03F1/64
- G06F3/06
- CPC G06F3/0638
- G06F30/392
- G06F30/373
- G06F30/394
- CPC G06F30/392
- G06F30/31
- G06F30/327
- G06F119/18
- G11C11/22
- G11C7/10
- CPC G11C11/2255
- G11C11/412
- G11C11/419
- H10B10/00
- CPC G11C11/412
- H01J37/32
- CPC H01J37/32651
- H01L21/28
- H01L21/3115
- H01L21/8234
- H01L27/088
- H01L29/51
- CPC H01L21/28185
- H01L21/321
- B24B9/06
- B24B37/04
- B24B37/24
- B24B37/26
- CPC H01L21/3212
- H01L21/56
- H01L23/00
- H01L23/48
- H01L25/065
- CPC H01L21/563
- H01L21/67
- F27B17/00
- F27D3/00
- F27D5/00
- H01L21/324
- CPC H01L21/67103
- H01L21/683
- CPC H01L21/67132
- B08B5/02
- H01L21/677
- CPC H01L21/67288
- G03F7/00
- G03F7/20
- CPC H01L21/6833
- H01L29/66
- CPC H01L21/823431
- H01L21/02
- H01L21/762
- H01L21/764
- CPC H01L21/823481
- H01L21/8238
- H01L21/285
- H01L27/092
- CPC H01L21/823814
- H01L23/31
- H01L23/544
- CPC H01L23/3157
- CPC H01L23/481
- H01L23/498
- H01L21/48
- H01L23/29
- CPC H01L23/49811
- G06F30/3953
- CPC H01L23/49816
- H01L21/768
- CPC H01L23/49827
- H01L23/522
- CPC H01L23/5226
- H01L23/528
- H01L23/532
- H01L27/02
- CPC H01L23/53223
- H01L23/538
- H01L21/60
- CPC H01L23/5384
- H01L23/66
- H01P3/08
- H03H7/01
- CPC H01L23/5386
- H01L23/58
- CPC H01L23/585
- H01Q1/22
- H01Q9/04
- H01Q9/28
- H01Q21/06
- CPC H01L23/66
- CPC H01L24/20
- H01L21/82
- CPC H01L27/0288
- H01L29/06
- H01L29/78
- CPC H01L27/0886
- CPC H01L27/0924
- H01L27/146
- CPC H01L27/14689
- CPC H01L28/24
- H01G4/06
- CPC H01L28/60
- H01G4/30
- CPC H01L28/91
- H01L29/423
- H01L29/775
- H01L29/786
- CPC H01L29/0673
- H01L29/40
- CPC H01L29/401
- H01L29/417
- CPC H01L29/41733
- CPC H01L29/41775
- CPC H01L29/42392
- H01L29/08
- H01L29/10
- CPC H01L29/7816
- H01L29/161
- H01L29/165
- H01L29/167
- CPC H01L29/7848
- H01L29/49
- CPC H01L29/7851
- H01L27/12
- H01L29/41
- H10B61/00
- H10B63/00
- CPC H01L29/78696
- H03H11/28
- CPC H03H11/28
- H03K5/134
- H03K3/03
- H03K19/0185
- CPC H03K5/134
- H03K5/156
- H03L7/081
- H03L7/095
- CPC H03K5/1565
- H04L9/32
- H03K19/096
- H04L9/08
- CPC H04L9/3278
- CPC H10B10/12
- CPC H10B10/125
- CPC H10B10/18