Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on May 8th, 2025
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on May 8th, 2025
Taiwan Semiconductor Manufacturing Company, Ltd.: 76 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L23/00 (13), H10D30/01 (13), H10D64/01 (12), H10D62/10 (12), H01L29/66 (11) H10D64/017 (4), H01L23/5226 (4), H10D30/6735 (3), H10D84/834 (2), H10D30/6757 (2)
With keywords such as: layer, structure, semiconductor, gate, substrate, device, forming, source, metal, and drain in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Wen-Chih Lin of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hsuan-Ting Kuo of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Cheng-Yu Kuo of Kaohsiung City TW for taiwan semiconductor manufacturing company, ltd., Yen-Hung Chen of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chia-Shen Cheng of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Chao-Wei Li of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Wen-Chih Chiou of Miaoli County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42, H01L23/00, H01L25/16
CPC Code(s): G02B6/4214
Abstract: a package assembly and a manufacturing method thereof are provided. the package assembly includes a photonic integrated circuit component, an electric integrated circuit component, a lens and an optical signal port. the photonic integrated circuit component comprises an optical input/output portion configured to transmit and receive optical signal. the electric integrated circuit component is electrically connected to the photonic integrated circuit component. the lens is disposed on a sidewall of the photonic integrated circuit component. the optical signal port is optically coupled to the optical input/output portion.
Inventor(s): Yun-Yue LIN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/22, G03F1/24, G03F1/38, G03F1/54
CPC Code(s): G03F1/22
Abstract: a method of manufacturing an extreme ultraviolet mask, including forming a multilayer mo/si stack including alternating mo and si layers over a first major surface of a mask substrate, and forming a capping layer over the multilayer mo/si stack. an absorber layer is formed on the capping layer, and a hard mask layer is formed over the absorber layer. the hard mask layer is patterned to form a hard mask layer pattern. the hard mask layer pattern is extended into the absorber layer to expose the capping layer and form a mask pattern. a border pattern is formed around the mask pattern. the border pattern is extended through the multilayer mo/si stack to expose the mask substrate and form a trench surrounding the mask pattern. a passivation layer is formed along sidewalls of the trench.
Inventor(s): Yen-Tung HU of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Danping PENG of Fremont CA US for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/82
CPC Code(s): G03F1/82
Abstract: a method includes receiving a layout; performing an optimization process to the layout to generate an optimized layout, wherein the optimization process comprising simulating a mask image of a photomask based on the layout; simulating an aerial image projected on a photoresist layer based on the mask image; simulating a resist image of the photoresist layer based on the aerial image; simulating an etch image of a layer underneath the photoresist layer based on the resist image; and performing an inverse lithographic technology (ilt) process to generate the optimized layout, wherein the ilt process is performed based on the mask image, the aerial image, the resist image, and the etch image; and fabricating a photomask based on the optimized layout.
Inventor(s): Chih-Cheng LIU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ming-Hui WENG of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Jr-Hung LI of Chupei City TW for taiwan semiconductor manufacturing company, ltd., Yahru CHENG of Taipei TW for taiwan semiconductor manufacturing company, ltd., Chi-Ming YANG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Tze-Liang LEE of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yuansun Village TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/004, C23C16/455, C23C16/56, G03F7/16, G03F7/20, G03F7/38, H01L21/027
CPC Code(s): G03F7/0042
Abstract: a method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate. a first precursor and a second precursor are combined. the first precursor is an organometallic having a formula: mrx, where m is one or more of sn, bi, sb, in, and te, r is one or more of a c7-c11 aralkyl group, a c3-c10 cycloalkyl group, a c2-c10 alkoxy group, and a c2-c10 alkylamino group, x is one or more of a halogen, a sulfonate group, and an alkylamino group, and 1≤a≤2, b≥1, c≥1, and b+c≤4, and the second precursor is one or more of water, an amine, a borane, and a phosphine. the photoresist layer is selectively exposed to actinic radiation to form a latent pattern. the latent pattern is developed by applying a developer to the selectively exposed photoresist layer.
Inventor(s): Ming-Hui WENG of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Chen-Yu LIU of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Cheng-Han WU of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yilang County TW for taiwan semiconductor manufacturing company, ltd., Chin-Hsiang LIN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/40, G03F1/82, G03F7/00, G03F7/30, G03F7/32
CPC Code(s): G03F7/40
Abstract: a method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. the patterned resist layer is developed by using a positive tone developer. the patterned resist layer is rinsed using a basic aqueous rinse solution. a ph value of the basic aqueous rinse solution is lower than a ph value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20� c. to about 40� c.
Inventor(s): Hung-Chih HSIEH of Miaoli County TW for taiwan semiconductor manufacturing company, ltd., Ming-Hsiao WENG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, H01L21/66
CPC Code(s): G03F7/70633
Abstract: an overlay error measurement method includes disposing a lower-layer pattern over a substrate that includes disposing a first pattern having a first plurality of first sub-patterns extending in a first interval along a first direction and being arranged with a first pitch in a second direction crossing the first direction. the method includes disposing a second pattern having a second plurality of second sub-patterns extending in a second interval along the first direction and being arranged with a second pitch, smaller than the first pitch, in the second direction crossing the first direction. the second sub-patterns are disposed interleaved between the first sub-patterns. the method includes disposing an upper-layer pattern including a third pattern having the first pitch and at least partially overlapping with the lower-layer pattern over the lower-layer pattern and determining an overlay error between the lower-layer pattern and the upper-layer pattern.
Inventor(s): Shinn-Sheng YU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ru-Gun LIU of Zhubei City TW for taiwan semiconductor manufacturing company, ltd., Hsu-Ting HUANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Kenji YAMAZOE of Campbell CA US for taiwan semiconductor manufacturing company, ltd., Minfeng CHEN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Shuo-Yen CHOU of Hualien County TW for taiwan semiconductor manufacturing company, ltd., Chin-Hsiang LIN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, G03F7/20
CPC Code(s): G03F7/70641
Abstract: a method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. a number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. sequences snx0, snx1, snx, snxr, sny0, sny1, sny, and snyr are formed. p*(nbx+1)−2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. a distance of each stepping operation in order follows the sequence snx.
Inventor(s): Chun-Han LIN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chieh HSIEH of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Sheng-Kang YU of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Shang-Chieh CHIEN of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Heng-Hsin LIU of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Li-Jui CHEN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, H05G2/00
CPC Code(s): G03F7/70916
Abstract: a method includes irradiating debris deposited in an extreme ultraviolet (euv) lithography system with laser, controlling one or more of a wavelength of the laser or power of the laser to selectively vaporize the debris and limit damage to the euv) lithography system, and removing the vaporized debris.
Inventor(s): Yung-Shun Chen of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Tzu-Ching Lin of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Shu-Chin Tai of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Amit Kundu of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Yung-Chow Peng of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Hung-Hsiang Lin of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Yi-Peng Weng of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chung-Ting Lu of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F30/398
CPC Code(s): G06F30/392
Abstract: a computer readable medium comprising computer executable instructions for carrying out a method is disclosed. the method includes: generating a schematic of an integrated circuit including a plurality of components, each of the components associated with a format, the format indicating a matching group that represents a respective circuit functionality; merging a first device array layout, which corresponds to a first subset of the components that share a first matching group, and a second device array layout, which corresponds to a second subset of the components that share a second matching group, to form a third device array layout, in response to detecting that the first device array layout and the second device array layout share a same cell type; forming a first layer enclosing the third device array layout; inserting dummy patterns surrounding the first layer; and inserting a guard ring further surrounding the dummy patterns.
Inventor(s): Xiu-Li YANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ching-Wei WU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., He-Zhou WAN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ming-En BU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C5/14, H03K3/012, H03K3/037, H03K19/0175, H03K19/20
CPC Code(s): G11C5/147
Abstract: a circuit includes a power management circuit configured to receive a first or second control signal, and to supply a first, second or third supply voltage. the power management circuit includes a first level shifter circuit, a first header circuit and a latch circuit. the first level shifter circuit is configured to generate a fourth control signal in response to a fifth control signal. the fourth control signal is a level shifted version of the fifth control signal. the first header circuit is configured to supply a first supply voltage of a first voltage supply to a first node in response to the first control signal, or a second supply voltage of a second voltage supply to a second node in response to a first level shifted signal. the latch circuit is configured to generate a first output control signal in response to the first and the fourth control signal.
Inventor(s): Meng-Sheng CHANG of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Yao-Jen YANG of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Yih WANG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Fu-An WU of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/10, G11C5/06, G11C8/08, G11C17/16, G11C17/18, H01L23/522, H01L23/525, H10B20/25
CPC Code(s): G11C7/1096
Abstract: a semiconductor device includes anti-fuse cells. the anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. the first gate and the second gate are separate from each other. the first gate and the second gate extend to cross over the first active area. the at least one first gate via is coupled to the first gate and disposed directly above the first active area. the at least one second gate via is coupled to the second gate. the first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.
Inventor(s): Pei-Chun LIAO of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Yu-Kai CHANG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Yi-Ching LIU of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Yu-Ming LIN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Yih WANG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chieh LEE of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C16/08, G11C16/26, G11C16/32
CPC Code(s): G11C16/08
Abstract: a memory device including a memory array, a driver circuit, and a recover circuit is provided. the memory array includes multiple memory cells. each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. the driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. the recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. the third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.
Inventor(s): Chih-Kai Hu of Taoyuan County TW for taiwan semiconductor manufacturing company, ltd., Ren-Guan Duan of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chiun-Da Shiue of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Chin-Han Meng of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J37/32, C23C16/40, C23C16/455, C23C28/04
CPC Code(s): H01J37/32495
Abstract: an anti-plasma coating formed on a surface of a component in a plasma chamber includes an insulation layer on the surface and a plasma-resistant layer on the insulation layer. the plasma-resistant layer includes one or more stacks, where each stack includes a crystalline layer and an amorphous layer. the anti-plasma coating improves a lifetime of the component in the plasma chamber with high-energy plasma sources.
Inventor(s): Chien-Hsun LIN of Kaohsiung City TW for taiwan semiconductor manufacturing company, ltd., Wen-Chiang HONG of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Jiun-Jie CHAO of Miaoli County TW for taiwan semiconductor manufacturing company, ltd., Jyh-Huei CHEN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L27/088, H01L29/06, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L21/02
Abstract: a method for forming a semiconductor device structure includes forming a fin structure over a substrate. the fin structure has a base layer, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner over the base layer. the method also includes partially removing the fin structure to form an opening exposing side surfaces of the semiconductor layers, the sacrificial layers, and the base layer. the method further includes partially or completely removing the base layer to form a recess, forming a protective structure in the recess, and forming an epitaxial structure filling the opening. in addition, the method includes partially removing the substrate from a backside surface of the substrate to form a contact opening exposing the protective structure and extending towards the epitaxial structure. the method includes forming a backside conductive contact in the contact opening.
Inventor(s): Ya-Wen YEH of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Yu-Tien SHEN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Shih-Chun HUANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Po-Chin CHANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Wei-Liang LIN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Yung-Sung YEN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Wei-Hao WU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Li-Te LIN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Pinyen LIN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ru-Gun LIU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/3213, H01L21/66
CPC Code(s): H01L21/32137
Abstract: in a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. a film is formed over the underlying structure. surface topography of the film is measured and the surface topography is stored as topography data. a local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. a plasma beam intensity of the directional etching is adjusted according to the topography data.
Inventor(s): Sam Vaziri of San Jose CA US for taiwan semiconductor manufacturing company, ltd., Xinyu Bao of Fremont CA US for taiwan semiconductor manufacturing company, ltd., Isha Datye of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/48, H01L23/373, H01L25/00, H01L25/065
CPC Code(s): H01L21/4807
Abstract: one aspect of the present disclosure pertains to a method of semiconductor device fabrication. the method includes forming a transistor on a semiconductor substrate, forming a first metal layer and an overlying second metal layer over the transistor, depositing a thermal dissipation layer over the overlying second metal layer, and annealing the thermal dissipation layer to a temperature above the threshold temperature. the depositing of the thermal dissipation layer is performed below a threshold temperature. during the annealing, the first metal layer and the overlying second metal layer are maintained below the threshold temperature.
Inventor(s): Yun Chen Teng of New Taipei TW for taiwan semiconductor manufacturing company, ltd., Chen-Fong Tsai of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Han-De Chen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Jyh-Cherng Sheu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Huicheng Chang of Tainan TW for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/762, H01L21/67, H10D30/01, H10D30/67, H10D62/10, H10D64/01, H10D86/00
CPC Code(s): H01L21/76251
Abstract: a method of forming a semiconductor device includes loading a first wafer and a second wafer into a wafer bonding system. a relative humidity within the wafer bonding system is measured a first time. after measuring the relative humidity, the relative humidity within the wafer bonding system may be adjusted to be within a desired range. when the relative humidity is within the desired range, the first wafer is bonded to the second wafer.
Inventor(s): Ching-Hung CHEN of Miaoli County TW for taiwan semiconductor manufacturing company, ltd., Yen-Chun HUANG of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Yu-Wei CHOU of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Zhen-Cheng WU of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/764, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L21/764
Abstract: a method includes following steps. a semiconductor fin is formed on a substrate. a shallow trench isolation (sti) region is formed around a lower portion of the semiconductor fin. an sti protection layer is over the sti region. after forming the sti protection layer, source/drain recesses are etched in the semiconductor fin. source/drain epitaxial regions are formed in the source/drain recesses.
Inventor(s): Ming-Da Cheng of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Eugene Chow Chi Hao of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Chang-Jung Hsueh of Taipei TW for taiwan semiconductor manufacturing company, ltd., Chun-Fu Wu of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Wen-Hsiung Lu of Tainan City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, C23C18/38, H01L21/285, H01L21/288
CPC Code(s): H01L21/76877
Abstract: a method includes adding a first additive to an electroplating solution, wherein the first additive is a relatively weak suppressing agent; adding a second additive to the electroplating solution, wherein the second additive is a relatively strong suppressing agent; adding a third additive to the electroplating solution, wherein the third additive is a leveling agent; and depositing copper using the electroplating solution, wherein most of the copper is nanotwinned grains having a (111)-orientation.
Inventor(s): Shu-Hui Su of Tucheng City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/78, H01L23/544
CPC Code(s): H01L21/78
Abstract: the present disclosure relates to a method for forming an integrated chip. the method includes performing a first dicing cut along a first direction and extending into a semiconductor substrate from a first side of the semiconductor substrate. the method includes performing a second dicing cut along the first direction and extending into the semiconductor substrate from a second side of the semiconductor substrate, opposite the first side. the method includes performing a third dicing cut, separate from the second dicing cut, along the first direction and extending into the semiconductor substrate from the second side of the semiconductor substrate.
Inventor(s): I-Che Lee of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Huai-Ying Huang of Jhonghe City TW for taiwan semiconductor manufacturing company, ltd., Yi Chien Lee of New Taipei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, G06T7/00, H01L21/67, H10N50/01
CPC Code(s): H01L22/12
Abstract: various embodiments of the present disclosure are directed towards a method for non-destructive inspection of cell etch redeposition. in some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. the grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. the cells are identified in the grayscale image to determine non-region of interest (non-roi) pixels corresponding to the cells. the non-roi pixels are subtracted from the grayscale image to determine roi pixels. the roi pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. an amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the roi pixels. further, the wafer is processed based on the score.
Inventor(s): Chang-Jhih Syu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hsiu-Hao Tsao of Taichung TW for taiwan semiconductor manufacturing company, ltd., Chih-Hao Yu of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Yu-Jiun Peng of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chang-Yun Chang of Taipei TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, H10D30/01, H10D64/01, H10D64/27, H10D84/01, H10D84/03
CPC Code(s): H01L22/20
Abstract: a system includes a gate formation tool configured to form a sacrificial gate structure and a replacement gate structure, a device dimension measuring tool configured to measure a dimension of the sacrificial gate structure, and a determination unit configured to pick an etching recipe from a series of etching recipes based on the measured dimension of the sacrificial gate structure. the gate formation tool is also configured to partially remove the sacrificial gate structure using the picked etching recipe to form a gate trench for filling the replacement gate structure therein. a portion of the sacrificial gate structure remains in the gate trench, and the series of etching recipes differ at least in a size of the remaining portion of the sacrificial gate structure.
Inventor(s): Chih-Hao Chen of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Po-Yuan Cheng of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Pu Wang of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Li-Hui Cheng of New Taipei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/373, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/498, H01L23/538, H01L25/065
CPC Code(s): H01L23/3736
Abstract: a manufacturing method of a package structure includes: forming a first package component, where the first package component includes a first insulating encapsulation laterally covering semiconductor dies and a redistribution structure formed on the first insulating encapsulation and the semiconductor dies; coupling the first package component to a second package component; forming an underfill layer between the first and second package component, where the underfill layer extends to cover a sidewall of the first package component; forming a metallic layer on opposing surfaces of the semiconductor dies and the first insulating encapsulation by using a jig, where a window of the jig accessibly exposes the opposing surfaces of the semiconductor dies and the first insulating encapsulation, and a peripheral region of the opposing surface of the first insulating encapsulation is shielded by the jig.
Inventor(s): Min-Feng Kao of Chiayi City TW for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Hsing-Chih Lin of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City TW for taiwan semiconductor manufacturing company, ltd., Wei-Tao Tsai of Tainan City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/3065, H01L21/761, H01L21/762, H01L21/768, H01L23/00, H01L23/522, H01L23/528, H01L23/60, H01L25/00, H01L25/065, H10D30/01, H10D30/65, H10D62/10, H10D89/60
CPC Code(s): H01L23/481
Abstract: various embodiments of the present application are directed towards an integrated circuit (ic) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (tsv). in some embodiments, the ic comprises a substrate, an interconnect structure, the semiconductor device, the tsv, and the shield structure. the interconnect structure is on a frontside of the substrate and comprises a wire. the semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. the tsv extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. the shield structure comprises a pn junction extending completely through the substrate and directly between the semiconductor device and the tsv.
Inventor(s): Chia-Yueh Chou of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Hsiang-Ku Shen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chen-Chiu Huang of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Yu-Bey Wu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L23/00, H01L25/065
CPC Code(s): H01L23/49838
Abstract: in an embodiment, a device includes: a plurality of redistribution lines over a semiconductor substrate, the redistribution lines including trace portions extending along the semiconductor substrate; a first passivation layer over the redistribution lines, the first passivation layer filling an entirety of an area between the trace portions of the redistribution lines; a passive device over the first passivation layer; a dielectric layer over the passive device; and a die connector extending through the dielectric layer, the die connector physically and electrically coupled to the passive device.
Inventor(s): Gary LIU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ting-Ya LO of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Shao-Kuan LEE of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Zi-Yi YANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chi-Lin TENG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Kuang-Wei YANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hsin-Yen HUANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang CHANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ming-Han LEE of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/02, H01L21/3105, H01L21/768, H01L23/528
CPC Code(s): H01L23/5226
Abstract: a method for manufacturing an interconnect structure includes: forming sacrificial portions and electrically conductive portions on a base structure such that the sacrificial portions are disposed to alternate with the electrically conductive portions in a first direction, and such that each of the sacrificial portions and the electrically conductive portions is elongated in a second direction transverse to the first direction; forming blocking portions respectively on the sacrificial portions; forming a sacrificial layer to cover the electrically conductive portions and the blocking portions; forming an electrically conductive via which extends through the sacrificial layer so as to permit the electrically conductive via to be electrically connected to one of the electrically conductive portions; after forming the electrically conductive via, performing a removal process to remove the sacrificial layer, the blocking portions and the sacrificial portions so as to form a cavity; and forming a dielectric portion to fill the cavity.
Inventor(s): Wei-Chen CHU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chia-Chen LEE of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chia-Tien WU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528
CPC Code(s): H01L23/5226
Abstract: an interconnection structure includes a semiconductor substrate that is formed with a first metal trench and a second metal trench, a first metal via, a second metal via, a third metal trench and a fourth metal trench. the first metal via is disposed over and connected to the first metal trench. the second metal via is disposed over and connected to the second metal trench. the third metal trench is disposed over and connected to the first metal via. the fourth metal trench that is disposed over and connected to the second metal via. a thickness of the third metal trench is different from a thickness of the fourth metal trench.
Inventor(s): Wei-Ren WANG of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Tze-Liang LEE of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Jen-Hung WANG of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/311, H01L21/768
CPC Code(s): H01L23/5226
Abstract: a semiconductor structure includes a first dielectric layer, a first conductive feature, a second conductive feature, a first etch stop layer, and a conductive via. the first conductive feature and the second conductive feature are embedded in the first dielectric layer. the first etch stop layer is disposed over the dielectric layer. the conductive via is surrounded by the first etch stop layer and electrically connected to the first conductive feature, in which the conductive via is in contact with a top surface of the first etch stop layer.
Inventor(s): Hao Kuang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Tung-Heng Hsieh of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Sheng-Hsiung Wang of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Bao-Ru Young of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Wang-Jung Hsueh of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Pang-Chi Wu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, G06F30/392, G06F30/3953, G06F30/398
CPC Code(s): H01L23/5226
Abstract: a device includes a semiconductor substrate, an active region over the semiconductor substrate extending lengthwise in a first direction, a gate structure over the active region extending lengthwise in a second direction perpendicular to the first direction, a source feature and a drain feature on the active region and interposed by the gate structure, a source contact on the source feature, a drain contact on the drain feature, and a via rail over the substrate spaced from the active region. the via rail includes a main portion extending lengthwise in the first direction having a sidewall surface facing opposite the end surface of the drain contact, and a jog via extending from the main portion along the second direction and having a sidewall surface facing the second direction, each of the main portion and the jog via contacting the source contact.
Inventor(s): Shih-Ming CHANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/768, H01L23/522, H01L23/535
CPC Code(s): H01L23/5283
Abstract: in a method of manufacturing a semiconductor device, a first conductive pattern is formed in a first interlayer dielectric (ild) layer disposed over a substrate, a second ild layer is formed over the first conductive pattern and the first ild layer, a via contact is formed in the second ild layer to contact an upper surface of the first conductive pattern, a second conductive pattern is formed over the via contact wherein a part of an upper surface of the via contact is exposed from the second conductive pattern in plan view, a part of the via contact is etched by using the second conductive pattern as an etching mask, thereby forming a space between the via contact and the second ild layer, and a third ild layer is formed over the second ild layer.
Inventor(s): Chen-Ming Lee of Taoyuan County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L29/06, H01L29/40, H01L29/417, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L23/5286
Abstract: a method includes providing a structure having a substrate, a fin-shape base protruding from the substrate, an isolation structure on sidewalls of the fin-shape base, and an epitaxial feature over the fin-shape base. the substrate is at the backside of the structure and the epitaxial feature is at the frontside of the structure. the method also includes recessing the substrate from the backside of the structure to expose a bottom surface of the isolation structure, forming a backside dielectric layer covering the isolation structure, depositing an etch stop layer on a bottom surface of the backside dielectric layer, forming an opening in the etch stop layer, wherein the opening exposes the fin-shape base from the backside of the structure, etching the fin-shape base from the opening to expose the epitaxial feature, and forming a backside conductive feature in the opening and in physical contact with the epitaxial feature.
Inventor(s): Meng-Han LIN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chia-En HUANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/535, H01L23/528, H10B51/20, H10B51/30
CPC Code(s): H01L23/535
Abstract: a semiconductor memory device includes first and second memory units, and first and second staircase vias. the first memory unit includes two first source/bit line portions separated from each other, a first word line surrounding the first source/bit line portions, a first memory film surrounding the first word line, and a first channel region between the first memory film and the first source/bit line portions. the second memory unit is disposed over the first memory unit, and includes two second source/bit line portions separated from each other, a second word line surrounding the second source/bit line portions, a second memory film surrounding the second word line, and a second channel region between the second memory film and the second source/bit line portions. the first and second staircase vias respectively penetrate the first and second memory films, and are respectively and electrically connected to the first and second word lines.
Inventor(s): Shin-Puu JENG of Po-Shan Village TW for taiwan semiconductor manufacturing company, ltd., Po-Yao LIN of Zhudong Township TW for taiwan semiconductor manufacturing company, ltd., Shuo-Mao CHEN of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Chia-Hsiang LIN of Zhubei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L21/683, H01L23/31, H01L23/538, H01L23/64
CPC Code(s): H01L23/562
Abstract: a package structure is provided. the package structure includes a reinforced plate and multiple conductive structures surrounded by the reinforced plate. the package structure also includes a redistribution structure over the reinforced plate. the redistribution structure has multiple polymer-containing layers and multiple conductive features, and the reinforced plate is thinner than the redistribution structure. a thickness ratio of a first thickness of the reinforced plate to a second thickness of the redistribution structure is greater than about 0.5. the package structure further includes one or more chip structures bonded to the redistribution structure.
Inventor(s): Yi-Shan Hsieh of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chen-Chiu Huang of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Yu-Bey Wu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hsiang-Ku Shen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/768, H01L23/522, H01L23/528
CPC Code(s): H01L24/08
Abstract: in an embodiment, a method includes forming active devices over a semiconductor substrate; forming an interconnect structure over the semiconductor substrate, the interconnect structure comprising a contact pad embedded in a dielectric layer; forming a first passivation layer over the interconnect structure; forming a first opening through the first passivation layer to expose the contact pad; depositing a seed layer over the first passivation layer and in the first opening; forming a sacrificial material over the seed layer; patterning the sacrificial material to reform the first opening and to form a second opening; depositing conductive material to form a first redistribution line in the first opening and a second redistribution line in the second opening; removing the sacrificial material; and attaching an integrated circuit die to the first redistribution line and the second redistribution line.
Inventor(s): Ming-Da Cheng of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Yung-Ching Chao of Gukeng Township TW for taiwan semiconductor manufacturing company, ltd., Chun Kai Tzeng of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Cheng Jen Lin of Kaohsiung City TW for taiwan semiconductor manufacturing company, ltd., Chin Wei Kang of Tainan TW for taiwan semiconductor manufacturing company, ltd., Yu-Feng Chen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Mirng-Ji Lii of Sinpu Township TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/31, H01L23/488, H01L23/522
CPC Code(s): H01L24/11
Abstract: a method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. the polymer layer is substantially free from n-methyl-2-pyrrolidone (nmp), and comprises aliphatic amide as a solvent. the method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.
Inventor(s): Yao-Jen Chang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chung-Yu Lu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ping-Kang Huang of Chiayi City TW for taiwan semiconductor manufacturing company, ltd., Sao-Ling Chiu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hsien-Pin Hu of Zhubei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/498, H01L25/065
CPC Code(s): H01L24/13
Abstract: a method includes forming a first conductive pillar on an interposer; forming a second conductive pillar on the interposer, wherein the second conductive pillar includes a barrier layer; bonding a first semiconductor device to the first conductive pillar by a first bonding region that includes more inter-metallic compound than solder; and bonding the first semiconductor device to the second conductive pillar by a second bonding region that includes more solder than inter-metallic compound.
Inventor(s): Zi-Jheng Liu of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/538, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H01L24/20
Abstract: a semiconductor package and a method of forming the same are provided. the semiconductor package includes a first die, a second die and a redistribution layer structure. the first die and the second die are disposed laterally. the redistribution layer structure is disposed over and electrically connected to the first die and the second die. the redistribution layer structure includes a plurality of vias and a plurality of lines stacked alternately and electrically connected to each other and embedded by a plurality of polymer layers. the redistribution layer structure further includes a first pad overlapped with the first die and a second pad overlapped with the second die. the first pad, the second pad and lines closest to the first die and the second die are located at substantially the same level, and from a top view, the first pad and the second pad have different shapes.
Inventor(s): Chao-Wei Chiu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hsiu-Jen Lin of Zhubei City TW for taiwan semiconductor manufacturing company, ltd., Hsuan-Ting Kuo of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/52, H01L23/053, H01L23/28
CPC Code(s): H01L24/32
Abstract: a semiconductor package and the method of forming the same are provided. the semiconductor package may include a substrate, a semiconductor package component having a semiconductor die bonded to the substrate, a lid attached to the substrate, and a first composite metal feature between the semiconductor package component and the lid. the first composite metal feature may include a first metal feature having a first material and a second metal feature having a second material. the first material may be an intermetallic compound. the second material may be different from the first material.
Inventor(s): Ming-Tsu Chung of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Yung-Chi Lin of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Yan-Zuo Tsai of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Yang-Chih Hsueh of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/74
Abstract: a bonding tool for bonding semiconductor dies to a semiconductor wafer is provided. the bonding tool includes a wafer chuck, an edge support, a hard plate, and a buffer layer. the wafer chuck carries the semiconductor wafer and the semiconductor dies placed on the semiconductor wafer. the edge support is disposed on the wafer chuck, the semiconductor wafer and the semiconductor dies are laterally surrounded by the edge support, and a top surface of the edge support substantially levels with surfaces of the semiconductor dies. the hard plate is movably disposed over the semiconductor dies, the edge support and the wafer chuck. the buffer layer is disposed on a bottom surface of the hard plate, and the buffer layer is in contact with the top surface of the edge support and the semiconductor dies when the hard plate moves towards the edge support.
Inventor(s): Hsien-Wei Chen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ying-Ju Chen of Tuku Township TW for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/304, H01L21/683, H01L21/768, H01L23/48, H01L23/544, H01L25/00, H01L25/065
CPC Code(s): H01L24/80
Abstract: a method includes placing a first package component. the first package component includes a first alignment mark and a first dummy alignment mark. a second package component is aligned to the first package component. the second package component includes a second alignment mark and a second dummy alignment mark. the aligning is performed using the first alignment mark for positioning the first package component, and using the second alignment mark for position the second package component. the second package component is bonded to the first package component to form a package, with the first alignment mark being bonded to the second dummy alignment mark.
Inventor(s): Min-Feng Kao of Chiayi City TW for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Hsing-Chih Lin of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City TW for taiwan semiconductor manufacturing company, ltd., Yi-Shin Chu of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Ping-Tzu Chen of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Che-Wei Chen of Kaohsiung City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/768, H01L23/00, H01L23/48, H01L23/532
CPC Code(s): H01L25/0657
Abstract: in some embodiments, the present disclosure relates to a 3d integrated circuit (ic) stack that includes a first ic die bonded to a second ic die. the first ic die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. the second ic die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. the first bonding structure faces the second bonding structure. further, the 3d ic stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.
Inventor(s): Yu-Hua HSIEH of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ying-Yen TSENG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Wen-Yu KU of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Kei-Wei CHEN of Tainan City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01S3/082, G01B11/30, H01S3/108
CPC Code(s): H01S3/082
Abstract: some implementations described herein provide a laser device. the laser device includes a first portion of the laser device, at a proximal end of the laser device, that includes one or more optical devices, where the first portion is configured to emit first electromagnetic waves having a first wavelength. the laser device includes a second portion of the laser device, at a distal end of the laser device, that includes an optical crystal configured to receive the first electromagnetic waves and to emit second electromagnetic waves having a second wavelength based on reception of the first electromagnetic waves, where the optical crystal includes a thin film coating disposed on an end of the optical crystal, the thin film coating configured to: support emission of the second electromagnetic waves from the optical crystal, and support internal reflection of the first electromagnetic waves within the optical crystal.
Inventor(s): Jing DING of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Zhang-Ying YAN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Qingchao MENG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Lei PAN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K3/037, G06F30/392, H03K19/0185
CPC Code(s): H03K3/037
Abstract: an integrated circuit includes a first region including a first set of transistors that include a first set of active regions having a first threshold voltage, the first set of transistors in a first portion of a level shifter circuit, the first portion of the level shifter circuit being coupled to a first voltage supply. the integrated circuit further includes a second region adjacent to the first region. the second region includes a second set of transistors that include a second set of active regions having a second threshold voltage different from the first threshold voltage, and the second set of transistors being in a second portion of the level shifter circuit.
Inventor(s): Shao-Te WU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chia-Jung CHANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Shih-Peng CHANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K17/687, G06F30/392, H03K19/0175
CPC Code(s): H03K17/6872
Abstract: an input/output (i/o) system includes an output level shifter coupled between an output node of a core circuit and a first node; an output driver coupled between the first node and an external terminal of the i/o system; and a gating signal generator configured to enable the output driver after an output signal of the output level shifter has stabilized.
Inventor(s): WeiShuo Lin of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03L7/07, H03L7/081, H03L7/095
CPC Code(s): H03L7/07
Abstract: a duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. the dc corrector circuit includes a delay-locked loop (dll) circuit and a duty-cycle correction (dcc) circuit. the dll circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. the dcc circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. the duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.
Inventor(s): Yong-Sheng Huang of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Ming Chyi Liu of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B43/30, H10B41/30, H10D62/10, H10D62/13
CPC Code(s): H10B43/30
Abstract: the present disclosure relates to an integrated chip comprising a substrate comprising a pair of sidewalls defining a first trench. a first gate structure is in the first trench and comprises a first conductive structure, a first dielectric structure between the first conductive structure and the substrate, a second conductive structure, and a second dielectric structure between the second conductive structure and the substrate. the first conductive structure and the second conductive structure are spaced laterally apart from one another between the pair of sidewalls.
Inventor(s): Sai-Hooi Yeong of Zhubei TW for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chenchen Jacob Wang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B53/40, H10B53/30, H10D1/68
CPC Code(s): H10B53/40
Abstract: a semiconductor device includes: a substrate; a first dielectric layer over the substrate; a memory cell over the substrate in a first region of the semiconductor device, where the memory cell includes a first ferroelectric structure in the first dielectric layer, where the first ferroelectric structure includes a first bottom electrode, a first top electrode, and a first ferroelectric layer in between; and a tunable capacitor over the substrate in a second region of the semiconductor device, where the tunable capacitor includes a second ferroelectric structure, where the second ferroelectric structure includes a second bottom electrode, a second top electrode, and a second ferroelectric layer in between, where at least a portion of the second ferroelectric structure is in the first dielectric layer.
Inventor(s): Ku-Feng Lin of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Ji-Kuan Lee of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Wen-Chun You of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Perng-Fei Yuh of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Yi-Chun Shih of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Yih Wang of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B63/00, H10B53/30
CPC Code(s): H10B63/80
Abstract: a memory device includes a memory array comprising a plurality of memory cells arranged over a plurality of rows, the rows including a plurality of word lines, respectively, a first group of the memory cells coupled to an even-numbered one of the word lines and a second group of the memory cells coupled to an odd-numbered one of the word lines. the even-numbered word line is disposed in a first one of a plurality of metallization layers formed vertically above a substrate, wherein the even-numbered word line extends along a first lateral direction and includes a first stitch portion extending in a second lateral direction perpendicular to the first lateral direction. the odd-numbered word line is disposed in a second one of the plurality of metallization layers, wherein the odd-numbered word line extends along the first lateral direction and includes a second stitch portion extending in the second lateral direction.
Inventor(s): Wei Ju Lee of Kaohsiung City TW for taiwan semiconductor manufacturing company, ltd., Zhiqiang Wu of Chubei TW for taiwan semiconductor manufacturing company, ltd., Chung-Wei Wu of Ju-Bei City TW for taiwan semiconductor manufacturing company, ltd., Chun-Fu Cheng of Zhubei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D30/01, H01L21/02, H10D30/62, H10D30/67, H10D62/00, H10D62/10, H10D62/13, H10D64/01, H10D84/01, H10D84/03, H10D84/83
CPC Code(s): H10D30/024
Abstract: the present disclosure provides a semiconductor device that includes channel layers vertically stacked over a substrate, a gate structure engaging the channel layers, a source/drain (s/d) formation assistance region partially embedded in the substrate and under a bottommost one of the channel layers, and an s/d epitaxial feature interfacing both the s/d formation assistance region and lateral ends of the channel layers. the s/d formation assistance region includes a semiconductor seed layer embedded in an isolation layer. the isolation layer separates the semiconductor seed layer from physically contacting the substrate.
Inventor(s): Chao-Ching CHENG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Wei-Sheng YUN of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Shao-Ming YU of Zhubei City TW for taiwan semiconductor manufacturing company, ltd., Tsung-Lin LEE of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chih-Chieh YEH of Taipei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D30/01, B82Y10/00, H01L21/762, H10D30/43, H10D30/63, H10D30/67, H10D30/69, H10D62/10, H10D62/13, H10D62/822, H10D64/01, H10D64/23, H10D64/27, H10D84/01, H10D84/03, H10D84/85, H10D88/00
CPC Code(s): H10D30/025
Abstract: structures and formation methods of a semiconductor device structure are provided. the semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. the semiconductor device structure includes a source/drain (s/d) portion adjacent to the gate electrode, and an interlayer dielectric layer adjacent formed over the source/drain portion. the semiconductor device structure includes an etch stop layer adjacent between the source/drain portion and the interlayer dielectric layer, and a protective element adjacent formed over the interlayer dielectric layer.
Inventor(s): Yu-Lien Huang of Jhubei TW for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chi-Hao Chang of Taoyuan TW for taiwan semiconductor manufacturing company, ltd., Jr-Hung Li of Chupei TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D30/62, H10D30/01, H10D30/67, H10D62/10, H10D64/01
CPC Code(s): H10D30/6211
Abstract: a method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.
Inventor(s): Jhon-Jhy LIAW of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L27/092, H01L29/06, H01L29/417, H01L29/423, H01L29/775
CPC Code(s): H10D30/6715
Abstract: a semiconductor structure is provided. the semiconductor structure includes a substrate, a well, a plurality of channel sheets, a source/drain region, a contact, a gate electrode, a gate dielectric layer and a spacer. the gate electrode includes at least one inner gate electrode and a top gate electrode. the inner gate electrode is located between the plurality of channel sheets. the top gate electrode is located upon a top of the plurality of channel sheets. the top gate electrode includes a first stage top gate and a second stage top gate. the first stage top gate is stacked on the second stage top gate, and a first gate length of the first stage top gate is less than a second gate length of the second stage top gate. the gate dielectric layer surrounds the gate electrode. the spacer includes at least one inner spacer and a top spacer.
Inventor(s): Guan-Lin CHEN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Pei-Yu WANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hsien-Chih HUANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chia-Hao YU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L27/088, H01L29/06, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D30/6735
Abstract: a method for forming transistors includes forming a stack of alternating first semiconductor layers and second semiconductor layers on a substrate and forming nanostructure channels and interposers by forming a source/drain opening in a first device region of the substrate. the source/drain opening extending through the first and second semiconductor layers. the method includes, after the forming a source/drain opening, increasing tensile strain of the nanostructure channels, and, after the increasing tensile strain, forming a source/drain in the source/drain opening.
Inventor(s): Jung-Chien Cheng of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Chia-Hao Chang of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Baoshan Township TW for taiwan semiconductor manufacturing company, ltd., Guan-Lin Chen of Baoshan Township TW for taiwan semiconductor manufacturing company, ltd., Shi Ning Ju of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Jia-Chuan You of Dayuan Township TW for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Zhubei City TW for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsin-Chu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D30/67, H10D30/01, H10D62/10, H10D64/01, H10D84/01, H10D84/03
CPC Code(s): H10D30/6735
Abstract: a semiconductor device includes first channel members, a first gate structure wrapping around each of the first channel members, a first epitaxial feature abutting the first channel members, second channel members, a second gate structure wrapping around each of the second channel members, a second epitaxial feature abutting the second channel members, and an isolation feature has a first portion laterally stacked between the first and second gate structures and a second portion laterally stacked between the first and second epitaxial features. a width of the first portion of the isolation feature is larger than a width of the second portion of the isolation feature.
Inventor(s): An-Hung TAI of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Jian-Hao CHEN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Hui-Chi CHEN of Zhudong Township TW for taiwan semiconductor manufacturing company, ltd., Kuo-Feng YU of Zhudong Township TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D30/67, H10D62/10, H10D64/01, H10D64/23
CPC Code(s): H10D30/6735
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a substrate. the semiconductor device structure includes a gate stack over the substrate. the semiconductor device structure includes a cap layer over the gate stack. the semiconductor device structure includes a protective layer over the cap layer. a lower portion of the protective layer extends into the cap layer. the semiconductor device structure includes a contact structure passing through the protective layer and the cap layer.
Inventor(s): Yu-Shiang HUANG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Cheng-Yi PENG of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Yen-Ting CHEN of Taichung City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H10D30/6757
Abstract: the present disclosure describes a semiconductor device having a channel extension structure. the semiconductor device includes a channel structure on a substrate. the channel structure includes a central portion and an end portion. the semiconductor device further includes a gate structure wrapped around the central portion of the channel structure, a source/drain (s/d) structure on the substrate and adjacent to the end portion of the channel structure, and an extension structure between the channel structure and the s/d structure. the extension structure has a first sidewall having a first height and adjacent to the end portion of the channel structure and a second sidewall having a second height and adjacent to the s/d structure greater than the first height.
Inventor(s): I-Sheng Chen of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Chao-Ching Cheng of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Tzu-Chiang Chen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Carlos H. Diaz of Mountain View CA US for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D30/67, H10D30/01, H10D62/10, H10D64/01, H10D84/85
CPC Code(s): H10D30/6757
Abstract: a nanowire fet device includes a vertical stack of nanowire strips configured as the semiconductor body. one or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.
Inventor(s): Matthias PASSLACK of Hayward CA US for taiwan semiconductor manufacturing company, ltd., Marcus Johannes Henricus VAN DAL of Linden BE for taiwan semiconductor manufacturing company, ltd., Timothy VASEN of Tervuren BE for taiwan semiconductor manufacturing company, ltd., Georgios VELLIANITIS of Heverlee BE for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D62/10, H01L21/02, H10D30/01, H10D30/62, H10D62/13, H10D64/01
CPC Code(s): H10D62/121
Abstract: in a method of forming a gate-all-around field effect transistor (gaa fet), a fin structure is formed. the fin structure includes a plurality of stacked structures each comprising a dielectric layer, a cnt over the dielectric layer, a support layer over the cnt. a sacrificial gate structure is formed over the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source/drain opening, and a source/drain contact layer is formed in the source/drain opening. the source/drain contact is formed such that the source/drain contact is in direct contact with only a part of the cnt and a part of the dielectric layer is disposed between the source/drain contact and the cnt.
Inventor(s): Chao-Hsin Wu of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Yu Ting Chao of Kaohsiung City TW for taiwan semiconductor manufacturing company, ltd., Yu-Hsuan Lu of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Ying-Chuan Chen of Tainan City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/18, H01L21/02
CPC Code(s): H10D62/84
Abstract: a method of forming a semiconductor device includes the following steps. a 2d material layer is formed over a bottom metal layer. a top metal layer is formed over the 2d material layer. an oxidation treatment is performed to the 2d material layer to form an oxide region interfacing both the 2d material layer and the top metal layer.
Inventor(s): Ding-Kang SHIH of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66
CPC Code(s): H10D64/017
Abstract: a manufacturing method includes the following steps: forming a semiconductor structure, wherein the semiconductor structure comprises a wafer, a plurality of dummy gates and a dielectric layer, and the dummy gates are formed on the wafer, and the dielectric layer is formed on the dummy gates; forming an epitaxy layer between adjacent two of the dummy gates, wherein there is a nodule remained on the dielectric layer in process of forming the epitaxy layer; and removing the nodule by using an ultrashort laser beam.
Inventor(s): Bo-Yu Lai of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Chung-I Yang of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Wei-Yang Lee of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Chih-Ching Wang of Kinmen County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/08, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D64/017
Abstract: semiconductor structures and methods for forming the same are provided. a semiconductor structure according to the present disclosure includes a substrate, a first base fin and a second base fin rising from the substrate, an isolation feature disposed over the substrate and between the first base fin and the second base fin, a first bottom epitaxial feature over the first base fin, a second bottom epitaxial feature over the second base fin, an isolation layer on the first bottom epitaxial feature, a first source/drain feature over the isolation layer, a second source/drain feature disposed over and in contact with the second bottom epitaxial feature, a contact etch stop layer (cesl) over the first source/drain feature and the isolation feature, a first interlayer dielectric (ild) layer over the cesl, and a second ild layer over and in direct contact with the second source/drain feature.
Inventor(s): Zheng Hui LIM of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ji-Yin TSAI of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ming-Hua YU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chii-Horng LI of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/08, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D64/017
Abstract: method for forming semiconductor device structure includes forming a sacrificial layer between first and second stacks of layers, the first stack of layers comprises first and second semiconductor layers alternatingly stacked, and the second stack of layers comprises third and fourth semiconductor layers alternatingly stacked, wherein the sacrificial layer comprises a semiconductor metal oxide, forming a sacrificial gate structure over portion of the second stack of layers, removing portions of the first and second stack of layers not covered by the sacrificial gate structure, removing the sacrificial layer to form cavity, filling the cavity with a dielectric to form an isolation layer, and forming first and second source/drain features on opposing sides of sacrificial gate structure, wherein the first source/drain feature is disposed below the second source/drain feature, and the first and second source/drain features are in contact with the isolation layer, first semiconductor layers, and third semiconductor layers.
Inventor(s): Yi-Ruei JHAN of Keelung City TW for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Zhubei City TW for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D64/01, H10D30/01, H10D30/67, H10D62/10, H10D62/13, H10D64/23, H10D84/83
CPC Code(s): H10D64/017
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. the semiconductor device structure includes a first gate structure surrounding the first nanostructures. the semiconductor device structure also includes a first gate spacer layer formed adjacent to the first gate structure. a topmost first nanostructure has a first portion below the gate spacer layer and a second portion below the first gate structure, and the first portion has a first height along the vertical direction, the second portion has a second height along the vertical direction, and the first height is greater than the second height.
Inventor(s): Kai-Chieh Yang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chun-Yu Liu of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Wei-Yen Woon of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Ku-Feng Yang of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/49, H01L21/288, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D64/667
Abstract: semiconductor structures and method of forming the same are provided. a method according to the present disclosure includes providing an intermediate structure that includes an opening, conformally depositing a metal liner over the opening, depositing a dummy fill material over the metal liner, recessing the dummy fill material such that a portion of the metal liner is exposed, removing the exposed portion of the metal liner, removing the recessed dummy fill material, and after the removing of the recessed dummy fill material, depositing a metal fill layer over the opening.
Inventor(s): Wei-Liang LU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chang-Yin CHEN of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Chih-Han LIN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chia-Yang LIAO of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D64/66, H10D30/01, H10D30/62, H10D62/00, H10D62/13, H10D64/01, H10D84/01, H10D84/03, H10D84/83
CPC Code(s): H10D64/671
Abstract: a semiconductor device and methods of fabricating the same are disclosed. the semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (s/d) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the s/d region. the first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. the second spacer portion extends below the fin top surface and is disposed along a sidewall of the s/d region.
Inventor(s): Gerben Doornbos of Kessel-Lo BE for taiwan semiconductor manufacturing company, ltd., Marcus Johannes Henricus van Dal of Linden BE for taiwan semiconductor manufacturing company, ltd., Georgios Vellianitis of Heverlee BE for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D64/68, H10B51/30, H10D30/01, H10D30/62, H10D30/67, H10D62/40, H10D62/854
CPC Code(s): H10D64/689
Abstract: semiconductor devices and methods of forming the same are provided. a semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. the ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. the ferroelectric structure is doped with a dopant.
Inventor(s): Yun Ju FAN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Lo-Heng CHANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Huan-Chieh SU of Tianzhong Township TW for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/45, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D84/038
Abstract: techniques described herein include forming respective (different) types of metal silicide layers for p-type source/drain regions and n-type source/drain regions of nanostructure transistors of a semiconductor device in a selective manner that reduces process complexity. for example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) of a first nanostructure transistor, and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective) of a second nanostructure transistor. this provides a low schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. this reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.
Inventor(s): Chun Yi CHOU of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Guan-Lin CHEN of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Shi Ning JU of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088
CPC Code(s): H10D84/038
Abstract: a method includes forming first semiconductive sheets over a substrate and arranged in a vertical direction, and second semiconductive sheets over the substrate and arranged in the vertical direction, wherein a number of the second semiconductive sheets is different than a number of the first semiconductive sheets; forming first source/drain regions on either side of each of the first semiconductive sheets, and second source/drain regions on either side of each of the second semiconductive sheets; forming a first gate around each of the first semiconductive sheets, and a second gate around each of the second semiconductive sheets.
Inventor(s): Chen-Hsiang HUNG of Hsin-Chu TW for taiwan semiconductor manufacturing company, ltd., Li-Hsin CHU of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Chia-Ping LAI of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chung-Chuan TSENG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D84/00, H01L23/532, H10D1/47, H10D1/68, H10D86/85
CPC Code(s): H10D84/206
Abstract: a method of making a semiconductor device, includes: providing a first dielectric layer; sequentially forming a first metal layer, a dummy capacitor dielectric layer, and a second metal layer over the first dielectric layer; and using a single mask layer with two patterns to simultaneously recess two portions of the second metal layer so as to define a metal thin film of a resistor and a top metal plate of a capacitor.
Inventor(s): Yu-Hung LIN of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Wei Hsin LIN of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Hui-Hsuan KUNG of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Yi-Lii HUANG of Zhubei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234
CPC Code(s): H10D84/834
Abstract: the present disclosure describes a semiconductor device having fin structures with optimized fin pitches for substantially uniform s/d structures. the semiconductor device includes multiple fin structures on a substrate. the multiple fin structures have a first pitch and a second pitch in an alternate configuration and the second pitch is different from the first pitch. the semiconductor device further includes a gate structure on the multiple fin structures and a source/drain (s/d) structure adjacent to the gate structure and in contact with the multiple fin structures.
Inventor(s): Yi-Chen HO of Taichung TW for taiwan semiconductor manufacturing company, ltd., Hung Chih HU of Taichung TW for taiwan semiconductor manufacturing company, ltd., Hung Cheng YU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ju Ru HSIEH of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D84/83, H10D30/01, H10D30/62, H10D62/10, H10D64/01, H10D84/01, H10D84/03
CPC Code(s): H10D84/834
Abstract: a semiconductor device including fin field-effect transistors, includes a first gate structure extending in a first direction, a second gate structure extending the first direction and aligned with the first gate structure in the first direction, a third gate structure extending in the first direction and arranged in parallel with the first gate structure in a second direction crossing the first direction, a fourth gate structure extending the first direction, aligned with the third gate structure and arranged in parallel with the second gate structure, an interlayer dielectric layer disposed between the first to fourth gate electrodes, and a separation wall made of different material than the interlayer dielectric layer and disposed between the first and third gate structures and the second and fourth gate structures.
Inventor(s): Cheng-Ming Lin of Kaohsiung City TW for taiwan semiconductor manufacturing company, ltd., Tsung-Kai Chiu of Zhubei City TW for taiwan semiconductor manufacturing company, ltd., Wei-Yen Woon of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Zhubei TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/822, H01L21/8238, H01L29/06, H01L29/423, H01L29/51, H01L29/66, H01L29/775
CPC Code(s): H10D84/856
Abstract: a method includes forming a first semiconductor channel region and a second semiconductor channel region, wherein the second semiconductor channel region overlaps the first semiconductor channel region, forming a first gate dielectric on the first semiconductor channel region, and forming a second gate dielectric on the second semiconductor channel region. a first dipole film and a second dipole film are formed on the first gate dielectric and the second gate dielectric, respectively. the dipole dopants in the first dipole film and the second dipole film are driven into the first gate dielectric and the second gate dielectric, respectively. the first dipole film and the second dipole film are then removed. a gate electrode is formed on both of the first gate dielectric and the second gate dielectric to form first transistor and a second transistor, respectively.
Inventor(s): Ching-Yu HUANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Wei-Cheng TZENG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Wei-Cheng LIN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chia-Tien WU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ken-Hsien HSIEH of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/12, H01L27/06, H01L27/118
CPC Code(s): H10D86/0221
Abstract: a device includes first to third power/ground (pg) elements; a first set of at least three tracks between the first and second pg elements and a second set of at least three tracks between the second and third pg elements, the tracks being arranged in equal numbers between the first and second pg and second and third pg elements; a first row of cells overlapping the first set; and a second row of cells overlapping the second set. in the first row of cells, a first cell has a first height and a second cell has a greater height than the first height; in the second row of cells, a third cell has the first height and a fourth cell has a lesser height less than the first height; and a track configured as an in-cell pg track is aligned with a boundary of the second and fourth cells.
Inventor(s): Cheng-Ying HO of Chiayi County TW for taiwan semiconductor manufacturing company, ltd., Kai-Chun HSU of Yonghe City TW for taiwan semiconductor manufacturing company, ltd., Wen-De WANG of Chiayi County TW for taiwan semiconductor manufacturing company, ltd., Yuh HUANG of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Cheng-Yu HSIEH of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Hung-Yu WANG of Keelung City TW for taiwan semiconductor manufacturing company, ltd., Jen-Cheng LIU of Hsin-Chu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H10F39/8053
Abstract: a pixel array that includes some pixels with high absorption (ha) structures and other pixels without ha structures exhibits increased dynamic range for near infrared (nir) light. additionally, the pixel array is a uniform array of photodiodes and thus does not exhibit current leakage that would have been caused by irregular isolation structures. additionally, the pixel array may further a lateral overflow integration capacitor to further increase the dynamic range for nir light.
Inventor(s): Hsiang-Ku SHEN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Dian-Hau CHEN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/10, G11C11/16, H01F10/32, H10B61/00, H10N50/01, H10N50/80, H10N50/85
CPC Code(s): H10N50/10
Abstract: methods and devices are provided that include a magnetic tunneling junction (mtj) element. a first spacer layer abuts sidewalls of the mtj element. the first spacer layer has a low-dielectric constant (low-k) oxide composition. a second spacer layer is disposed on the first spacer layer and has a low-k nitride composition.
Inventor(s): Bi-Shen Lee of Hsin-Chu TW for taiwan semiconductor manufacturing company, ltd., Hai-Dang Trinh of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Fa-Shen Jiang of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Hsun-Chung Kuang of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/00, G11C13/00
CPC Code(s): H10N70/8265
Abstract: various embodiments of the present disclosure are directed towards an integrated chip comprising a first electrode overlying a substrate. a first data storage layer overlies the first electrode. the first data storage layer comprises a metal oxide. the metal oxide comprises a first metal, a second metal, and a nonmetal. the first metal is different from the second metal. an atomic percentage of the nonmetal is less than an atomic percentage of the second metal. a second electrode overlies the first data storage layer.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on May 8th, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- G02B6/42
- H01L23/00
- H01L25/16
- CPC G02B6/4214
- Taiwan semiconductor manufacturing company, ltd.
- G03F1/22
- G03F1/24
- G03F1/38
- G03F1/54
- CPC G03F1/22
- G03F1/82
- CPC G03F1/82
- G03F7/004
- C23C16/455
- C23C16/56
- G03F7/16
- G03F7/20
- G03F7/38
- H01L21/027
- CPC G03F7/0042
- G03F7/40
- G03F7/00
- G03F7/30
- G03F7/32
- CPC G03F7/40
- H01L21/66
- CPC G03F7/70633
- CPC G03F7/70641
- H05G2/00
- CPC G03F7/70916
- G06F30/392
- G06F30/398
- CPC G06F30/392
- G11C5/14
- H03K3/012
- H03K3/037
- H03K19/0175
- H03K19/20
- CPC G11C5/147
- G11C7/10
- G11C5/06
- G11C8/08
- G11C17/16
- G11C17/18
- H01L23/522
- H01L23/525
- H10B20/25
- CPC G11C7/1096
- G11C16/08
- G11C16/26
- G11C16/32
- CPC G11C16/08
- H01J37/32
- C23C16/40
- C23C28/04
- CPC H01J37/32495
- H01L29/423
- H01L21/8234
- H01L27/088
- H01L29/06
- H01L29/66
- H01L29/775
- H01L29/786
- CPC H01L21/02
- H01L21/3213
- CPC H01L21/32137
- H01L21/48
- H01L23/373
- H01L25/00
- H01L25/065
- CPC H01L21/4807
- H01L21/762
- H01L21/67
- H10D30/01
- H10D30/67
- H10D62/10
- H10D64/01
- H10D86/00
- CPC H01L21/76251
- H01L21/764
- CPC H01L21/764
- H01L21/768
- C23C18/38
- H01L21/285
- H01L21/288
- CPC H01L21/76877
- H01L21/78
- H01L23/544
- CPC H01L21/78
- G06T7/00
- H10N50/01
- CPC H01L22/12
- H10D64/27
- H10D84/01
- H10D84/03
- CPC H01L22/20
- H01L21/56
- H01L23/31
- H01L23/498
- H01L23/538
- CPC H01L23/3736
- H01L23/48
- H01L21/3065
- H01L21/761
- H01L23/528
- H01L23/60
- H10D30/65
- H10D89/60
- CPC H01L23/481
- CPC H01L23/49838
- H01L21/02
- H01L21/3105
- CPC H01L23/5226
- H01L21/311
- G06F30/3953
- H01L23/535
- CPC H01L23/5283
- H01L29/40
- H01L29/417
- CPC H01L23/5286
- H10B51/20
- H10B51/30
- CPC H01L23/535
- H01L21/683
- H01L23/64
- CPC H01L23/562
- CPC H01L24/08
- H01L23/488
- CPC H01L24/11
- CPC H01L24/13
- H01L25/18
- CPC H01L24/20
- H01L21/52
- H01L23/053
- H01L23/28
- CPC H01L24/32
- CPC H01L24/74
- H01L21/304
- CPC H01L24/80
- H01L23/532
- CPC H01L25/0657
- H01S3/082
- G01B11/30
- H01S3/108
- CPC H01S3/082
- H03K19/0185
- CPC H03K3/037
- H03K17/687
- CPC H03K17/6872
- H03L7/07
- H03L7/081
- H03L7/095
- CPC H03L7/07
- H10B43/30
- H10B41/30
- H10D62/13
- CPC H10B43/30
- H10B53/40
- H10B53/30
- H10D1/68
- CPC H10B53/40
- H10B63/00
- CPC H10B63/80
- H10D30/62
- H10D62/00
- H10D84/83
- CPC H10D30/024
- B82Y10/00
- H10D30/43
- H10D30/63
- H10D30/69
- H10D62/822
- H10D64/23
- H10D84/85
- H10D88/00
- CPC H10D30/025
- CPC H10D30/6211
- H01L27/092
- CPC H10D30/6715
- CPC H10D30/6735
- CPC H10D30/6757
- CPC H10D62/121
- H01L29/18
- CPC H10D62/84
- CPC H10D64/017
- H01L29/08
- H01L29/49
- CPC H10D64/667
- H10D64/66
- CPC H10D64/671
- H10D64/68
- H10D62/40
- H10D62/854
- CPC H10D64/689
- H01L21/8238
- H01L29/45
- CPC H10D84/038
- H10D84/00
- H10D1/47
- H10D86/85
- CPC H10D84/206
- CPC H10D84/834
- H01L21/822
- H01L29/51
- CPC H10D84/856
- H01L27/12
- H01L27/06
- H01L27/118
- CPC H10D86/0221
- H01L27/146
- CPC H10F39/8053
- H10N50/10
- G11C11/16
- H01F10/32
- H10B61/00
- H10N50/80
- H10N50/85
- CPC H10N50/10
- H10N70/00
- G11C13/00
- CPC H10N70/8265