Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on May 1st, 2025
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on May 1st, 2025
Taiwan Semiconductor Manufacturing Company, Ltd.: 77 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L21/768 (17), H01L23/00 (17), H01L23/522 (14), H01L23/528 (12), H01L29/66 (11) H01L23/5226 (3), H10D62/121 (3), H10D84/038 (3), H10N50/01 (2), H01L24/05 (2)
With keywords such as: layer, structure, semiconductor, dielectric, device, gate, conductive, forming, substrate, and portion in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Yi-Lin WANG of Kaohsiung TW for taiwan semiconductor manufacturing company, ltd., Chin-Szu LEE of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Hua-Sheng CHIU of Zhudong Town TW for taiwan semiconductor manufacturing company, ltd., Yi-Chao CHANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Zih-Shou MUE of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): C23C14/34, B08B7/00, B08B17/04, C23C14/50, H01J37/32, H01J37/34
CPC Code(s): C23C14/34
Abstract: some implementations described herein provide a shutter disc for use during a conditioning process within a processing chamber of a deposition tool. the shutter disc described herein includes a material having a wave-shaped section to reduce heat transfer to the shutter disc and to provide relief from thermal stresses. furthermore, the shutter disc includes a deposition of a thin-film material on a backside of the shutter disc, where a diameter of the shutter disc causes a spacing between an inner edge of the thin-film material and an outer edge of a substrate support component. the spacing prevents an accumulation of material between the thin film material and the substrate support component, reduces tilting of the shutter disc due to a placement error, and reduces heat transfer to the shutter disc.
Inventor(s): Feng-Wei KUO of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Lan-Chou CHO of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Huan-Neng CHEN of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Chewn-Pu JOU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): E04B1/84, B32B9/00, C01F11/46, E04B1/86, E04B2/74, E04C2/04, E04C2/288, G10K11/168
CPC Code(s): E04B1/8409
Abstract: disclosed is a system and method for communication using an efficient fiber-to-chip grating coupler with a high coupling efficiency. in one embodiment, a method for communication, includes: transmitting optical signals between a semiconductor photonic die on a substrate and an optical fiber array attached to the substrate using at least one corresponding grating coupler on the semiconductor photonic die, wherein the at least one grating coupler each comprises a plurality of coupling gratings, a waveguide, a cladding layer, a first reflection layer and a second reflection layer, wherein the plurality of coupling gratings each comprises at least one step in a first lateral direction and extends in a second lateral direction, wherein the first and second lateral directions are parallel to a surface of the substrate and perpendicular to each other in a grating plane, wherein the first reflection layers are configured such that the plurality of coupling gratings is disposed between the first reflection layer and the cladding layer, wherein the second reflection layer are configured such that the cladding layer is disposed between the second reflection layer and the waveguide.
Inventor(s): Yi-An Lai of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Chan-Hong Chern of Palo Alto CA US for taiwan semiconductor manufacturing company, ltd., Cheng-Hsiang Hsieh of Taipei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01R31/28, H01L21/02
CPC Code(s): G01R31/2853
Abstract: an integrated circuit includes a first circuit, formed based on one or more group iii-v compound materials, that is configured to operate with a first voltage range. the integrated circuit includes a second circuit, also formed based on the one or more group iii-v compound materials, that is operatively coupled to the first circuit and configured to operate with a second voltage range, wherein the second voltage range is substantially higher than the first voltage range. the integrated circuit includes a set of first test terminals connected to the first circuit. the integrated circuit includes a set of second test terminals connected to the second circuit. test signals applied to the set of first test terminals and to the set of second test terminals, respectively, are independent from each other.
Inventor(s): Shih-Wei LIANG of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Jiun-Yi WU of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4214
Abstract: a chip package structure is provided. the chip package structure includes a photonic integrated circuit chip including a dielectric structure, a photodetector, an optical modulator, and a first waveguide structure in the dielectric structure. the photodetector and the optical modulator are connected to the first waveguide structure. the chip package structure includes an electronic integrated circuit chip over the photonic integrated circuit chip. the chip package structure includes an optical transmission chip over the photonic integrated circuit chip. the optical transmission chip includes a substrate, a second waveguide structure, and a first reflective structure.
Inventor(s): Shuen-Shin Liang of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Tsung-Fu Tsai of Changhua County TW for taiwan semiconductor manufacturing company, ltd., Szu-Wei Lu of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chung-Shi Liu of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02F1/01
CPC Code(s): G02F1/0113
Abstract: an electro-optical device includes a waveguide and a first electrode and a second electrode. the first electrode and the second electrode at first and second sides of the waveguide, wherein the first electrode and the second electrode directly contact and extend beyond the first and second sides of the waveguide respectively.
Inventor(s): Kun-Lung HSIEH of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hao-En LUO of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Shang-Cheng TSAI of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chih-Wei WEN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/24
CPC Code(s): G03F1/24
Abstract: an extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and patterned absorber layer on the reflective multilayer stack is provided with a pellicle membrane frame attached to the substrate. in some embodiments, the pellicle membrane frame is attached to the substrate using an adhesive between the pellicle membrane frame and the substrate. in some embodiments, the pellicle membrane frame is located in a trench formed in the reflective multilayer stack and patterned absorber layer. in other embodiments, the pellicle membrane frame not located in a trench formed in the reflective multilayer stack and patterned absorber layer.
Inventor(s): Chien-Wei WANG of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Wei-Han LAI of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yilang County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/32, G03F7/11, G03F7/30, H01L21/02, H01L21/027
CPC Code(s): G03F7/325
Abstract: the present disclosure provides resist rinse solutions and corresponding lithography techniques that achieve high pattern structural integrity for advanced technology nodes. an example lithography method includes forming a resist layer over a workpiece, exposing the resist layer to radiation, developing the exposed resist layer using a developer that removes an unexposed portion of the exposed resist layer, thereby forming a patterned resist layer, and rinsing the patterned resist layer using a rinse solution. the developer is an organic solution, and the rinse solution includes water.
Inventor(s): Chih-Wei CHANG of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Chun-Hua CHANG of Zhubei City TW for taiwan semiconductor manufacturing company, ltd., Chun-Hsien WEN of Taoyuan County TW for taiwan semiconductor manufacturing company, ltd., Johnny Chiahao LI of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Jerry Chang Jui KAO of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F113/10
CPC Code(s): G06F30/392
Abstract: a method for creating a layout element includes receiving an integrated circuit (ic) layout pattern that includes a shape corresponding to a component of the layout pattern. a mathematical definition of the shape is retrieved from a shape database, and parameter inputs regarding characteristics of the shape are received. a vertex listing is created based on the mathematical definition of the shape and the parameter inputs, and a layout element is created based on the vertex listing.
Inventor(s): XiuLi YANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ching-Wei WU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., He-Zhou WAN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Kuan CHENG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Luping KONG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C8/18, G11C7/10, G11C7/22, G11C8/08, G11C8/10, G11C11/418, G11C11/419
CPC Code(s): G11C8/18
Abstract: a memory circuit includes a control circuit configured to receive a clock signal including a clock cycle and output control signals based on the clock signal, an input circuit arrangement configured to, responsive to the control signals, pass a latched address to an output of the input circuit arrangement, the latched address including, during a first half of the clock cycle, a read address received at a first input port, and, during a second half of the clock cycle, a write address received at a second input port, an array of single-port memory cells, the memory circuit being configured to perform read and write operations during the respective first and second halves of the clock cycle, and a decoding circuit arrangement configured to, based on the latched address at the output, activate a row of memory cells of the array during each of the first and second clock cycle halves.
Inventor(s): Harry-Hak-Lay CHUANG of Zhubei City TW for taiwan semiconductor manufacturing company, ltd., Sheng-Huang HUANG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Hung-Cho WANG of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Sheng-Chang CHEN of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/16, G11C5/02, G11C5/06, H10B61/00, H10N50/01, H10N50/80
CPC Code(s): G11C11/161
Abstract: a method for fabricating a semiconductor device is provided. the method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.
Inventor(s): Meng-Sheng CHANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chia-En HUANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Gu-Huan LI of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/16
CPC Code(s): G11C11/1657
Abstract: a method for operating a memory device is provided. a first address is decoded to select a bit line of a memory device. a second address is decoded to select a word line of the memory device. a word line voltage is applied to the selected word line. a bit line voltage is applied to the selected bit line. a first bias voltage is applied to each of a plurality of unselected word lines connected to a plurality of memory cells connected to the selected bit line san a memory cell connected to both the selected bit line and the selected word line.
Inventor(s): Jui-Che Tsai of Tainan TW for taiwan semiconductor manufacturing company, ltd., Chen-Lin Yang of Zhubei City TW for taiwan semiconductor manufacturing company, ltd., Yu-Hao Hsu of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Shih-Lien Linus Lu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/418, G06F7/58, G11C5/14, G11C7/12, G11C8/08
CPC Code(s): G11C11/418
Abstract: a memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (rng) phase; and operate as a memory cell at a first voltage level during a sram phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the rng phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.
Inventor(s): Perng-Fei YUH of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Shao-Ting WU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Yu-Fan LIN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C13/00, G11C7/14, G11C11/16
CPC Code(s): G11C13/0038
Abstract: a memory circuit includes an operational amplifier configured to generate a bias voltage at an output terminal responsive to reference and feedback voltages received at respective first and second input terminals, a first nmos device including a gate coupled to the output terminal of the operational amplifier, a second nmos device including a gate coupled to a source terminal of the first nmos device and a source terminal coupled to the second input terminal of the operational amplifier, a resistive device coupled between the source terminal of the second nmos device and a power reference node, a third nmos device including a gate coupled to the output terminal of the operational amplifier, a fourth nmos device including a gate coupled to a source terminal of the third nmos device, and a resistance-based memory device coupled between a source terminal of the fourth nmos device and the power reference node.
Inventor(s): Szu-Hua CHEN of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Lilin CHANG of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Yahru CHENG of Taipei TW for taiwan semiconductor manufacturing company, ltd., Wei-Yen WOON of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Szuya LIAO of Zhubei TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01J37/32, H01L21/768, H01L21/822, H01L23/532
CPC Code(s): H01L21/0234
Abstract: a low thermal budget dielectric material deposition process is provided. the dielectric material may be deposited using spin-on coating, and treated with a microwave plasma treatment. in some implementations, the dielectric material is used adjacent a contact feature of a cfet device, such as a contact feature providing connection to a source/drain region of a bottom transistor of a cfet device.
Inventor(s): Chung-Liang CHENG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/306, G06N20/00, H01L21/283, H10D62/10, H10D64/27, H10D84/83
CPC Code(s): H01L21/30604
Abstract: a semiconductor process system etches gate metals on semiconductor wafers. the semiconductor process system includes a machine learning based analysis model. the analysis model dynamically selects process conditions for an etching process. the process system then uses the selected process conditions data for the next etching process.
Inventor(s): Ting-Ya Lo of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Cheng-Chin Lee of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Shao-Kuan Lee of Kaohsiung City TW for taiwan semiconductor manufacturing company, ltd., Hsin-Yen Huang of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang Chang of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/528, H01L23/532
CPC Code(s): H01L21/7682
Abstract: semiconductor structures and methods of forming the same are provided. an exemplary method incudes forming a metal layer over a substrate, patterning the metal layer to from first and second metal lines with a trench therebetween, depositing a sacrificial layer in a lower portion of the trench, forming a first dielectric layer on the sacrificial layer, selectively removing the sacrificial layer to form an air gap between the first and second metal lines after the forming of the first dielectric layer, and depositing a second dielectric layer over the first dielectric layer and in an upper portion of the trench.
Inventor(s): Szu-Hua Chen of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Kuan-Kan Hu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Wei-Yen Woon of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/532
CPC Code(s): H01L21/76831
Abstract: a method of forming a semiconductor structure includes forming a conductive feature in a first dielectric layer, forming a second dielectric layer over the conductive feature, forming an opening in the second dielectric layer to expose a top surface of the conductive feature, forming an inhibitor film at the top surface of the conductive feature, depositing a thermal conductive layer having a first portion on sidewalls of the opening and a second portion on a top surface of second dielectric layer, removing the inhibitor film to expose the top surface of the conductive feature, depositing a conductive material in the opening and on the second portion of the thermal conductive layer, removing a portion of the conductive material to expose the second portion of the thermal conductive layer, and forming a third dielectric layer on the second portion of the thermal conductive layer and on the second dielectric layer.
Inventor(s): Hsia-Wei CHEN of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Fu-Ting SUNG of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Yu-Wen LIAO of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Wen-Ting CHU of Kaohsiung City TW for taiwan semiconductor manufacturing company, ltd., Fa-Shen JIANG of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Tzu-Hsuan YEH of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/528, H01L23/532
CPC Code(s): H01L21/76877
Abstract: an integrated circuit structure includes a plurality of transistors, an interconnect layer, and a memory stack. the interconnect layer includes an interlayer dielectric (ild) and a conductive structure embedded in the ild. the conductive structure includes a barrier layer and a conductive filling material surrounded by the barrier layer in a cross-sectional view. the memory stack is over the interconnect layer. the memory stack includes a bottom electrode extending across the conductive structure in the cross-sectional view, a resistance switching layer over the bottom electrode, and a top electrode over the resistance switching layer. in the cross-sectional view, an interface formed by the bottom electrode and the barrier layer has a topmost point higher than a topmost point of an interface formed by the bottom electrode and the conductive filling material.
Inventor(s): Chen-Hua Yu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Wei Ling Chang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chuei-Tang Wang of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Tin-Hao Kuo of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Che-Wei Hsu of Kaohsiung City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/77, H01L23/00, H01L23/40, H01L23/528, H01L25/18
CPC Code(s): H01L21/76895
Abstract: systems, devices and methods of manufacturing a system on silicon wafer (sosw) device and package are described herein. a plurality of functional dies is formed in a silicon wafer. different sets of masks are used to form different types of the functional dies in the silicon wafer. a first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. a second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. an optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. the optional backside redistribution structure may provide backside interconnects between functional dies of different types.
Inventor(s): Isha Datye of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Sam Vaziri of San Jose CA US for taiwan semiconductor manufacturing company, ltd., Xinyu Bao of Fremont CA US for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L21/768, H01L21/8234, H01L23/00, H01L23/373, H01L23/48, H01L25/065, H01L27/088
CPC Code(s): H01L23/367
Abstract: an ic structure includes a frontside interconnect structure on a front side of a device layer, the frontside interconnect structure includes first metal features and second metal features isolated from each other by and embedded in an imd layer, the first metal features are electrically connected to the transistor devices, and the second metal features are electrically isolated from the transistor devices; a backside interconnect structure on a back side of the device layer, the backside interconnect structure includes third metal features and fourth metal features isolated from each other by and embedded in a backside imd layer, the third metal features are electrically connected to the transistor devices, and the fourth metal features are electrically isolated from the transistor devices. the ic structure further includes a heat spreader layer having a material that is thermally conductive and electrically insulating on a back side of the backside interconnect structure.
Inventor(s): Che Chi Shih of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Ku-Feng Yang of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/373, H01L21/8238, H01L23/00, H01L27/088
CPC Code(s): H01L23/3732
Abstract: the present disclosure provides an integrated circuit (ic) structure in accordance with some embodiments. the ic structure includes a circuit structure having semiconductor devices formed on a first substrate, an interconnect structure over the semiconductor devices; and a thermal dissipation structure formed on a second substrate. the second substrate is boned to the circuit structure such that the thermal dissipation structure is interposed between the first and second substrates. the thermal dissipation structure includes a diamond-like carbon (dlc) layer. the dlc layer includes a bottom portion having large grain sizes and a top portion having fine dlc grain sizes.
Inventor(s): Sam Vaziri of San Jose CA US for taiwan semiconductor manufacturing company, ltd., Xinyu Bao of Fremont CA US for taiwan semiconductor manufacturing company, ltd., Isha Datye of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/373, H01L21/768, H01L21/8234, H01L29/417, H01L29/66
CPC Code(s): H01L23/3732
Abstract: one aspect of the present disclosure pertains to an integrated circuit (ic) structure and method of fabricating thereof. the ic structure includes a transistor device formed on a substrate where the transistor device having source/drain (s/d) regions and a gate structure. a multi-layer interconnect (mli) structure including metal lines and metal vias embedded in an intermetal dielectric (imd) layer is formed over the substrate. and a thermal dissipation layer is formed having a surface with a plurality of peaks and valleys disposed over at least a portion of the mli structure. a bonding layer is disposed over the thermal dissipation layer and covering the plurality of peaks and valleys.
Inventor(s): Isha DATYE of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Sam VAZIRI of San Jose CA US for taiwan semiconductor manufacturing company, ltd., Xinyu BAO of Fremont CA US for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/373, H01L23/00, H01L23/522, H01L25/065
CPC Code(s): H01L23/3736
Abstract: one aspect of the present disclosure pertains to an integrated circuit (ic) structure and method of fabricating thereof. the ic structure may include the first plurality of thermal vias disposed at a first pitch and the third plurality of thermal vias disposed at a second pitch, the second pitch greater than the first pitch.
Inventor(s): Cheng-Ming Lin of Kaohsiung City TW for taiwan semiconductor manufacturing company, ltd., Che Chi Shih of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Wei-Yen Woon of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Isha Datye of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Sam Vaziri of San Jose CA US for taiwan semiconductor manufacturing company, ltd., Po-Yu Chen of Baoshan Township TW for taiwan semiconductor manufacturing company, ltd., Cheng Hung Wu of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Wei-Pin Changchien of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Xinyu Bao of Fremont CA US for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/38, H01L21/48, H01L23/00, H01L23/48, H01L23/528, H01L23/538, H01L25/065
CPC Code(s): H01L23/38
Abstract: a thermoelectric cooler (tec) is positioned to move heat away from a hot spot on a semiconductor chip and toward a dielectric substrate. this approach to thermal management is particularly effective when used in conjunction with a buried rail and back side power delivery. the tec may be in a layer that contains solder connections be between two device layers an ic package. alternatively, the tec may be in a metal interconnect structure over the semiconductor substrate such as in a passivation stack at the top of the metal interconnect structure. tecs at either of these locations may be formed by wafer-level processing.
Inventor(s): Chao-Wei Li of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chun-Yen Lan of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Yu-Wei Lin of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Sheng-Hsiang Chiu of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Tzu-Ting Chou of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Pei-Hsuan Lee of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Chih-Wei Lin of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/42, H01L23/00, H01L23/31, H01L23/498
CPC Code(s): H01L23/42
Abstract: a package structure is provided. the package structure comprises a package substrate, an electronic device, a thermal interface material (tim), a lid and an insulating encapsulant. the electronic device is disposed on and electrically connected to the package substrate. the tim is disposed on the electronic device. the lid is disposed on the tim. the insulating encapsulant is disposed on the package substrate and laterally encapsulates the electronic device and the tim. a lateral dimension of the tim is greater than a lateral dimension of the electronic device.
Inventor(s): Ming-Hsien Lin of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Wen-Che Liao of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Kun-Yen Liao of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang Chang of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/427, H01L21/02, H01L21/768, H01L23/373
CPC Code(s): H01L23/427
Abstract: a contact structure according to the present disclosure includes a conductive feature, an etch stop layer (esl) over the conductive feature, a dielectric layer over the esl, and a contact feature extending through the dielectric layer and the esl to contact the conductive feature. the dielectric layer includes a low-k dielectric matrix material, and nano-pipes disposed in the low-k dielectric matrix material and configured to reduce a thermal resistance of the dielectric layer.
Inventor(s): Jhih-Yu Wang of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Po-Han Wang of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang Hu of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L23/00, H01L23/538, H01L23/544, H01L25/10
CPC Code(s): H01L23/481
Abstract: a semiconductor package and a formation method thereof are provided. the method includes: providing a device wafer, with a barrier layer covering a back surface of a semiconductor substrate, and having a through substrate via (tsv) penetrating through the barrier layer and extending into the semiconductor substrate; defining an alignment mark over the back surface of the semiconductor substrate; forming a seed layer over the back surface of the semiconductor substrate, wherein the seed layer has a recess portion corresponding to the alignment mark; forming a mask layer on the seed layer; performing a lithography process by using a redefined alignment mark formed by the recess portion of the seed layer, to form an opening through the mask layer and overlapping the tsv; filling a conductive structure in the opening; removing the mask layer and portions of the seed layer around the conductive structure; and singulating the processed device wafer.
Inventor(s): Chih-Chiang Chang of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Hua-Wei Tseng of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Ta-Hsuan Lin of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Wu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Der-Chyang Yeh of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L23/00, H01L23/31, H01L23/367, H01L23/522, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H01L23/49822
Abstract: in a semiconductor package having a redistribution structure, two or more semiconductor dies are connected to a first side of the redistribution structure and an encapsulant surrounds the two or more semiconductor dies. an integrated passive device (ipd) is connected on a second side of the redistribution structure. the second side is opposite to the first side and the ipd is electrically coupled to the redistribution structure. an interconnect device is connected on the second side of the redistribution structure and is electrically coupled to the redistribution structure. two or more external connections are on the second side of the redistribution structure and are electrically coupled to the redistribution structure.
Inventor(s): Chuan-Pu CHOU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chia-Tien WU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hsin-Ping CHEN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Wei-Chen CHU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/532
CPC Code(s): H01L23/5226
Abstract: a semiconductor structure is provided. the semiconductor structure includes a first dielectric layer, a first metal layer, a via, an air gap, an etching stop layer, a second dielectric layer, and a second metal layer. the first metal layer is embedded in the first dielectric layer. the first metal layer includes a first conductive line and a second conductive line. the via is disposed on the first conductive line. the air gap is located on the second conductive line. the sustaining layer covers the air gap. the etching stop layer is disposed on the sustaining layer. the second dielectric layer is disposed on the etching stop layer. the second metal layer is disposed on the second dielectric layer and connected to the via.
Inventor(s): Chi-Hui Lai of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Yang-Che Chen of Hsin-Chu City TW for taiwan semiconductor manufacturing company, ltd., Hsiang-Tai Lu of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Wei-Ray Lin of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Tse-Wei Liao of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Ming Jun Li of New Taipei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/66, H01L23/00, H01L23/48, H01L23/58
CPC Code(s): H01L23/5226
Abstract: a semiconductor includes a first substrate having a device region and a ring region surrounding the device region, a first interconnect structure over the first substrate, the first interconnect structure including a first via tower and a second via tower, a first bonding layer over the first interconnect structure and including a first metal bonding feature, a second bonding layer over the first bonding layer and including a second metal bonding feature in contact with the first metal bonding feature, and a second interconnect structure over the second bonding layer and including a third via tower extending through the second interconnect structure and disposed directly over the ring region. the first via tower is electrically coupled to the second via tower by a first metal line. the first via tower is electrically coupled to the third via tower by the first metal bonding feature and the second metal bonding feature.
Inventor(s): Chrong Jung LIN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Ya-Chin KING of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Gui-Sheng CHAO of Taichung City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528, H01L27/07
CPC Code(s): H01L23/5226
Abstract: an integrated circuit device includes a first metallization layer, a second metallization layer, and a first metal via. the first metallization layer comprises two adjacent first metal lines. the second metallization layer is over the first metallization layer, wherein the second metallization layer comprises a second metal line. the first metal via is connected with a bottom of the second metal line. the first metal via is between the first metal lines and misaligned with the first metal lines in a top view.
Inventor(s): Wen-Ling CHANG of Miaoli County TW for taiwan semiconductor manufacturing company, ltd., Chi-Hao CHANG of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Hsiang-Ku SHEN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Dian-Hau CHEN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/768, H01L23/522
CPC Code(s): H01L23/5283
Abstract: a method for forming a semiconductor device structure is provided. the method includes forming an interconnect structure over a substrate. the method further includes forming a passivation layer over the interconnect structure. the method further includes forming a conductive structure over the passivation layer, wherein the conductive structure includes a surrounding portion over the passivation layer, and a concave portion surrounded by the surrounding portion. a height of the surrounding portion is greater than a height of the concave portion calculated from a top surface of the passivation layer. the method further includes forming a liner over the conductive structure, wherein an oxygen-to-silicon ratio of the liner is lower than about 1.8.
Inventor(s): Han-Tang HUNG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Tsu-Chun KUO of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Shin-Yi YANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/768, H01L23/522, H01L23/528
CPC Code(s): H01L23/53238
Abstract: an interconnection structure includes a first dielectric layer, a second dielectric layer, a first conductive feature, and a second conductive feature. the second dielectric layer is disposed on one side of the first dielectric layer. the first conductive feature is embedded in the first dielectric layer or the second dielectric layer, the second conductive feature is embedded in the first dielectric layer or the second dielectric layer, wherein the first the conductive feature includes a first conductive material, the second conductive feature includes a second conductive material and a barrier layer, the first conductive material is different from the second conductive material. the first conductive material does not contain copper, and the second conductive material contains copper.
Inventor(s): Ming-Hsien Lin of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Kun-Yen Liao of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Hsin-Ping Chen of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Chia-Tien Wu of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang Chang of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/3213, H01L23/427, H01L23/528
CPC Code(s): H01L23/53276
Abstract: the present disclosure relates to an integrated chip. the integrated chip includes a plurality of conductive interconnects arranged within a dielectric structure having a plurality of inter-level dielectric (ild) layers stacked onto one another. a heat pipe vertically extends through the plurality of ild layers. a high thermal conductivity layer is sandwiched between neighboring ones of the plurality of ild layers. the high thermal conductivity layer laterally extends from over one or more of the plurality of conductive interconnects to the heat pipe.
Inventor(s): Kai-Fang Cheng of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang Chang of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Ming-Han Lee of Taipei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/768, H01L23/373, H01L23/522
CPC Code(s): H01L23/53295
Abstract: contact structures and methods of forming the same are provided. a contact structure according to the present disclosure includes an etch stop layer (esl), a first pillar feature and a second pillar feature disposed on the esl, a metal feature disposed between the first pillar feature and the second pillar feature, the metal feature including a first sidewall, a bottom surface, a second sidewall, and a top surface, a dielectric liner extending continuously from a top surface of the first pillar feature, along the first sidewall, the bottom surface and the second sidewall of the metal feature, and onto a top surface of the second pillar feature, and a gap between the first pillar feature and a portion of the dielectric liner that extends along the first sidewall of the metal feature.
Inventor(s): Chih Hsin YANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hui-Zhong ZHUANG of Kaohsiung TW for taiwan semiconductor manufacturing company, ltd., Mao-Nan WANG of Kaohsiung TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/768, H01L23/48, H01L25/065
CPC Code(s): H01L23/562
Abstract: a semiconductor device structure and methods of forming the same are described. the structure includes a through silicon via (tsv) disposed in an interconnect structure and a substrate, a guard structure located in the interconnect structure surrounding the tsv, and an active region surrounding the guard structure. a space between the guard structure and the active region is free of dummy devices.
Inventor(s): Wen-Shiang LIAO of Miaoli County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/64, H01L21/56, H01L23/00, H01L23/31, H01L23/498, H01L25/16
CPC Code(s): H01L23/645
Abstract: a package structure includes a first insulating layer, a second insulating layer, a magnetic element, a molding material, and a third insulating layer. the first insulating layer is formed on a substrate, and a first conductive feature is formed in the first insulating layer. the second insulating layer is formed on the first insulating layer. the magnetic element is disposed on the second insulating layer and includes a plurality of dielectric layers and magnetic permeable layers that are alternatively stacked. the molding material covers the magnetic element and the conductive feature, and conductive vias penetrate the second insulating layer and the molding material. the third insulating layer is formed on the molding material, and a second conductive feature is formed in the third insulating layer. the first conductive feature, the conductive vias, and the second conductive feature are electrically connected to form a coil surrounding the magnetic element.
Inventor(s): Ming-Fa Chen of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Hsien-Wei Chen of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Jie Chen of New Taipei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/56, H01L23/31
CPC Code(s): H01L24/05
Abstract: a semiconductor structure and a manufacturing method thereof are provided. the semiconductor structure includes an integrated circuit (ic) component, an insulating layer laterally encapsulating the ic component, a redistribution structure disposed on the insulating layer and the ic component, and a warpage control portion coupling to a back side of the ic component opposite to the redistribution structure. the redistribution structure is electrically connected to the ic component. the warpage control portion includes a substrate, a patterned dielectric layer disposed between the substrate and the ic component, and a metal pattern embedded in the patterned dielectric layer and electrically isolated from the ic component.
Inventor(s): Chih-Fan Huang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Yen-Ming Chen of Hsin-Chu TW for taiwan semiconductor manufacturing company, ltd., Chih-Sheng Li of Hsin-Chu City TW for taiwan semiconductor manufacturing company, ltd., Hui-Chi Chen of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Chih-Hung Lu of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/02
CPC Code(s): H01L24/05
Abstract: semiconductor devices, integrated circuits and methods of forming the same are provided. in one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.
Inventor(s): Meng-Che Tu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Po-Nan Yeh of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Po-Han Wang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang Hu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/31
CPC Code(s): H01L24/11
Abstract: a method includes forming a conductive pillar over and connecting to a conductive pad, dispensing a first polymer layer, wherein the first polymer layer contacts a lower portion of a sidewall of the conductive pillar, curing the first polymer layer, and dispensing a second polymer layer on the first polymer layer. the second polymer layer contacts an upper portion of the sidewall of the conductive pillar. the second polymer layer is then cured.
Inventor(s): Sheng-An Kuo of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chao-Wen Shih of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Kuo-Chiang Ting of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Yen-Ming Chen of Hsin-Chu County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/31, H01L23/48, H01L23/522, H01L23/538
CPC Code(s): H01L25/0652
Abstract: a structure including a first semiconductor die, second semiconductor dies, a bridge die, and a gap filling material is provided. the first semiconductor die includes integrated circuit regions. the second semiconductor dies are disposed over and electrically connected to the first semiconductor die. the bridge die is disposed over and electrically connected to the first semiconductor die, and the integrated circuit regions are electrically connected to each other through the bridge die. the gap filling material is disposed on the first semiconductor die to laterally encapsulate the bridge die and the second semiconductor dies.
Inventor(s): Shin-Puu Jeng of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Po-Yao Chuang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Shuo-Mao Chen of New Taipei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L23/31, H01L23/538, H01L25/00
CPC Code(s): H01L25/0652
Abstract: an embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.
Inventor(s): Wei-Yu CHEN of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., An-Jhih SU of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/498, H01L23/538, H01L25/00, H01L25/03
CPC Code(s): H01L25/0657
Abstract: a chip package structure is provided. the chip package structure includes a wiring structure. the chip package structure includes a first chip structure over the wiring structure. the chip package structure includes a first molding layer surrounding the first chip structure. the chip package structure includes a second chip structure over the first chip structure and the first molding layer. the chip package structure includes a second molding layer surrounding the second chip structure and over the first chip structure and the first molding layer. the chip package structure includes a third chip structure over the second chip structure and the second molding layer. the chip package structure includes a third molding layer surrounding the third chip structure and over the second chip structure and the second molding layer. the chip package structure includes a fourth molding layer surrounding the second molding layer and the third molding layer.
Inventor(s): Chih-Chien Pan of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Chin-Fu Kao of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Li-Hui Cheng of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Szu-Wei Lu of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/16, G02B6/13, H01L21/56, H01L23/00, H01L23/24
CPC Code(s): H01L25/167
Abstract: a package structure and methods of forming a package structure are provided. the package structure includes a first die, a second die, a wall structure and an encapsulant. the second die is electrically bonded to the first die. the wall structure is located aside the second die and on the first die. the wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. the encapsulant laterally encapsulates the second die and the wall structure.
Inventor(s): Chung-Cheng Chou of Hsin-Chu TW for taiwan semiconductor manufacturing company, ltd., Tien-Yen Wang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H02M3/07, G11C5/14, G11C13/00
CPC Code(s): H02M3/07
Abstract: a system includes a charge pump system having a plurality of enable signal input terminals and an output terminal, the charge pump system configured to provide an output voltage at the output terminal; and a detection circuit connected to the enable terminals and the output terminal of the charge pump system, the detection circuit configured to compare the charge pump system output voltage to a plurality of predefined input detection voltage levels, and to selectively output a plurality of enable signals to the charge pump system enable signal input terminals in response to the comparison.
Inventor(s): Chih-Kuan Yu of Nantou County TW for taiwan semiconductor manufacturing company, ltd., Feng-Chi Hung of Chu-Bei City TW for taiwan semiconductor manufacturing company, ltd., Wen-I Hsu of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Bing Cheng You of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City TW for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H04N25/79, H01L27/146
CPC Code(s): H04N25/79
Abstract: various embodiments of the present disclosure are directed to a stacked complementary metal-oxide semiconductor (cmos) image sensor. a first integrated circuit (ic) chip and a second ic chip are vertically stacked. a pixel sensor spans the first and second ic chips. the pixel sensor comprises a first transfer transistor and a photodetector that are at the first ic chip, and further comprises a source-follower transistor, a transistor capacitor, and a second transfer transistor that are at the second ic chip. the transistor capacitor and the second transfer transistor are electrically coupled in series from a source/drain region of the first transfer transistor to a gate electrode of the source-follower transistor.
Inventor(s): Sheng-Chen Wang of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Meng-Han Lin of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Han-Jong Chia of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Feng-Cheng Yang of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, H01L23/48, H01L23/522, H10B51/10, H10B51/40
CPC Code(s): H10B51/20
Abstract: a semiconductor structure and method of forming the same are provided. the semiconductor structure includes a circuit structure, an interlayer structure and a memory structure. the circuit structure includes a substrate having semiconductor devices formed thereon; a dielectric structure disposed over the semiconductor devices; and an interconnect layer embedded in the dielectric structure and connected to the semiconductor devices. the interlayer structure is disposed over the circuit structure. the memory structure is disposed over the interlayer structure and physically separated from the circuit structure by the interlayer structure.
Inventor(s): Yu-Sheng CHEN of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Kuen-Yi CHEN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Yi-Hsuan CHEN of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Hsin Heng WANG of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Yi Ching ONG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Kuo-Ching HUANG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B61/00, G06N3/047, H10B63/00
CPC Code(s): H10B61/22
Abstract: a neural network circuit includes an input neuron layer comprises a plurality of first neurons. a hidden neuron layer includes a plurality of second neurons, wherein each of the second neurons comprises a probabilistic bit having a time-varying resistance. the probabilistic bit is a magnetic tunnel junction structure comprises a pinned layer, a free layer, and a tunneling barrier layer between the pinned layer and the free layer. a weight matrix comprising a plurality of synapse units, each of the synapse units connecting one of the plurality of first neurons to a corresponding one of the plurality of first neurons.
Inventor(s): Anhao CHENG of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Fang-Ting KUO of Zhubei TW for taiwan semiconductor manufacturing company, ltd., Yen-Yu CHEN of Taichung TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D1/68, H01L23/522, H01L23/528
CPC Code(s): H10D1/696
Abstract: the present disclosure is directed to a method for the fabrication of mim capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. the method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. the method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. the method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.
Inventor(s): Chun-Hsiung LIN of Zhubei City TW for taiwan semiconductor manufacturing company, ltd., Pei-Hsun WANG of Kaohsiung City TW for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township TW for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHING of Zhubei City TW for taiwan semiconductor manufacturing company, ltd., Jui-Chien HUANG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D30/01, H10D30/62, H10D62/10, H10D84/01, H10D84/03
CPC Code(s): H10D30/0243
Abstract: a semiconductor device is provided. the semiconductor device includes a silicon layer over a fin, a doped semiconductor layer over the fin and adjoining the silicon layer, a plurality of channel layers over the silicon layer, a source/drain structure on the doped semiconductor layer and adjoining plurality of channel layers, and a plurality of inner spacers between the plurality of channel layers.
Inventor(s): Jhon-Jhy LIAW of Zhudong Township TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/775, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H10B10/00
CPC Code(s): H10D30/43
Abstract: a semiconductor structure includes a substrate, nanostructures, source/drain features, a gate structure, inner spacers, and dielectric layers. the nanostructures are over the substrate and spaced apart from each other in a z-direction. the source/drain features are attached to the nanostructures in an x-direction. the gate structure wraps around the nanostructures and extends in a y-direction. the inner spacers are between the nanostructures in the z-direction. the dielectric layers are under the inner spacers. bottom surfaces of the dielectric layers are lower than a bottommost surface of the gate structure.
Inventor(s): Yu-Ho CHIANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Wei-Chen CHANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Jiun-Jie CHAO of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Jyh-Huei CHEN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Jye-Yen CHENG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8238, H01L23/522, H01L23/528, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D30/6729
Abstract: a semiconductor structure includes: a first fin portion and a second fin portion; a first device and a second device which are respectively disposed on front surfaces of the first and second fin portions, each of the first and second devices including a source/drain portion; an isolation portion disposed to separate the first fin portion from the second fin portion and to separate the first device from the second device; and a hard mask portion disposed beneath a back surface of the isolation portion, and including a main region and two sidewall regions that are respectively located at two opposite sides of the main region so as to separate the main region from the first and second fin portions. the sidewall regions are made of a material different from that of the isolation portion. the main region is made of a material different from the material of the sidewall regions.
Inventor(s): Jung-Hung CHANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Tsung-Han CHUANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Fu-Cheng CHANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Shih-Cheng CHEN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chia-Cheng TSAI of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L27/088, H01L29/06, H01L29/08, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D30/6735
Abstract: a semiconductor device includes two source/drain regions, two isolation elements, a channel feature, at least one semiconductor layer and a gate feature. the source/drain regions are spaced apart from each other, and are respectively disposed above the isolation elements. the channel feature includes at least one effective channel layer and at least one dummy channel layer that are spaced apart from each other. each of the at least one effective channel layer extends between the source/drain regions. each of the at least one dummy channel layer extends between the isolation elements. the at least one semiconductor layer at least covers a lower surface of a bottommost one of the at least one dummy channel layer. the gate feature is disposed around the at least one effective channel layer, such that two opposite surfaces of each of the at least one effective channel layer are adjacent to the gate feature.
Inventor(s): Shih-Yao Lin of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Chih-Han Lin of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Hsiao Wen Lee of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D30/67, H01L21/3065, H10D30/01, H10D30/60, H10D62/10, H10D64/01
CPC Code(s): H10D30/6735
Abstract: a semiconductor device includes a plurality of semiconductor layers vertically separated from one another. each of the plurality of semiconductor layers extends along a first lateral direction. the semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. the lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.
Inventor(s): Hsin-Che CHIANG of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Wei-Chih KAO of Taipei TW for taiwan semiconductor manufacturing company, ltd., Ju-Li HUANG of Nantou County TW for taiwan semiconductor manufacturing company, ltd., Jeng-Ya YEH of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Mu-Chi CHIANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Jhon-Jhy LIAW of Zhudong Township TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H10D30/6757
Abstract: semiconductor structures and methods for manufacturing the same are provided. the semiconductor structure includes first nanostructures formed over a substrate along a first direction, and second nanostructures formed over the substrate along the first direction. the semiconductor structure includes a first gate structure formed over the first nanostructures along a second direction, and a second gate structure formed over the second nanostructures along the second direction. the semiconductor structure also includes a dielectric wall structure between the first gate structure and the second gate structure along the second direction. the semiconductor structure also includes a dielectric strip structure formed along the second direction. the dielectric strip structure includes a protruding portion which is lower than a bottom surface of a bottommost first nanostructure.
Inventor(s): Shu-Han Chen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Yi-Shao Li of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chun-Heng Chen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D62/10, H10D30/62, H10D30/67, H10D64/27
CPC Code(s): H10D62/118
Abstract: a device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. the horizontal portions have a first thickness. the vertical portions have a second thickness. the corner portions have a third thickness. both of the second thickness and the third thickness are greater than the first thickness. a high-k dielectric layer surrounds the oxide layer. a gate electrode surrounds the high-k dielectric layer.
Inventor(s): Chih-Chao Chou of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Baoshan Township TW for taiwan semiconductor manufacturing company, ltd., Ching-Wei Tsai of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/768, H01L21/8234, H01L23/522, H01L23/528, H01L27/06, H01L27/088, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D62/121
Abstract: a method of forming a semiconductor device includes: forming a device layer that includes nanostructures and a gate structure around the nanostructures; forming a first interconnect structure on a front-side of the device layer; and forming a second interconnect structure on a backside of the device layer, which includes: forming a dielectric layer along the backside of the device layer using a first dielectric material; forming a first conductive feature and a second conductive feature in the dielectric layer; form an opening in the dielectric layer between the first and the second conductive features; forming a first barrier layer and a second barrier layer along a first sidewall of the first conductive feature and along a second sidewall of the second conductive feature, respectively; and forming a second dielectric material different from the first dielectric material in the opening between the first barrier layer and the second barrier layer.
Inventor(s): Kuo-Chiang TSAI of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Jeng-Ya YEH of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Mu-Chi CHIANG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/423, H01L29/66, H01L29/775, H01L29/78
CPC Code(s): H10D62/121
Abstract: a method includes forming a transistor over a substrate, the transistor comprising a channel region, a gate structure over the channel region, and a plurality of source/drain regions on opposite sides of the channel region; forming a source/drain contact over one of the source/drain regions; forming a source/drain via over the source/drain contact, wherein from a top view, the source/drain via has a t-shaped profile, the source/drain via has a first portion extending in a lengthwise direction of the channel region, and a second portion extending in a lengthwise direction of the gate structure.
Inventor(s): Hsin-Yi Lee of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Jia-Ming Lin of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D62/10, H01L21/265, H10D84/85
CPC Code(s): H10D62/121
Abstract: in an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.
Inventor(s): Tung-Ying LEE of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Tse-An CHEN of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Tzu-Chung WANG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Miin-Jang CHEN of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Yu-Tung YIN of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Meng-Chien YANG of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D64/01, H01L21/02, H01L21/28, H10D30/01, H10D30/62, H10D30/67, H10D62/10
CPC Code(s): H10D64/015
Abstract: a semiconductor device includes a channel structure, source region, a drain region, metal gate structure, and a self-assembled layer. the source region and the drain region are on opposite sides of the channel structure. a bottom surface of the source region is lower than a bottom surface of the channel structure, and a top surface of the source region is higher than a top surface of the channel structure. the metal gate structure covers the channel structure and between the source region and the drain region. the self-assembled layer is between the source region and the metal gate structure. the self-assembled layer is in contact with the bottom surface of the channel structure but spaced apart from the top surface of the channel structure.
Inventor(s): Yi-Ren CHEN of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Che-Chia CHANG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Po-Cheng CHI of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Yi-Hsin TING of Pingtung County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D64/017
Abstract: a semiconductor device structure and a method for forming a semiconductor device structure are provided. the method includes forming a metal gate stack wrapped around multiple semiconductor nanostructures, and the semiconductor nanostructures are adjacent to an epitaxial structure. the method also includes forming a dielectric layer over the metal gate stack and the epitaxial structure and partially removing the dielectric layer to form a contact opening exposing the epitaxial structure. the method further includes forming a first protective layer over sidewalls of the contact opening and forming a second protective layer over the first protective layer. the first protective layer has a lower dielectric constant than that of the second protective layer. in addition, the method includes forming a conductive contact over the second protective layer and the epitaxial structure to fill the contact opening.
Inventor(s): Li-Zhen YU of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Chia-Hao CHANG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Cheng-Chi CHUANG of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Yu-Ming LIN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D64/23, H01L21/02, H01L21/285, H01L21/311, H01L21/3213, H01L21/768, H10D64/01, H10D84/01, H10D84/03, H10D84/83, H10D84/85
CPC Code(s): H10D64/251
Abstract: a method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.
Inventor(s): Meng-Han Lin of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Zhubei City TW for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D64/23, H10D30/01, H10D62/17, H10D64/01, H10D64/27, H10D64/68, H10D84/01, H10D84/03, H10D84/83, H10D84/85
CPC Code(s): H10D64/258
Abstract: methods for forming contacts to source/drain regions and gate electrodes in low- and high-voltage devices and devices formed by the same are disclosed. in an embodiment a device includes a first channel region in a substrate adjacent a first source/drain region; a first gate over the first channel region; a second channel region in the substrate adjacent a second source/drain region, a top surface of the second channel region being below a top surface of the first channel region; a second gate over the second channel region; an ild over the first gate and the second gate; a first contact extending through the ild and coupled to the first source/drain region; and a second contact extending through the ild, coupled to the second source/drain region, and having a width greater a width of the first contact and a height greater than a height of the first contact.
Inventor(s): Chuan-Cheng TSOU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Po-Yuan SU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Sung-Hsin YANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Jung-Chi JENG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chen-Chieh CHIANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H10D84/038
Abstract: a method for manufacturing a semiconductor device includes: forming a first fin portion and a second fin portion on a semiconductor substrate, the first fin portion and the second fin portion being spaced apart from each other; and forming a first gate dielectric layer and a second gate dielectric layer on the first fin portion and the second fin portion, respectively, the first gate dielectric layer having a first thickness, the second gate dielectric layer having a second thickness different from the first thickness.
Inventor(s): Shang-Rong Li of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chih-Wei Lee of New Taipei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D84/038
Abstract: one aspect of the present disclosure pertains to a method of forming a semiconductor device. the method includes forming a high-k gate dielectric layer over a channel region of a substrate; depositing a work function metal layer over the high-k gate dielectric layer; forming a titanium nitride (tin) cap over the work function metal layer, wherein the tin cap includes one or more oxygenated regions; depositing a silicon cap layer over the tin cap; depositing a conductive glue layer over the silicon cap layer; and depositing a gate fill metal layer over the conductive glue layer to form a gate structure.
Inventor(s): Kuo-Cheng CHIANG of Zhubei City TW for taiwan semiconductor manufacturing company, ltd., Chung-Wei HSU of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Lung-Kun CHU of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Jia-Ni YU of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township TW for taiwan semiconductor manufacturing company, ltd., Mao-Lin HUANG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D84/03, H01L21/033, H01L21/28, H01L21/308, H10D30/01, H10D30/62, H10D62/10, H10D64/01, H10D64/66, H10D84/01, H10D84/85
CPC Code(s): H10D84/038
Abstract: a semiconductor device is provided. the semiconductor device includes a plurality of first nanostructures formed over a substrate, and a plurality of second nanostructures formed over the substrate. the semiconductor device includes a gate structure surrounding the first nanostructures and the second nanostructures, and the first hard mask layer and the second hard mask layer are surrounded by the gate dielectric layer. the semiconductor device includes an isolation structure extending upwardly above the substrate, and a bottom surface of the isolation structure is lower than a bottommost surface of the gate structure.
Inventor(s): Jui-Lin Chen of Taipei TW for taiwan semiconductor manufacturing company, ltd., Gu-Huan Li of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ping-Wei Wang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Lien-Jung Hung of Taipei TW for taiwan semiconductor manufacturing company, ltd., Chen-Ming Lee of Taoyuan TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234, H01L23/528, H01L29/06, H01L29/417, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D84/83
Abstract: semiconductor structures and methods for fabricating semiconductor structures are provided. a semiconductor structure includes a first fin extending in an x-direction and a second fin parallel to the first fin and distanced from the first fin in a y-direction perpendicular to the x-direction. each fin is formed with a first device area and a second device area aligned in the x-direction; an isolation region disposed between the fins; an isolation structure disposed between the device areas in each fin; and an isolation layer disposed under the fins. the isolation region contacts the isolation layer, the isolation structure contacts the isolation layer, and the isolation region contacts the isolation structure to isolate the first fin from the second fin and to isolate the first device area from the second device area in each fin.
Inventor(s): Yu-Xuan Huang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ching-Wei Tsai of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Jam-Wem Lee of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Kuo-Ji Chen of Taipei County TW for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsin-Chu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D84/83, H10D30/01, H10D30/62, H10D62/10, H10D84/80
CPC Code(s): H10D84/834
Abstract: the present disclosure provides embodiments of semiconductor devices. a semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.
Inventor(s): Tzu-Ging LIN of Kaohsiung TW for taiwan semiconductor manufacturing company, ltd., Hung-Yu LIN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chia-Chin LEE of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chun-Liang LAI of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Yun-Chen WU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H10D84/85
Abstract: embodiments of present disclosure relates to forming isolation structures in gate structures to prevent current leakage through source/drain regions (epi), transistors, and silicon substrate. the isolation structures are arranged in a pattern with a long isolation structure adjacent a short isolation structure. the isolation structures may be formed in the gate structure prior to or after the replacement gate sequence.
Inventor(s): Kuo-Cheng CHING of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Ching-Wei TSAI of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D84/85, H01L21/285, H01L21/311, H01L21/768, H10D30/01, H10D30/62, H10D30/69, H10D62/10, H10D62/13, H10D62/822, H10D62/832, H10D62/834, H10D64/01, H10D84/01, H10D84/03
CPC Code(s): H10D84/853
Abstract: a semiconductor device includes a semiconductor channel region, a source/drain region, and a contact structure. the semiconductor channel region is over a substrate. the source/drain region is adjacent the semiconductor channel region. the source/drain region has a notched corner. the contact structure has a portion inlaid in the notched corner in the source/drain region.
Inventor(s): Kuo-Cheng CHING of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Ching-Wei TSAI of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsin-Chu TW for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D84/85, H10D30/01, H10D30/62
CPC Code(s): H10D84/853
Abstract: a method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. the fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. a portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. a first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. a first source/drain feature is formed abutting the first portion of the first gate structure.
Inventor(s): Ya-Chin KING of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Chrong Jung LIN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Burn Jeng LIN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Shi-Jiun WANG of Changhua City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10F30/298, H10F77/20
CPC Code(s): H10F30/298
Abstract: a device includes an active region, an isolation structure, a gate structure, an interlayer dielectric (ild) layer, a reading contact, and a sensing contact. the isolation structure laterally surrounds the active region. the gate structure is across the active region. the ild layer laterally surrounds the gate structure. the reading contact is in contact with the isolation structure and is separated from the gate structure by a first portion of the ild layer. the sensing contact is in contact with the isolation structure and is separated from the gate structure by a second portion of the ild layer.
Inventor(s): Chung-Lei Chen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Yen-Liang Lin of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Ru-Shang Hsiao of Jhubei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H10F39/80373
Abstract: the present disclosure provides an image sensor and a method of manufacturing the same. the image sensor includes a substrate and a gate electrode. the gate electrode is disposed proximate to a first side of the substrate. the gate electrode includes a first gate portion, a second gate portion, and a third gate portion. the first gate portion is disposed over the first side of the substrate. the second gate portion is disposed within the substrate and connected to the first gate portion. the third gate portion is disposed below and connected to the second gate portion. a first width of the first gate portion is greater than a second width of the second gate portion, and a third width of the third gate portion is greater than the second width.
Inventor(s): Yi-Hsuan Wang of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Cheng-Yu Huang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Keng-Yu Chou of Kaohsiung City TW for taiwan semiconductor manufacturing company, ltd., Wei-Chieh Chiang of Yuanlin Township TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H10F39/8053
Abstract: some embodiments relate to an integrated circuit (ic) device including a substrate having first photodetector groups respectively associated with a plurality of color pixels and second photodetector groups respectively associated with a plurality of phase detection pixels. each of the first and second photodetector groups includes one or more photodetectors. the device further includes a grid structure over the substrate, color filters over the substrate, and a crosstalk reduction structure. the grid structure includes light shields, each configured to redirect light away from a corresponding one of the second photodetector groups. each color filter vertically spans the grid structure at a corresponding one of the first photodetector groups. the crosstalk reduction structure is level with the color filters and limits an amount of the light redirected by the light shield of each of the phase detection pixels to the first photodetector group of a neighboring one of the color pixels.
Inventor(s): Hsin-Hung Chen of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Wen-I Hsu of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Feng-Chi Hung of Chu-Bei City TW for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City TW for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H10F39/809
Abstract: the present disclosure relates to a multi-dimensional image sensor integrated chip (ic) structure. the multi-dimensional image sensor ic structure includes a plurality of image sensing elements disposed within a plurality of pixel regions arranged in a pixel array of a first integrated chip (ic) tier. the plurality of pixel regions include a plurality of active pixel regions and one or more dummy pixel regions. a plurality of pixel support devices are disposed on a second substrate within a second ic tier that is bonded to the first ic tier. a plurality of logic devices are disposed within a third ic tier that is bonded to the second ic tier. a through substrate via (tsv) extends vertically through the second substrate laterally outside of the plurality of pixel support devices and directly below the pixel array.
Inventor(s): Yi Yang of Fremont CA US for taiwan semiconductor manufacturing company, ltd., Yu-Jen Wang of San Jose CA US for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/01, H10B61/00
CPC Code(s): H10N50/01
Abstract: a method includes providing a first electrode, forming a stack of magnetic tunneling junction (mtj) layers on the first electrode, forming a second electrode on the stack of mtj layers, and forming a hybrid hard mask on the second electrode. the hybrid hard mask includes a first material layer, a second material layer, and a third material layer. the method also includes patterning the third material layer and the second material layer, patterning the first material layer while using the patterned third material layer and the patterned second material layer as a first mask, patterning the second electrode while using the patterned first material layer as a second mask, and etching the stack of mtj layers and the first electrode using the patterned second electrode as a third mask. after the etching the stack of mtj layers and the first electrode, the hybrid hard mask is completely removed.
Inventor(s): Hsiang-Ku Shen of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/01, H10B61/00, H10N50/80
CPC Code(s): H10N50/01
Abstract: a first metal layer extends across memory and logic device regions of a semiconductor structure. a dielectric barrier layer is disposed over the first metal layer. a first dielectric layer is disposed over the dielectric barrier layer in the memory device region and not in the logic device region. multiple magnetic tunneling junction (mtj) devices are disposed in the memory device region. a second dielectric layer is disposed in the memory device region and not in the logic device region. the second dielectric layer is disposed over the first dielectric layer and the mtj devices. an extreme low-k dielectric layer is disposed over the dielectric barrier layer in the logic device region. a conductive feature in the logic device region penetrates the extreme low-k dielectric layer and the dielectric barrier layer to electrically connect to the first metal layer.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on May 1st, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- C23C14/34
- B08B7/00
- B08B17/04
- C23C14/50
- H01J37/32
- H01J37/34
- CPC C23C14/34
- Taiwan semiconductor manufacturing company, ltd.
- E04B1/84
- B32B9/00
- C01F11/46
- E04B1/86
- E04B2/74
- E04C2/04
- E04C2/288
- G10K11/168
- CPC E04B1/8409
- G01R31/28
- H01L21/02
- CPC G01R31/2853
- G02B6/42
- CPC G02B6/4214
- G02F1/01
- CPC G02F1/0113
- G03F1/24
- CPC G03F1/24
- G03F7/32
- G03F7/11
- G03F7/30
- H01L21/027
- CPC G03F7/325
- G06F30/392
- G06F113/10
- CPC G06F30/392
- G11C8/18
- G11C7/10
- G11C7/22
- G11C8/08
- G11C8/10
- G11C11/418
- G11C11/419
- CPC G11C8/18
- G11C11/16
- G11C5/02
- G11C5/06
- H10B61/00
- H10N50/01
- H10N50/80
- CPC G11C11/161
- CPC G11C11/1657
- G06F7/58
- G11C5/14
- G11C7/12
- CPC G11C11/418
- G11C13/00
- G11C7/14
- CPC G11C13/0038
- H01L21/768
- H01L21/822
- H01L23/532
- CPC H01L21/0234
- H01L21/306
- G06N20/00
- H01L21/283
- H10D62/10
- H10D64/27
- H10D84/83
- CPC H01L21/30604
- H01L23/528
- CPC H01L21/7682
- H01L23/522
- CPC H01L21/76831
- CPC H01L21/76877
- H01L21/77
- H01L23/00
- H01L23/40
- H01L25/18
- CPC H01L21/76895
- H01L23/367
- H01L21/8234
- H01L23/373
- H01L23/48
- H01L25/065
- H01L27/088
- CPC H01L23/367
- H01L21/8238
- CPC H01L23/3732
- H01L29/417
- H01L29/66
- CPC H01L23/3736
- H01L23/38
- H01L21/48
- H01L23/538
- CPC H01L23/38
- H01L23/42
- H01L23/31
- H01L23/498
- CPC H01L23/42
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- CPC H01L23/427
- H01L23/544
- H01L25/10
- CPC H01L23/481
- H01L25/00
- CPC H01L23/49822
- CPC H01L23/5226
- H01L21/66
- H01L23/58
- H01L27/07
- CPC H01L23/5283
- CPC H01L23/53238
- H01L21/3213
- CPC H01L23/53276
- CPC H01L23/53295
- CPC H01L23/562
- H01L23/64
- H01L21/56
- H01L25/16
- CPC H01L23/645
- CPC H01L24/05
- CPC H01L24/11
- CPC H01L25/0652
- H01L25/03
- CPC H01L25/0657
- G02B6/13
- H01L23/24
- CPC H01L25/167
- H02M3/07
- CPC H02M3/07
- H04N25/79
- H01L27/146
- CPC H04N25/79
- H10B51/20
- H10B51/10
- H10B51/40
- CPC H10B51/20
- G06N3/047
- H10B63/00
- CPC H10B61/22
- H10D1/68
- CPC H10D1/696
- H10D30/01
- H10D30/62
- H10D84/01
- H10D84/03
- CPC H10D30/0243
- H01L29/775
- H01L29/06
- H01L29/08
- H01L29/423
- H10B10/00
- CPC H10D30/43
- H01L27/092
- H01L29/786
- CPC H10D30/6729
- CPC H10D30/6735
- H10D30/67
- H01L21/3065
- H10D30/60
- H10D64/01
- CPC H10D30/6757
- CPC H10D62/118
- H01L27/06
- CPC H10D62/121
- H01L29/78
- H01L21/265
- H10D84/85
- H01L21/28
- CPC H10D64/015
- CPC H10D64/017
- H10D64/23
- H01L21/285
- H01L21/311
- CPC H10D64/251
- H10D62/17
- H10D64/68
- CPC H10D64/258
- CPC H10D84/038
- H01L21/033
- H01L21/308
- H10D64/66
- CPC H10D84/83
- H10D84/80
- CPC H10D84/834
- CPC H10D84/85
- H10D30/69
- H10D62/13
- H10D62/822
- H10D62/832
- H10D62/834
- CPC H10D84/853
- H10F30/298
- H10F77/20
- CPC H10F30/298
- CPC H10F39/80373
- CPC H10F39/8053
- CPC H10F39/809
- CPC H10N50/01