Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on March 6th, 2025
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on March 6th, 2025
Taiwan Semiconductor Manufacturing Company, Ltd.: 81 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L29/66 (27), H01L29/423 (18), H01L29/06 (16), H01L29/786 (14), H01L21/768 (13) H10D30/6735 (4), H01L23/5226 (3), H10D30/62 (3), G11C11/419 (2), H01L25/50 (2)
With keywords such as: layer, semiconductor, structure, gate, device, dielectric, substrate, region, disposed, and metal in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Ting-Jung Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B81B3/00, B81C1/00, G02B7/02, H04N23/54, H04N23/68
CPC Code(s): B81B3/0072
Abstract: the present disclosure relates to an integrated chip structure. the integrated chip structure includes a mems device. the mems device includes a frame, a proof mass, and one or more curved cantilevers coupled between the frame and the proof mass. the one or more curved cantilevers have curved outer surfaces. the curved outer surfaces have a plurality of inflection points respectively arranged between turning points. the one or more curved cantilevers include four curved cantilevers respectively arranged along a different side of the proof mass.
Inventor(s): Shu-Cheng Chin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kong-Beng Thei of Pao-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01R1/04, H01L21/311, H01L21/768, H01L23/498, H01L23/522
CPC Code(s): G01R1/0416
Abstract: some embodiments relate to a method of an integrated circuit structure having a conductive structure for circuit probe testing. the method includes providing an integrated circuit structure including a substrate, a dielectric structure disposed over the substrate, and a plurality of electrodes disposed over an upper surface of the dielectric structure. the method also includes forming a first dielectric layer over the dielectric structure and the plurality of electrodes, etching the first dielectric layer over each of the plurality of electrodes, forming a conductive layer over the first dielectric layer and the plurality of electrodes, and removing at least a portion of the conductive layer to form a plurality of conductive structures over the plurality of electrodes. each of the plurality of conductive structures contacts a corresponding subset of the plurality of electrodes.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Liang Shao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Jan Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Sheng Huang of Hemei Township (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Fu Tsai of Changhua City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Jen Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42, G02B6/12, G02B6/13
CPC Code(s): G02B6/4214
Abstract: optical devices and methods of manufacture are presented in which a multi-tier connector is utilized to transmit and receive optical signals to and from an optical device. in embodiments a multi-tier connection unit receives optical signals from outside of an optical device, wherein the optical signals are originally in multiple levels. the multi-tier connection unit then routes the optical signals into a single level of optical components.
Inventor(s): Yun-Yue LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/62, G03F1/22, G03F1/80
CPC Code(s): G03F1/62
Abstract: a pellicle for an euv photo mask includes a first capping layer, a matrix layer disposed over the first capping layer, a second capping layer disposed over the matrix layer; and a metallic layer disposed over the second capping layer.
Inventor(s): Chien-Chih CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yilang County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/004
CPC Code(s): G03F7/0045
Abstract: a photo acid generator includes a photoactive cation and an anion. the photoactive cation includes a moiety and one or more euv absorbing atoms. the moiety includes onium salts, selenium salts, phosphonium salts, iodonium salts, or sulfonium salts. the one or more euv absorbing atoms are attached to the moiety. the anion is attached to the photoactive cation.
Inventor(s): Che-Chang HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Kang YU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Chieh CHIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jui CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Heng-Hsin LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, G06T1/00, G06T7/00, G21K1/06, H05G2/00
CPC Code(s): G03F7/70033
Abstract: in a method of generating extreme ultraviolet (euv) radiation in a semiconductor manufacturing system one or more streams of a gas is directed, through one or more gas outlets mounted over a rim of a collector mirror of an euv radiation source, to generate a flow of the gas over a surface of the collector mirror. the one or more flow rates of the one or more streams of the gas are adjusted to reduce an amount of metal debris deposited on the surface of the collector mirror.
Inventor(s): Chun-Shuo CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsuan-Yuan Wu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kai Yuan Chan of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chien Chou Ko of Tainan County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G05B19/4099, G08B21/18
CPC Code(s): G05B19/4099
Abstract: the present disclosure describes a system configured to prevent a false low water alarm in a semiconductor processing system. the system includes a liquid reservoir configured to hold a liquid and a sensor system configured to delay an alarm for a predetermined duration of time. in some embodiments, the sensor system includes a sensor configured to determine a level of the fluid in the liquid reservoir and send a signal indicating the level of the fluid to an alarm system and a delay circuit coupled to the fluid level sensor and configured to delay the signal to the alarm system for the predetermined duration of time.
Inventor(s): Motoki TAMURA of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G05F1/575, G05F1/565, H03K17/082
CPC Code(s): G05F1/575
Abstract: a circuit includes a first capacitive device coupled between first and second nodes, a second capacitive device coupled between third and fourth nodes, a first switching device coupled between the first node and a voltage node, a second switching device coupled between the second node and a reference voltage node, a third switching device coupled between the third node and the voltage node, a fourth switching device coupled between the fourth node and the reference voltage node, fifth through eighth switching devices coupled between the respective first through fourth nodes and an output node, and first and second variable capacitance devices including first terminals coupled to either the respective first and third nodes or the respective second and fourth nodes.
Inventor(s): Po-Sheng WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kao-Cheng LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yangsyu LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Huei CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Cheng Hung LEE of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jonathan Tsung-Yung CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/10, G11C11/419, H10B10/00
CPC Code(s): G11C7/10
Abstract: a memory device in an integrated circuit is provided, including an input/output (i/o) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the i/o circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the i/o circuit. a first width of the first pair of data lines is different from a second width of the second pair of data lines.
20250078885. MEMORY DEVICE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): He-Zhou WAN of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Xiu-Li YANG of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Pei-Le LI of Nanjing City (CN) for taiwan semiconductor manufacturing company, ltd., Ching-Wei WU of Nantou County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/10, G11C5/14, G11C7/12, G11C8/10
CPC Code(s): G11C7/109
Abstract: a memory device includes a memory array, a first latch and a first logic element. the memory array is configured to operate according to a first global write signal. the first latch is configured to generate a first latch write data based on a clock signal. the first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.
Inventor(s): Po-Hao Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Fu Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chun Shih of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/16, G11C11/00, G11C17/16, G11C17/18, H10B61/00
CPC Code(s): G11C11/1673
Abstract: a memory device includes a plurality of magnetoresistive random-access memory (mram) cells including a first one-time programmable (otp) mram cell. a first otp select transistor is connected to the first otp mram cell. the first otp select transistor configured to selectively apply a breakdown current to the first otp mram cell to write the first otp mram cell to a breakdown state.
Inventor(s): Kuo-Yu HSIANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Min-Hung LEE of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/22
CPC Code(s): G11C11/2297
Abstract: a memory device includes multiple first memory cells each having a first terminal coupled to a first node and a second terminal coupled to a corresponding one in multiple first bit lines; multiple second memory cells each having a first terminal coupled to a second node and a second terminal coupled to a corresponding one in multiple second bit lines; and a driver circuit coupled between the first node and the second node, and configured to generate, in response to a first voltage at the first node, a second voltage at the second node when a memory operation is performed to one of the first memory cells. the first voltage and the second voltage have different polarity.
Inventor(s): He-Zhou WAN of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Xiu-Li YANG of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Mu-Yang YE of Nanjing City (CN) for taiwan semiconductor manufacturing company, ltd., Yan-Bo SONG of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/408, G11C5/06, G11C11/4074, G11C11/4094
CPC Code(s): G11C11/4085
Abstract: a memory device, comprising: a first driving circuit configured to provide a first current signal to a first node according to a decoder signal; a second driving circuit configured to provide a second current signal to a second node according to the decoder signal; and a modulating circuit coupled to the first node and the second node, configured to transmit each of the first current signal and the second current signal to a reference voltage terminal. a method is also disclosed herein. a method is also disclosed herein.
Inventor(s): Chi Lo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ching Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hiroki Noguchi of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yih Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/4091, G11C11/408
CPC Code(s): G11C11/4091
Abstract: an integrated circuit includes a sense amplifier connected to a bit line and a bit line bar, a first memory cell configured to store a data signal and selectively output the data signal on at least one of the bit line and the bit line bar in response to a word line signal, a first circuit connected between a first voltage terminal configured to receive a first external voltage and the bit line and having a first enable terminal configured to receive a first enable signal, wherein the first external voltage is different than the data signal, and a second circuit connected between a second voltage terminal configured to receive a second external voltage and the bit line bar and having a second enable terminal configured to receive a second enable signal, wherein the second external voltage is different than the data signal and the first external voltage.
Inventor(s): Jhon Jhy LIAW of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/412, H10B10/00
CPC Code(s): G11C11/412
Abstract: a method of manufacturing a memory circuit includes forming active regions in a semiconductor substrate, each active region defining a long axis extending in a first direction, at least some of the active regions corresponding to a first dual-port memory cell and other ones of the active regions corresponding to a second dual-port memory cell adjacent to the first dual-port memory cell, forming gate electrodes over the active regions, the gate electrodes extending in a second direction perpendicular to the first direction and including subsets in each of the first and second dual-port memory cells, forming bit line landing pads in a first metal layer above the gate electrodes, pairs of the bit line landing pads being aligned in the first direction and separated by local interconnects, and forming word lines in a second metal layer above the first metal layer, the word lines extending in the second direction.
Inventor(s): Hsin-Cheng LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tao CHOU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Ying CHIU of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chee-Wee LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/419, H01L23/48, H01L29/417, H01L29/66, H01L29/78, H10B10/00
CPC Code(s): G11C11/419
Abstract: an sram cell includes a first active region, a first gate structure, a second gate structure, and a first source/drain contact region. the first gate structure is over the first active region and forms a pull-up transistor with the first active region. the second gate structure is over the first active region and forms a write-assist transistor with the first active region. the write-assist transistor and the pull-up transistor are of a same conductivity type. the first source/drain contact region is over a source/drain of the write-assist transistor and a source/drain of the pull-up transistor.
Inventor(s): Shih-Lien Linus LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/419, G06F21/44, G06F21/75, G11C11/4074, G11C11/4096
CPC Code(s): G11C11/419
Abstract: a method of operating an integrated circuit includes powering off the integrated circuit, powering on the integrated circuit, reading data from each memory cell in the first memory cell array in response to powering on the integrated circuit, and determining whether to allow an authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array. the integrated circuit includes a first memory cell array.
Inventor(s): Po-Hao Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Fu Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chun Shih of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C13/00
CPC Code(s): G11C13/0028
Abstract: a circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. the circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.
Inventor(s): Yen-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J37/34, B08B5/00, B08B13/00, H01J37/32
CPC Code(s): H01J37/3476
Abstract: the present disclosure provides embodiments of a system and method for detecting processing chamber condition. the embodiments include performing a wafer-less processing step in a processing chamber to determine the condition of the chamber walls. based on an analysis of the residual gas resulting from the wafer-less processing step, an operator or a process controller can determine whether the chamber walls have deteriorated to such an extent as to be cleaned.
Inventor(s): Ming-Tung Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsun-Chung Kuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tung-He Chou of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, B23K26/03, B23K26/53, B23K103/00, H01L21/268, H01L21/304, H01L21/66, H01L23/544
CPC Code(s): H01L21/02021
Abstract: in some embodiments, the present disclosure relates to a method. the method includes identifying an alignment mark within a substrate using an infrared camera. a stealth laser apparatus is aligned with respect to the substrate using the alignment mark. the alignment mark was used to perform a patterning process on the substrate prior to alignment of the stealth laser apparatus. the laser apparatus is operated to form a damage region within the substrate. the damage region separates an inner region of the substrate from an outer region of the substrate structure. a force is applied to the substrate to remove at least a part of the outer region of the substrate.
Inventor(s): Szu-Ying Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ya-Wen Chiu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Po Chau of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yi Che Chan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih Ping Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., YungHao Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sen-Hong Syue of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01L21/762, H01L21/768, H01L21/8234, H01L29/66
CPC Code(s): H01L21/02321
Abstract: embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. the high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. the high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.
Inventor(s): Chun-Kai Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., JeiMing Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/033, H01L21/311, H01L21/768
CPC Code(s): H01L21/0332
Abstract: a method includes forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a young's modulus greater than about 400 mpa and a tensile stress greater than about 600 mpa, patterning the metal-containing hard mask layer to form an opening in the metal-containing hard mask layer, and etching the dielectric layer using the metal-containing hard mask layer as an etching mask. the opening extends into the dielectric layer. the opening is filled with a conductive material to form a conductive feature. the metal-containing hard mask layer is then removed.
Inventor(s): En-Ping LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ling KO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., I-Chung WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Jen CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Kai JOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Teng LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/3065, H01L21/308, H01L21/8238
CPC Code(s): H01L21/3065
Abstract: in a method of manufacturing a semiconductor device, a mask pattern is formed over a target layer to be etched, and the target layer is etched by using the mask pattern as an etching mask. the etching is performed by using an electron cyclotron resonance (ecr) plasma etching apparatus, the ecr plasma etching apparatus includes one or more coils, and a plasma condition of the ecr plasma etching is changed during the etching the target layer by changing an input current to the one or more coils.
Inventor(s): Rong Syuan FAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Jung CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Feng TUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang Yin SHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/673, H01L21/67, H01L21/677
CPC Code(s): H01L21/67309
Abstract: the present disclosure is directed to a stocker utilizing one or more storage carriers to optimize the utilization of a storage compartment within the stocker. the stocker includes one or more storage towers each including one or more shelves that may be moved from a closed position to an opened position by being pulled outward by a hook of a forking structure. this forking structure is configured to lift up a corresponding storage carrier off the shelf to be transported to a storage carrier load port to position one or more workpieces or toolpieces within the storage carrier, which is then transported back to the corresponding shelf for storage. the utilization of the forking structure along with the pull out shelves allows for a large number of storage carriers to be stored within the storage compartment of the stocker.
Inventor(s): Guancyun LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Jung CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Feng TUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang Yin SHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/677, B65D81/02, H01L21/67
CPC Code(s): H01L21/67733
Abstract: a support member system is described for association with an overhead transport system. the support member system provides a safety feature to the overhead transport system by which the overhead transport system is able to avoid damage to wafers that are contained within a wafer cassette that is unintentionally released by the overhead transport system. the support member system is able to prevent such released cassettes from impacting the ground or tools located under the overhead transport system. the support member system targets wafer cassettes that have dimensions which are different than the dimensions of wafer cassettes for which the overhead transport system was originally designed to transport. stocker systems for receiving, storing and delivering different types of wafer cassettes are also described.
Inventor(s): Wei-Hsuen Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hung En Hsu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ching Hsu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, G01R31/28, H01L21/52
CPC Code(s): H01L22/12
Abstract: methods and pad structures to test via accuracy are provided. a method according to the present disclosure includes forming a first pad and a second pad on a device component, wherein the second pad includes a via landing area and a clearance opening, providing a core substrate that includes a cavity, placing the device component in the cavity, forming a build-up film over the device component and the core substrate, forming a first contact via extending through the build-up film to contact the landing area and a second contact via extending through build-up film and the clearance opening, and performing a continuity test to determine whether the second contact via is in contact with the second pad.
Inventor(s): Chieh-Ming CHANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Kuei HSU of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Chih YEW of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/16, H01L23/00, H01L23/373, H01L23/498, H01L25/065
CPC Code(s): H01L23/16
Abstract: a chip package structure is provided. the chip package structure includes a semiconductor die formed over a package substrate and an interconnect structure bonded and electrically connected between the semiconductor die and the package substrate. the chip package structure also includes a stiffener structure formed over the package substrate and covering the semiconductor die. the metal stiffener structure has a metal lid cap portion covering the upper surface of the semiconductor die, a metal ring portion surrounding the metal lid cap portion, and a metal spacer wall portion extending between the metal ring portion and the package substrate to surround the semiconductor die.
Inventor(s): Kai-Fung Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Yang Lei of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L23/00, H01L23/498, H01L25/10
CPC Code(s): H01L23/3192
Abstract: a semiconductor package includes a semiconductor die including die connectors, a first insulating encapsulant laterally covering the semiconductor die, a die attach film (daf) overlying the first insulating encapsulant and the semiconductor die, and a redistribution structure overlying the daf and the semiconductor die. the die connectors are laterally covered by the daf, and the redistribution structure is electrically coupled to the die connectors.
Inventor(s): Ching-Chen Li of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Chi Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Chuan Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Jhan Tsai of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Wei Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ching Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L23/00, H01L23/31, H01L25/065
CPC Code(s): H01L23/49822
Abstract: a package structure includes a first semiconductor die, a second semiconductor die, an insulating encapsulant and a redistribution layer. the insulating encapsulant laterally surrounds the first semiconductor die and the second semiconductor die, wherein the insulating encapsulant includes a first portion sandwiched in between the first semiconductor die and the second semiconductor die, the first portion has a first recessed part adjacent to an edge of the first semiconductor die, and a second recessed part adjacent to an edge of the second semiconductor die. the redistribution layer is disposed on and electrically connected to the first semiconductor die and the second semiconductor die.
Inventor(s): Chia-Chen LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Tien WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chen CHU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768
CPC Code(s): H01L23/5226
Abstract: an interconnection structure includes a substrate, a first dielectric layer over the substrate, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, and a hyper via. the first dielectric layer is formed with a first metal trench. the second dielectric layer is formed with a metal plate and a connection via. the connection via interconnects the metal plate and the first metal trench. the hyper via penetrates the third dielectric layer and is connected to the metal plate. the hyper via is at least 1.5 times wider than the connection via.
Inventor(s): Pokuan Ho of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Tien Wu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Ping Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chen Chu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528
CPC Code(s): H01L23/5226
Abstract: the present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. the first metal line includes a first metal material and is within a first interlayer dielectric (ild) layer over the substrate. the hybrid metal line is also within the first ild layer. the hybrid metal line includes a pair of first metal segments that comprise the first metal material. the hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. the second metal segment is laterally between the pair of first metal segments.
Inventor(s): Zhen Yu Guan of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Wen Fu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsun-Chung Kuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, G11C11/16, H01L21/768, H01L23/528, H10N50/01, H10N50/10, H10N50/80
CPC Code(s): H01L23/5226
Abstract: the present disclosure relates to integrated chip structure. the integrated chip structure includes a lower insulating structure disposed over a lower dielectric structure surrounding one or more lower interconnects. a bottom electrode via is surrounded by one or more interior sidewalls of the lower insulating structure. the bottom electrode via includes a barrier surrounding a conductive core. a bottom electrode is arranged on the bottom electrode via, a data storage structure is over the bottom electrode, and a top electrode is over the data storage structure. the barrier includes a sidewall disposed along the one or more interior sidewalls of the lower insulating structure and a horizontally covering segment protruding outward from the sidewall to above a top surface of the lower insulating structure.
Inventor(s): Liang-Shiuan PENG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hung LU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/768
CPC Code(s): H01L23/5283
Abstract: the present disclosure describes a semiconductor structure that can provide improved gap fill. the semiconductor structure can include conductive features disposed on a first layer separated by a distance and a layer disposed over the conductive features and the first layer. the layer can include triangular-shaped peaks above each conductive feature in the conductive features and valley regions above the first layer.
Inventor(s): Cian-Yu Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Lung Chung of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Chi Chiang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Han-Tang Hung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Pei Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Yi Yang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Han Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Fu Yeh of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/768
CPC Code(s): H01L23/53238
Abstract: a semiconductor structure including a first dielectric layer and a conductive pattern is provided. the conductive pattern is disposed in the first dielectric layer, wherein the conductive pattern comprises an alloy layer and a first conductive layer, the alloy layer surrounds sidewalls and a bottom surface of the first conductive layer, a material of the alloy layer comprises an alloy of at least two metals, and at least one of the at least two metals relative to the rest of the at least two metals tends to be reacted with a dielectric material of the first dielectric layer.
Inventor(s): Hans HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Wei LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chen CHAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Yi YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Han LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Blanka MAGYARI-KOPE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L23/522
CPC Code(s): H01L23/53276
Abstract: an interconnect structure includes a conductive feature embedded in a dielectric feature. the conductive feature has a first horizontal portion and a first vertical portion. the first horizontal portion extends in a horizontal direction to terminate at two edge surfaces. the first horizontal portion includes graphene layers stacked on each other, and an intercalation material interposed among the graphene layers. the intercalation material includes a first atom dopant including one of a group 1 metal, a group 2 metal, a group 3 metal, a lanthanide series metal, an actinide series metal, and combinations thereof. the first vertical portion extends in a vertical direction and is in contact with one of the two edge surfaces of the first horizontal portion. the first vertical portion is made of a first electrically conductive metal material.
Inventor(s): Szu-Hua CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Chien HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yen WOON of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szuya LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/762, H01L21/8234, H01L27/088, H01L29/40, H01L29/51
CPC Code(s): H01L23/53295
Abstract: a semiconductor device and an isolation structure and a contact etch stop layer thereof are provided. according to an embodiment of the present disclosure, a semiconductor device is provided, which includes a first dielectric layer and a second dielectric layer. the first dielectric layer is deposited on the sidewall of an active device or formed in a trench of a gate structure. the second dielectric layer covers the first dielectric layer, wherein the dielectric constant of the first dielectric layer is between 2 and 2.5, and the dielectric constant of the second dielectric layer is less than or equal to 4. in some embodiments, a dielectric bilayer is composed of amorphous boron nitride and crystalline boron nitride.
Inventor(s): Marcus Johannes Henricus Van Dal of Linden (BE) for taiwan semiconductor manufacturing company, ltd., Gerben Doornbos of Kessel-Lo (BE) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/535, H01L21/74, H01L23/48, H01L23/482, H01L23/485, H01L27/088, H01L27/12, H01L29/417, H01L29/66
CPC Code(s): H01L23/535
Abstract: the present disclosure relates to an integrated chip including a semiconductor structure including a gate, a first source/drain region, and a second source/drain region. a power rail is disposed under the gate, the first source/drain region, and the second source/drain region. the power rail is in electrical connection with the first source/drain region.
Inventor(s): Chien-Hsun Chen of Pingtung County (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hsun Lee of Hsin-chu County (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Shi Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jiun-Yi Wu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Shou-Yi Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Ding Wang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L23/00, H01L23/498, H01L25/065
CPC Code(s): H01L23/5386
Abstract: a semiconductor package is provided. the semiconductor package includes: semiconductor dies, separated from one another, and including die i/os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die i/os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die i/os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die i/os and rout the die i/os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region.
Inventor(s): Yu-Huan Chen of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Yi Tang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ching Hsu of Chung-Ho City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/56, H01L25/065
CPC Code(s): H01L23/5389
Abstract: semiconductor package and method of manufacturing are presented herein. in an embodiment, a device is provided that includes a first semiconductor component embedded in a first core substrate, a first redistribution layer on a first side of the first core substrate, a second redistribution layer on a second side of the first core substrate opposite the first side, a first resin film over the second redistribution layer, a second semiconductor component embedded in a second core substrate, a third redistribution layer on a third side of the second core substrate, wherein the third redistribution layer is bonded to the second redistribution layer by the first resin film, a fourth redistribution layer on a fourth side of the second core substrate opposite the third side, and a through hole via extending through the first redistribution layer, the first core substrate, the second redistribution layer, the third redistribution layer, the second core substrate, and the fourth redistribution layer.
Inventor(s): Sung-Hsin YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Yuan CHANG LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Chieh CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chuan-Cheng TSOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/02, H01L21/3105, H01L21/67
CPC Code(s): H01L23/562
Abstract: a stress modulating device including a semiconductor substrate, a first insulating layer formed over a first side of the semiconductor substrate, a second insulating layer formed over the first insulating layer, a third insulating layer formed over a second side of the semiconductor substrate, a fourth insulating layer formed over the third insulating layer, and a fifth insulating layer formed over the fourth insulating layer for incorporation in multi-stack package assemblies for reducing stress, strain, and/or warpage on the active elements within the package assembly.
Inventor(s): Mao-Nan Wang of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Chih Hsin Yang of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Wei Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L23/564
Abstract: semiconductor devices having dummy regions with dummy fill structures that vary in lateral dimensions and methods for forming the semiconductor devices are provided herein. the semiconductor devices may include a through silicon via extending through a substrate of the semiconductor device, an active device in or on the substrate, and a dummy region of the substrate separating the through silicon via and the active device, the dummy region including dummy fill structures, wherein the dummy fill structures have lateral dimensions measured in a first direction from the through silicon via to the active device, wherein the lateral dimensions of the dummy fill structures varying in the first direction.
Inventor(s): Ching-Wen Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Che Ho of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L23/31, H01L23/538
CPC Code(s): H01L23/564
Abstract: a semiconductor structure and a method of forming the same are disclosed. a method of forming a semiconductor structure includes the following operations. an insulating layer is formed over a substrate. a metal feature is formed in the insulating layer. an argon-containing plasma treatment is performed to the insulating layer and the metal feature.
Inventor(s): Jiun Yi Wu of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/02, H01L21/48, H01L21/56, H01L21/768, H01L23/31, H01L23/498, H01L23/538
CPC Code(s): H01L24/13
Abstract: semiconductor devices and methods of manufacture are described herein. the methods include forming a local organic interconnect (loi) by forming a stack of conductive traces embedded in a passivation material, forming first and second local contacts over the passivation material, the second local contact being electrically coupled to the first local contact by a first conductive trace of the stack. the methods further include forming a backside redistribution layer (rdl) and a front side rdl on opposite sides of the loi with tmvs electrically coupling the backside and front side rdls to one another. first and second external contacts are formed over the backside rdl for mounting of semiconductor devices, the first and second external contacts being electrically connected to one another by the loi. an interconnect structure is attached to the front side rdl for further routing. external connectors electrically coupled to the external contacts at the backside rdl.
Inventor(s): Kuo-Chiang Ting of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jian-Wei Hong of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/31, H01L25/00
CPC Code(s): H01L25/0657
Abstract: a semiconductor device includes a first die, a second die and a third die. the first die has a first side including a plurality of first connecting structures and a second side including a plurality of second connecting structures, where the first side is opposite to the second side. the second die has a third side including a plurality of third connecting structures, where the plurality of third connecting structures are in contact with the plurality of first connecting structures of the first die. the third die has a fourth side including a plurality of fourth connecting structures, where the plurality of fourth connecting structures are in contact with the plurality of second connecting structures of the first die. a first pitch of the plurality of first connecting structures and a second pitch of the plurality of third connecting structures are less than a third pitch of the plurality of fourth connecting structures.
Inventor(s): Han-Tang HUNG of ShinChu (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Yi YANG of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Han LEE of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/18, H01L21/78, H01L23/00, H01L23/538, H01L25/00
CPC Code(s): H01L25/18
Abstract: embodiments of the present disclosure provide a semiconductor package. in one embodiment, the semiconductor package includes a first integrated circuit die having a first circuit design, and the first integrated circuit die comprises a first device layer and a first interconnect structure. the semiconductor package also includes a second integrated circuit die having a second circuit design different than the first circuit design, and the second integrated circuit die comprises a second device layer and a second interconnect structure having a first side in contact with the first device layer and a second side in direct contact with the first interconnect structure of the first integrated circuit die. the semiconductor package further includes a substrate having a first side bonded to the first interconnect structure, wherein the substrate has an opening extending through entire thickness of the substrate, and the second integrated circuit die is surrounded by a filling material.
Inventor(s): Yi-Wen Wu of Xizhi City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Liang Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Techi Wong of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Ting Hung of Sanchong City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hao Tsai of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Po-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/00, H01L21/56, H01L23/00, H01L25/18
CPC Code(s): H01L25/50
Abstract: packaged devices and methods of manufacturing the devices are described herein. the packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (rdl) structure. the packaged devices may be formed with a heterogeneous three-dimensional (3d) fan-out system-in-package (sip) structure having small profiles and can be formed using a single carrier substrate.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/00, H01L21/56, H01L21/768, H01L23/00, H01L23/31, H01L23/48, H01L23/538, H01L25/03, H01L25/065, H01L25/10, H01L25/18
CPC Code(s): H01L25/50
Abstract: a method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. a first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. the opening is then extended through the first etch stop layer. a second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. the second etching process stops on a second etch stop layer in the plurality of gap-filling layers. the method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via.
Inventor(s): Hui-Hsien WEI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Han-Ting TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tai-Yen PENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Teng DAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Min LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chih LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chih WEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B61/00, B82Y25/00, G11C11/16, H01F41/30, H10N50/01, H10N50/10, H10N50/80, H10N50/85
CPC Code(s): H10B61/00
Abstract: in a method of manufacturing a semiconductor device, a magnetic random access memory (mram) cell structure is formed. the mram cell structure includes a bottom electrode, a magnetic tunnel junction (mtj) stack and a top electrode. a first insulating cover layer is formed over the mram cell structure. a second insulating cover layer is formed over the first insulating cover layer. an interlayer dielectric (ild) layer is formed. a contact opening in the ild layer is formed, thereby exposing the second insulating cover layer. a part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. a conductive layer is formed in the opening contacting the top electrode.
Inventor(s): Jhih-Bin CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wan-Chen CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/306
CPC Code(s): H10D1/696
Abstract: a semiconductor device and a manufacturing method thereof are provided. the semiconductor device includes a top electrode layer, a bottom electrode layer, an insulator layer and a hard mask layer. the insulator layer is disposed between the top electrode layer and the bottom electrode. the top electrode layer, the insulator layer and the bottom electrode layer form a metal-insulator-metal structure. the hard mask layer stacks on the top electrode layer. the insulator layer protrudes from a first sidewall of the top electrode layer and a second sidewall of the bottom electrode layer.
Inventor(s): Kuei-Lin CHAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Ting YEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Ting YEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Yun PENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Chu LIN of Pingtung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, C23C16/455, H01L21/02
CPC Code(s): H10D30/014
Abstract: embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. the method includes removing a first semiconductor layer disposed between a second semiconductor layer and a third semiconductor layer and performing an oxide refill process to form a seamless dielectric material between the second and third semiconductor layers. the oxide refill process includes exposing the second and third semiconductor layers to a silicon-containing precursor at a first flow rate for a first duration to form a monolayer, and exposing the monolayer to an oxygen-containing precursor at a second flow rate for a second duration to form the seamless dielectric material, the second flow rate is about twice to about 20 times the first flow rate, and the second duration is about twice to about 20 times the first duration.
Inventor(s): Tzu-Ging LIN of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Yu TAI of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Liang LAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Chen WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shun-Hui YANG of Jungli City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/423, H01L29/775
CPC Code(s): H10D30/014
Abstract: a continuous metal on diffusion edge (cmode) may be used to form a cmode structure in a semiconductor device after a replacement gate process that is performed to replace the polysilicon dummy gate structures of the semiconductor device with metal gate structures. the cmode process described herein includes removing a portion of a metal gate structure (as opposed to removing a portion of a polysilicon dummy gate structure) to enable formation of the cmode structure in a recess left behind by removal of the portion of the metal gate structure.
Inventor(s): Yu-Cheng SHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Jie SHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/8234, H01L29/78
CPC Code(s): H10D30/024
Abstract: a method of manufacturing a semiconductor device includes forming a plurality of work function metal layers and an oxygen absorbing layer over a channel region of the semiconductor device, including forming a first work function metal layer over the channel region, forming an oxygen absorbing layer over the first work function metal layer, forming a second work function metal layer over the oxygen absorbing layer. a gate electrode metal layer is formed over the plurality of work function metal layers. the work function metal layers, oxygen absorbing layer, and gate electrode metal layer are made of different materials.
Inventor(s): Wei-Chih KAO of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Che CHIANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Sheng LIANG of Puyan Township (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Hua PAN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66
CPC Code(s): H10D30/0243
Abstract: a dummy fin described herein includes a low dielectric constant (low-k or lk) material outer shell. a leakage path that would otherwise occur due to a void being formed in the low-k material outer shell is filled with a high dielectric constant (high-k or hk) material inner core. this increases the effectiveness of the dummy fin to provide electrical isolation and increases device performance of a semiconductor device in which the dummy fin is included. moreover, the dummy fin described herein may not suffer from bending issues experienced in other types of dummy fins, which may otherwise cause high-k induced alternating current (ac) performance degradation. the processes for forming the dummy fins described herein are compatible with other fin field effect transistor (finfet) formation processes and are be easily integrated to minimize and/or prevent polishing issues, etch back issues, and/or other types of semiconductor processing issues.
Inventor(s): Shih-Yen LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Jia CHANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/18, H01L29/417, H01L29/423, H01L29/786
CPC Code(s): H10D30/031
Abstract: a method includes forming a gate electrode in contact with a gate dielectric layer; forming a first 2-d material buffer layer over the gate dielectric layer; forming a 2-d material channel layer over the first 2-d material buffer layer; and forming source/drain electrodes over source/drain regions of the 2-d material channel layer.
Inventor(s): Tzu-Wen Shih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Der-Ming Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Shao Hsieh of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hsiang Tai of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/778, H01L29/20, H01L29/205, H01L29/40, H01L29/423, H01L29/66
CPC Code(s): H10D30/475
Abstract: a semiconductor device comprises an insulating region surrounding an active area having a channel direction and a transverse direction that is transverse to the channel direction. a source region and a drain region are disposed in the active area, and are spaced apart along the channel direction. a channel is disposed in the active area and is interposed between the source region and the drain region. the channel comprises a two-dimensional electron gas (2deg). a gate line is oriented along the transverse direction and is disposed on the channel and has a gate width in the channel direction. the gate line comprises gate material. a gate line terminus is disposed at each end of the gate line. each gate line terminus comprises the gate material. each gate line terminus has a width in the channel direction that is at least 1.2 time the gate width.
Inventor(s): Ting-Hsiang CHANG of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Ting KO of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Shu Ling LIAO of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Sung-En LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D30/62
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a source/drain (s/d) feature disposed over a substrate and between two adjacent semiconductor layers, an inner spacer disposed between and in contact with one semiconductor layer and the substrate, and a dielectric layer structure disposed between the s/d feature and the substrate. the dielectric layer structure includes a first dielectric layer in contact with the inner spacer and the substrate, and a second dielectric layer nested within the first dielectric layer, wherein a bottom surface and sidewall surfaces of the second dielectric layer are in contact with the first dielectric layer.
Inventor(s): Yuan Tsung TSAI of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yao Jui KUO of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wei FAN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ying Ming WANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hao CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ling-Sung WANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/417, H01L29/66
CPC Code(s): H10D30/62
Abstract: a semiconductor device and method of manufacturing the same are provided. the semiconductor device includes a first fin and a gate electrode. the first fin extends along a first direction. the gate electrode has a sidewall extending along a second direction different from the first direction. the sidewall of the gate electrode defines an indentation adjacent to the first fin in a top view.
Inventor(s): Jhu-Min Song of Nantou City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Kai Ciou of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Te Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Chou Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jiou-Kang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Huan Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chih Chou of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Fei-Yun Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/311, H01L21/762
CPC Code(s): H10D30/62
Abstract: some embodiments relate to an integrated circuit device incorporating an etched recessed gate dielectric region. the integrated circuit device includes a substrate including a first upper surface, a gate dielectric region disposed at the first upper surface of the substrate and extending into the substrate, and a gate structure disposed over the gate dielectric region. the gate dielectric region includes a second upper surface and forms a recess extending below the second upper surface. the second upper surface includes a perimeter portion surrounding the recess. the gate structure completely covers the second upper surface of the gate dielectric region and extends into the recess.
Inventor(s): Wen-Yi Lin of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Shi-Sheng Hu of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Chi Chen of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D30/6211
Abstract: field effect transistor (fet) devices having a heterogeneous/segmented channel region and methods for fabricating the same are provided. in one example, a fin-like field effect transistor (finfet) device includes a substrate, a fin structure disposed on the substrate, a segmented channel region formed in the fin structure, two source/drain (s/d) regions separated by the segmented channel region, and a gate structure wrapping around the segmented channel region. the segmented channel region further includes multiple channel segments sequentially arranged in the segmented channel region, and the multiple channel segments include a first channel segment and a second channel segment. the first channel segment includes a first channel barrier material dispersed therein and has a first energy barrier, and the first energy barrier is at least 0.1 electron volts (ev) in a carrier flow path between the two s/d regions when the finfet device is not activated for operation.
Inventor(s): Ya-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi Yuen Pak of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Hong Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Han-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsien Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L27/088, H01L27/092, H01L29/08, H01L29/423, H01L29/66
CPC Code(s): H10D30/6211
Abstract: a semiconductor structure according to the present disclosure includes a substrate, a first base fin and a second base fin arising from the substrate, an isolation structure disposed between the first base fin and the second base fin, first channel members disposed over the first base fin, second channel members disposed over the second base fin, a region isolation feature extending into the substrate, a first gate structure wrapping around each of the first channel members, second gate structure wrapping around each of the second channel members, a first gate cut feature extending through the first gate structure and into the isolation feature, and a second gate cut feature extending though the second gate structure and into the isolation feature. each of the first gate cut feature and the second gate cut feature are spaced apart from the region isolation feature.
Inventor(s): Chien-Chia Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Che-Yu Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chiang Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chii-Horng Li of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L29/66, H01L29/78
CPC Code(s): H10D30/6706
Abstract: embodiments with present disclosure provides a gate-all-around fet device including a patterned or lowered bottom dielectric layer. the bottom dielectric layer prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.
Inventor(s): Chen-Ming Lee of Yangmei City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chieh Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., I-Wen Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Kai Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Yun Wang of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8238, H01L23/528, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D30/6729
Abstract: a semiconductor die and the method of forming the same are provided. the semiconductor die includes a first interconnect structure, a second interconnect structure including a conductive feature, and a device layer between the first interconnect structure and the second interconnect structure. the device layer includes a semiconductor fin, a first gate structure on the semiconductor fin, a source/drain region adjacent the first gate structure, and a shared contact extending through the semiconductor fin to be electrically connected to the source/drain region and the first gate structure. the conductive feature contacts the shared contact.
Inventor(s): Kuei-Yu Kao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chiung-Yu Cho of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Ching Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L29/49, H01L29/66
CPC Code(s): H10D30/6735
Abstract: semiconductor devices and methods for forming the semiconductor devices using diffusion cap layers are provided. the semiconductor devices include a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers, and a plurality of diffusion cap layers disposed between and separating the plurality of semiconductor layers and the gate structure. in some embodiments, the plurality of diffusion cap layers function as diffusion barriers for the plurality of semiconductor layers.
Inventor(s): Chien-Chia CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chiang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hua YU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chii-Horng LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Ting KO of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Sung-En LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Shan CHEN of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., De-Fang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L27/088, H01L29/06, H01L29/08, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H10D30/6735
Abstract: embodiments with present disclosure provides a gate-all-around fet device including extended bottom inner spacers. the extended bottom inner prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.
Inventor(s): Chao-Wei HSU of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/3065, H01L29/06, H01L29/08, H01L29/417, H01L29/66, H01L29/786
CPC Code(s): H10D30/6735
Abstract: the present disclosure describes a semiconductor device having a channel structure with profile control. the semiconductor device includes a fin structure on a substrate. the fin structure includes a bottom portion on the substrate and a top portion including multiple semiconductor layers. the semiconductor device further includes a gate structure wrapped around the multiple semiconductor layers and a source/drain (s/d) structure on the bottom portion of the fin structure and in contact with the plurality of semiconductor layers. the s/d structure extends into end portions of the multiple semiconductor layers.
Inventor(s): Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao Wen Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Ching Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L29/06, H01L29/66, H01L29/786
CPC Code(s): H10D30/6735
Abstract: a semiconductor device includes an active gate structure extending along a first lateral direction. the semiconductor device includes an inactive gate structure also extending along the first lateral direction. the semiconductor device includes a first epitaxial structure disposed between the active gate structure and the inactive gate structure along a second lateral direction perpendicular to the first lateral direction. the active gate structure wraps around each of a plurality of channel layers that extend along the second direction, and the inactive gate structure straddles a semiconductor cladding layer that continuously extends along a first sidewall of the first epitaxial structure and across the plurality of channel layers.
Inventor(s): Yu-Yu Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Zheng-Yang Pan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ya-Wen Chiu of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D62/121
Abstract: various embodiments of the present disclosure provide a semiconductor device structure. in one embodiment, the semiconductor device structure includes a plurality of semiconductor layers vertically stacked, a plurality of inner spacers, each being disposed between two adjacent semiconductor layers. the structure also includes a source/drain feature in contact with each of the inner spacers, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, and a cap layer disposed between the source/drain feature and each of the plurality of the semiconductor layers.
Inventor(s): Chien-Wei LEE of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-I KUO of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hua YU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L27/088, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D62/151
Abstract: a semiconductor device and a method of fabricating the semiconductor device are disclosed. the semiconductor device includes a substrate, first and second nanostructured channel regions disposed on the substrate, a gate structure surrounding the first and second nanostructured channel regions, an inner gate spacer disposed along a sidewall of the gate structure and between the first and second nanostructured channel regions, and a source/drain (s/d) region. the s/d region includes an epitaxial liner disposed along sidewalls of the first and second nanostructured channel regions and the inner gate spacer and a germanium-based epitaxial region disposed on the epitaxial liner. the semiconductor further includes an isolation structure disposed between the germanium-based epitaxial region and the substrate.
Inventor(s): Cheng-Ta Wu of Shueishang Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/311, H01L21/84, H01L27/12
CPC Code(s): H10D64/015
Abstract: various embodiments of the present disclosure are directed towards an integrated circuit (ic). the ic includes a pair of source/drain regions in a substrate. a gate dielectric layer is on the substrate and laterally between the source/drain regions. a gate electrode overlies the gate dielectric layer. a sidewall liner is disposed along sidewalls of the gate electrode and along an upper surface of the substrate. a sidewall spacer overlies the substrate and is on sidewalls and an upper surface of the sidewall liner. the sidewall spacer has a pair of segments respectively on opposite sides of the gate electrode. the sidewall spacer consists essentially of silicon oxycarbonitride. a dielectric constant of the sidewall spacer is greater than that of the sidewall liner.
Inventor(s): Yu-Chang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Kang HO of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Yin CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Yu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On CHUI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/265, H01L21/324, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D64/018
Abstract: a semiconductor device structure and methods of forming the same are described. the structure includes a first semiconductor material disposed over a substrate and a dielectric layer disposed on the first semiconductor material. the dielectric layer includes a dopant. the structure further includes a second semiconductor material disposed on the dielectric layer, a first semiconductor layer in contact with the second semiconductor material, and a first dielectric spacer in contact with the first semiconductor layer, wherein the first dielectric spacer includes the dopant.
Inventor(s): Ming-Heng Tsai of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Sheng Liang of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L23/528, H01L27/088, H01L29/06, H01L29/423, H01L29/775, H01L29/786, H10B10/00
CPC Code(s): H10D64/251
Abstract: a semiconductor device includes a first transistor, a second transistor and an interconnect structure. the interconnect structure is disposed over the first transistor and the second transistor, wherein the interconnect structure includes a first conductive via electrically connecting a first source/drain contact of the first transistor to a second gate structure of the second transistor. the first conductive via is in contact with a top surface of the first source/drain contact and a side surface of the first source/drain contact.
Inventor(s): Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L23/528, H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D64/256
Abstract: a semiconductor device includes circuit cells, a vss conductor, a first vdd conductor, and a second vdd conductor. each of the circuit cells comprises at least one n-type transistor and at least one p-type transistor. the vss conductor is under the circuit cells. the vss conductor is electrically connected to source/drain features of the n-type transistors. the first vdd conductor is under the circuit cells. the first vdd conductor is electrically connected to source/drain features of the p-type transistors. the second vdd conductor is over the circuit cells. the second vdd conductor is electrically connected to the source/drain features of the p-type transistors and the first vdd conductor.
Inventor(s): Yi-Jing LI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsin KO of Fongshan City (TW) for taiwan semiconductor manufacturing company, ltd., Clement Hsingjen WANN of Carmel NY (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/49, H01L21/8238, H01L27/092, H01L29/40, H01L29/66, H01L29/78
CPC Code(s): H10D64/667
Abstract: in a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first barrier layer is formed on the gate dielectric layer, a second barrier layer is formed on the first barrier layer, a first work function adjustment layer is formed on the second barrier layer, the first work function adjustment layer and the second barrier layer are removed. after the first work function adjustment layer and the second barrier layer are removed, a second work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the second work function adjustment layer.
Inventor(s): Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao Wen Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Shan Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Ching Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/49, H01L21/02, H01L21/28, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H10D64/679
Abstract: a semiconductor device includes a channel structure, extending along a first lateral direction, that is disposed over a substrate. the semiconductor device includes a gate structure, extending along a second lateral direction perpendicular to the first lateral direction, that straddles the channel structure. the semiconductor device includes an epitaxial structure, coupled to the channel structure, that is disposed next to the gate structure. the semiconductor device includes a first gate spacer and a second gate spacer each comprising a first portion disposed between the gate structure and the epitaxial structure along the first lateral direction. the semiconductor device includes an air gap interposed between the first portion of the first gate spacer and the first portion of the second gate spacer. the air gap exposes a second portion of the first gate spacer that extends in the first lateral direction.
Inventor(s): Kuan-Ting PAN of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Wen CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/768, H01L27/088
CPC Code(s): H10D84/038
Abstract: a semiconductor device structure, along with methods of forming such, are described. the structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. the dielectric feature has a first surface. the structure further includes a first conductive layer disposed on the first gate electrode layer. the first conductive layer has a second surface. the structure further includes a second conductive layer disposed on the second gate electrode layer. the second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. the structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. the dielectric layer is disposed between the third conductive layer and the fourth conductive layer.
Inventor(s): Ming-Heng Tsai of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Sheng Liang of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/768, H01L21/8234, H01L23/522
CPC Code(s): H10D84/83
Abstract: an integrated circuit and a formation method thereof are provided. the integrated circuit includes: an active structure, formed on a semiconductor substrate, and extending along a first lateral direction; first and second gate lines, extending along a second lateral direction on the semiconductor substrate, and crossing the active structure; an isolation wall, extending along the second lateral direction between the first and second gate lines, and cutting through the active structure; a first source/drain contact, extending along the second lateral direction between the first gate line and the isolation wall, and crossing the active structure; and a first source/drain via, disposed on the first source/drain contact, and laterally extending along the first direction to overlap the isolation wall.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Hua PAN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234, H01L29/06, H01L29/66, H01L29/78
CPC Code(s): H10D84/834
Abstract: transistors of different types of electronic devices on the same semiconductor substrate are configured with different transistor attributes to increase the performance of the different types of electronic devices. fin height, shallow source drain (ssd) height, source or drain width, and/or one or more other transistor attributes may be co-optimized for the different types of electronic devices by various semiconductor manufacturing processes such as etching, lithography, process loading, and/or masking, among other examples.
Inventor(s): Georgios Vellianitis of Heverlee (BE) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8234, H01L21/8238, H01L29/06
CPC Code(s): H10D84/853
Abstract: a manufacturing method of a complementary metal-oxide-semiconductor device includes forming semiconductor fins over a semiconductor substrate; forming nanosheets over the semiconductor substrate; forming a gate structure contacting the semiconductor fins and the nanosheets, where a contact area of the gate structure with the semiconductor fins extends mostly along a () crystallographic surface of a semiconductor material of the semiconductor fins, and a contact area of the gate structure with the nanosheets extends mostly along a () crystallographic surface of a semiconductor material of the nanosheets.
Inventor(s): Yi-Chun LIU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yi CHENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Te Tu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chee-Wee LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/768, H01L21/822, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H10D84/856
Abstract: a method includes following steps. a first transistor is formed on a substrate. a first dielectric layer is formed over the first transistor. a first trench is formed in the first dielectric layer. an amorphous semiconductor layer is deposited in the first trench and over the first dielectric layer. the amorphous semiconductor layer is crystallized into a crystalline semiconductor layer. a second transistor is formed over the crystalline semiconductor layer.
Inventor(s): Hung-Li Chiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-En Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jer-Fu Wang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Ching Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Iuliana Radu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Sheng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/06, H01L21/8258
CPC Code(s): H10D88/00
Abstract: semiconductor structures and formation processes thereof are provided. a semiconductor structure of the present disclosure includes a semiconductor substrate, a plurality of transistors disposed on the semiconductor substrate and comprising a plurality of gate structures extending lengthwise along a first direction, a metallization layer disposed over the plurality of transistors, the metallization layer comprising a plurality of metal layers and a plurality of contact vias, a dielectric layer over the metallization layer, a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric layer, a semiconductor layer disposed conformally over the plurality of dielectric fins, a source contact and a drain contact disposed directly on the semiconductor layer, and a gate structure disposed over the semiconductor layer and between the source contact and the drain contact.
Inventor(s): Yi-Hui Chen of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Lii Huang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsiao Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ming Chen Hung of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yen Wei Tseng of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chen Li of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02
CPC Code(s): H10D89/10
Abstract: a semiconductor structure a method of fabricating thereof including a substrate having a device region and a dummy region. a first active region is disposed over the substrate in the device region and a second active region is over the substrate in the dummy region. a first operational gate structure over the first active region and a first non-operational gate structure over the second active region. a first epitaxial region of an n-type dopant is adjacent the first operation gate structure; and a second epitaxial region of an n-type dopant is adjacent the first non-operational gate structure.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on March 6th, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
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- CPC H10D62/151
- H01L21/84
- CPC H10D64/015
- H01L21/265
- H01L21/324
- CPC H10D64/018
- CPC H10D64/251
- CPC H10D64/256
- CPC H10D64/667
- H01L21/28
- CPC H10D64/679
- CPC H10D84/038
- CPC H10D84/83
- CPC H10D84/834
- CPC H10D84/853
- H01L21/822
- CPC H10D84/856
- H01L27/06
- H01L21/8258
- CPC H10D88/00
- H01L27/02
- CPC H10D89/10