Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on June 20th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on June 20th, 2024
Taiwan Semiconductor Manufacturing Company, Ltd.: 55 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L29/66 (10), H01L23/00 (10), H01L29/78 (8), H01L21/8234 (8), H01L21/56 (6) H01L29/0649 (2), H01L24/19 (2), H01L25/0657 (2), H01L29/785 (2), H01L27/14629 (1)
With keywords such as: layer, structure, semiconductor, substrate, portion, region, metal, gate, device, and dielectric in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Kuo-Ming Wu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Lung Lin of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hau-Yi Hsiao of Chiayi City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chau Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yuan Tsai of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B23K26/361, B23K26/035, B23K26/062, H01L21/02, H01L21/66
CPC Code(s): B23K26/361
Abstract: in some embodiments, the present disclosure relates to a method of trimming an annular portion of a wafer. the method includes aligning the wafer over a wafer chuck. the method uses a rotating blade having a first rotational speed to remove the annular portion from an upper surface of the wafer. while the rotating blade is removing the annular portion of the upper surface of the wafer, measuring a parameter of the wafer at a position adjacent to the rotating blade. lastly, the method involves changing the first rotation speed of the rotating blade to a second rotational speed when the parameter is greater than a predetermined threshold.
Inventor(s): Wei-Jie Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ching Lo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Pin Yuan of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chih Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yu Kuo of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Yang Lei of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B32B38/18, H01L21/48, H01L23/00
CPC Code(s): B32B38/1858
Abstract: a lamination chuck for lamination of film materials includes a support layer and a top layer. the top layer is disposed on the support layer. the top layer includes a polymeric material having a shore a hardness lower than a shore hardness of a material of the support layer. the top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.
Inventor(s): Chia-Chen Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chiting Cheng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-jer Hsieh of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yangsyu Lin of New Taipei CIty (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01R19/165, H02H1/00, H02H9/02
CPC Code(s): G01R19/16519
Abstract: a power detection circuit is provided. the power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. the output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. the output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. a current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.
Inventor(s): Wen-Hao Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/12, G02B6/122
CPC Code(s): G02B6/12002
Abstract: the present disclosure provides an embodiment of a photonics structure that includes a ring optical waveguide on a substrate; a rail optical waveguide configured to couple a light into the ring optical waveguide; and enhancement features configured around the ring optical waveguide and the rail optical waveguide to enhancement the photonic structure.
Inventor(s): Feng-Wei KUO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Shiang Liao of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/124, G02B6/136, H01L23/00, H01L25/00, H01L25/065
CPC Code(s): G02B6/1245
Abstract: a semiconductor package and a manufacturing method thereof are provided. a die stack in the semiconductor package includes a photonic die and an electronic die stacked on the photonic die by a face-to-face manner. a convex lens is disposed at a back surface of the electronic die, and is formed in an oval shape, such that optical beams can be collimated to have circular beam shape, as passing through the convex lens. in some embodiments, the semiconductor package includes more of the die stacks, and includes an interposer lying below the die stacks. in these embodiments, tilted reflectors are formed in the photonic dies and the interposer, to set up vertical optical paths between the interposer and the photonic dies, and lateral optical paths in the interposer. in this way, optical communication between the photonic dies can be established.
Inventor(s): Hsu-Ting HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hsiang LO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Gun LIU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/36, G03F1/78, G03F7/20
CPC Code(s): G03F1/36
Abstract: a method for mask data synthesis and mask making includes calibrating an optical proximity correction (opc) model by adjusting a plurality of parameters including a first parameter and a second parameter, wherein the first parameter indicates a long-range effect caused by an electron-beam lithography tool for making a mask used to manufacture a structure, and the second parameter indicates a geometric feature of a structure or a manufacturing process to make the structure, generating a device layout, calculating a first grid pattern density map of the device layout, generating a long-range correction map, at least based on the calibrated opc model and the first grid pattern density map of the device layout, and performing an opc to generate a corrected mask layout, at least based on the generated long-range correction map and the calibrated opc model.
Inventor(s): Yong-Liang JIN of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Ya-Qi MA of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Wei LI of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Di FAN of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G05F1/565, G05F1/46
CPC Code(s): G05F1/565
Abstract: a device includes a voltage regulator circuit configured to pull up a voltage at an output terminal to equal to half of a supply voltage; multiple first transistors coupled between the output terminal and a voltage terminal providing the supply voltage; and a control circuit configured to pull down gate voltages of the first transistors from the supply voltage to a voltage level between the supply voltage and a ground voltage at a first time. the first transistors are configured to pull up the voltage at the output terminal to the supply voltage at a second time.
Inventor(s): Jerry Chang Jui KAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hsiung CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jack LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chen CHIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Hsiang MA of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Hsing WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F1/10, G06F30/396
CPC Code(s): G06F1/10
Abstract: a clock distribution system includes a clock mesh structure which has first metal patterns extending along a first axis, second metal patterns extending along a second axis, third metal patterns extending along a third axis. the first metal patterns, second metal patterns, and third metal patterns are electrically coupled with each other. the second axis is transverse to the first axis. the third axis is oblique to both the first axis and the second axis. the first metal patterns include a main first metal pattern, and other first metal patterns. the second metal patterns include a main second metal pattern, and other second metal patterns. the third metal patterns include a main third metal pattern, and other third metal patterns. the main third metal pattern overlaps the main first metal pattern and the main second metal pattern, without overlapping the other first metal patterns or the other second metal patterns
Inventor(s): Kinshuk Khare of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hidehiro Fujiwara of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chang Zhao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Haruki Mori of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F7/544, G06F5/01
CPC Code(s): G06F7/5443
Abstract: a method for performing a shift last multiplication and accumulation (mac) process. a processing circuit can multiply a first input by a first bit of a second input to obtain a first intermediate output. the processing circuit can multiply a third input by a first bit of a fourth input to obtain a second intermediate output. the processing circuit can sum the first and second intermediate outputs to obtain a first sum. the processing circuit can multiply the first input by a second bit of the second input to obtain a third intermediate output. the processing circuit can multiply the third input by a second bit of the fourth input to obtain a fourth intermediate output. the processing circuit can sum the third and fourth intermediate outputs to obtain a second sum. the processing circuit can generate an output by accumulating the first sum and the second sum.
Inventor(s): Shih-Lien Linus LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F21/75, G11C11/412, G11C11/418, G11C11/419, H03K19/003, H04L9/00, H04L9/32
CPC Code(s): G06F21/755
Abstract: methods and apparatus for protecting a physical unclonable function (puf) generator are disclosed. in one example, a puf generator is disclosed. the puf generator includes a puf cell array, a puf control circuit and a reset circuit. the puf cell array comprises a plurality of bit cells. each of the plurality of bit cells is configurable into at least two different stable states. the puf control circuit is coupled to the puf cell array and is configured to access each of the plurality of bit cells to determine one of the at least two different stable states upon a power-up of the plurality of bit cells, and generate a puf signature based on the determined stable states of the plurality of bit cells. the reset circuit is coupled to the puf cell array and is configured to set the plurality of bit cells to represent their initialization data based on an indication of a voltage tempering event of a supply voltage of the puf cell array.
Inventor(s): Wei-Yi HU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Ming CHAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yeh YU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F30/398, G06F115/08, H01L27/02, H01L29/423
CPC Code(s): G06F30/392
Abstract: integrated circuits (ic) are provided. an ic includes a plurality of macros and a top channel arranged between the macros. each macro includes a plurality of transistors with different gate lengths. the top channel includes a plurality of first and second sub-channels. each first sub-channel is arranged between a first macro and a second macro, and is formed by a plurality of first dummy boundary cells. each second sub-channel is arranged between two of the second macros, and is formed by a plurality of second dummy boundary cells. the macro boundaries of the first macros are formed by the first dummy boundary cells, and the macro boundaries of the second macros are formed by the second dummy boundary cells. a first gate length of dummy patterns within the first dummy boundary cells is different from a second gate length of dummy patterns within the second dummy boundary cells.
Inventor(s): Po-Sheng Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yangsyu Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kao-Cheng Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng Hung Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jonathan Tsung-Yung Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C5/14, G11C16/30
CPC Code(s): G11C5/14
Abstract: disclosed herein are related to an integrated circuit including a semiconductor layer. in one aspect, the semiconductor layer includes a first region, a second region, and a third region. the first region may include a circuit array, and the second region may include a set of interface circuits to operate the circuit array. a side of the first region may face a first side of the second region along a first direction. the third region may include a set of header circuits to provide power to the set of interface circuits through metal rails extending along a second direction. a side of the third region may face a second side of the second region along the second direction. in one aspect, the first side extending along the second direction is shorter than the second side extending along the first direction, and the metal rails are shorter than the first side.
Inventor(s): Fa-Shen Jiang of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hsia-Wei Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsun-Chung Kuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Dang Trinh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yuan Tsai of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/16, G11C11/56, H10B53/30, H10B61/00, H10B63/00
CPC Code(s): G11C11/161
Abstract: various embodiments of the present disclosure are directed towards a memory device. the memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. a dielectric structure is disposed over the semiconductor substrate. a first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. a second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.
Inventor(s): Chih-Chuan YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Wen Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Ming Chang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kian-Long Lim of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Hsiu Hsu of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Lien Jung Hung of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Wei Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/417, H01L29/423, H10B10/00
CPC Code(s): G11C11/417
Abstract: the present disclosure describes a method for memory cell placement. the method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. the method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. the method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.
Inventor(s): Hidehiro FUJIWARA of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yu LIN of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Sahil Preet Singh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Yu PAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Huei CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jen LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/419, G11C5/14, G11C7/12, G11C11/412, G11C11/418, H03K19/013
CPC Code(s): G11C11/419
Abstract: the present disclosure describes embodiments of a write assist circuit. the write assist circuit can include a control circuit and a voltage generator. the control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. the voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. the voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.
Inventor(s): Meng-Fan CHANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Cheng CHIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C13/00, G11C7/08, H03K19/20
CPC Code(s): G11C13/004
Abstract: a memory includes a memory device, a reading device and a feedback device. the memory device stores a plurality of bits. the reading device includes first and second reading circuits coupled to the memory device. the second reading circuit is coupled to the first reading circuit at a first node. the first and second reading circuits cooperates with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits. the feedback device adjusts at least one of the first reading circuit or the second reading circuit based on the first voltage signal. the first and second reading circuits generate a second voltage signal, different from the first voltage signal, corresponding to the bits, after the at least one of the first reading circuit or the second reading circuit is adjusted by the feedback device.
Inventor(s): Yen-Yu CHEN of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chi LU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Pin TSAO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hsun CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/28, H01L29/49
CPC Code(s): H01L21/28088
Abstract: a device includes gate spacers over a substrate, and a gate structure between the gate spacers. the gate structure includes an interfacial layer over the substrate, a metal oxide layer over the interfacial layer, a metal oxide layer over the interfacial layer, a first metal nitride layer over the metal oxide layer, a second metal nitride over the first metal nitride layer, and a tungsten-containing material interposing the first metal nitride layer and the second metal nitride layer.
Inventor(s): Ju-Li Huang of Mingjian Township (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Liang Chuang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsi Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Bin Huang of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/28, H01L21/3213, H01L21/8238, H01L27/092, H01L29/49, H01L29/51, H01L29/66
CPC Code(s): H01L21/28247
Abstract: semiconductor device structures having metal gate structures with tunable work function values are provided. in one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.
Inventor(s): Yu-Chen WEI of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Inn WU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tzi-Yi SHIEH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/321, H01L21/306, H01L21/8234
CPC Code(s): H01L21/3212
Abstract: in a method of manufacturing a semiconductor device, a sacrificial gate structure is formed over a substrate. the sacrificial gate structure includes a sacrificial gate electrode. a first dielectric layer is formed over the sacrificial gate structure. a second dielectric layer is formed over the first dielectric layer. the second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed while a lower portion of the sacrificial gate structure is embedded in the first dielectric layer. a third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. a fourth dielectric layer is formed over the third dielectric layer. the fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. the sacrificial gate electrode is removed.
Inventor(s): Shin-Wei SHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hsiang CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chao MAO of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Fu TSAI of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei LU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, H01L21/683, H01L21/78
CPC Code(s): H01L21/67132
Abstract: a die-transfer tool includes a source frame stage, a target frame stage, a roller, and a driving mechanism. the source frame stage is configured to secure a first tape. the target frame stage is configured to secure a second tape, wherein the second tape has an adhesive surface facing the source frame stage when the second tape is mounted on the target frame stage. the roller is configured to move laterally over the non-adhesive surface of the second tape opposite the adhesive surface when a plurality of dies is between the first tape and the adhesive surface of the second tape. the driving mechanism is configured to vertically drive the target frame stage to adjust the relative position of the target frame stage above the source frame stage.
Inventor(s): Ching-Wen CHENG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Xin-Kai HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuei-Hsiung CHO of Xinpu Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/673, C23C16/458, C23C16/46, H01L21/02
CPC Code(s): H01L21/67309
Abstract: in an embodiment, a system includes: a base; and a rod set comprising multiple rods connected to the base, wherein each rod of the rod set comprises multiple fingers disposed in a vertically-stacked relationship to each other and separated respectively from each other by respective slots, wherein each slot is configured to receive a bevel of a wafer, and wherein each of the multiple fingers comprises a rounded end at a furthest extension.
Inventor(s): Ching-Fu YEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Lung CHUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Wei LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chen CHAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Yi YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Han LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/532
CPC Code(s): H01L21/76877
Abstract: a method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.
Inventor(s): Chung-Ting KO of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-En LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chi-On CHUI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/02, H01L21/033, H01L27/088
CPC Code(s): H01L21/823481
Abstract: a semiconductor device includes a substrate, first and second semiconductor strips, a dummy fin structure, first and second channel layers, a gate structure, and crystalline and amorphous hard mask layers. the first and second semiconductor strips extend upwardly from the substrate and each has a length extending along a first direction. the dummy fin structure is laterally between the first and second semiconductor strips. the first and second channel layers extend in the first direction above the first and second semiconductor strips and are arranged in a second direction substantially perpendicular to the substrate. the crystalline hard mask layer extends upwardly from the dummy fin structure and has an u-shaped cross section. the amorphous hard mask layer is in the crystalline hard mask layer. the amorphous hard mask layer has an u-shaped cross section conformal to the u-shaped cross section of the crystalline hard mask layer.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon-Jhy LIAW of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L23/481
Abstract: a semiconductor device includes a transistor structure disposed on a first side of a substrate and a back-side via structure disposed on a second side of the substrate opposite to the first side. the transistor structure includes a pair of epitaxial structures and a channel feature extending in a channel length direction to be disposed between the epitaxial structures. the channel feature has a width in a channel width direction transverse to the channel length direction. the back-side via structure extends through the substrate so as to be connected to a bottom surface and a sidewall surface of a lower portion of a corresponding one of the epitaxial structures. the back-side via structure has a width in the channel width direction, which is greater than the width of the channel feature.
Inventor(s): Ling-Wei LI of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Hua CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lin HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L21/56, H01L21/683, H01L23/31, H01L25/10
CPC Code(s): H01L23/49827
Abstract: a package structure is provided. the package structure includes a conductive structure having a first portion with a first sidewall and a second portion with a second sidewall, and the first sidewall and the second sidewall have different slopes. the package structure also includes a semiconductor chip beside the conductive structure and a protective layer laterally surrounding the conductive structure and the semiconductor chip. the protective layer covers the first sidewall of the first portion and the second sidewall of the second portion. the protective layer is made of a polymer material dispersed with fillers.
Inventor(s): Chih-Hsuan LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsi Chung CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ji-Ling WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Teng LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/535, H01L21/3213, H01L21/768, H01L23/528, H01L23/532
CPC Code(s): H01L23/535
Abstract: a method of manufacturing a semiconductor device includes forming a first dielectric layer over a substrate, forming a metal layer in the first dielectric layer, forming an etch stop layer on a surface of the first dielectric layer and the metal layer, removing portions of the metal layer and the etch stop layer to form a recess in the metal layer, and forming a tungsten plug in the recess. the recess is spaced apart from a bottom surface of the etch stop layer.
Inventor(s): Po-Hao TSAI of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Liang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao CHUANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Techi WONG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Po-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L23/31, H01L25/00, H01L25/18
CPC Code(s): H01L23/5389
Abstract: a package structure is provided, which includes a redistribution structure, an interposer substrate disposed over the redistribution structure, a first semiconductor die disposed between the redistribution structure and the interposer substrate, a second semiconductor die partially overlapping the first semiconductor die in a direction perpendicular to a surface of the redistribution structure, and a first protective layer surrounding the first semiconductor die.
Inventor(s): Tsung-Fu TSAI of Changhua City (TW) for taiwan semiconductor manufacturing company, ltd., Kung-Chen YEH of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., I-Ting HUANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Ting LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei LU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/56, H01L21/683, H01L21/768, H01L21/78, H01L23/31, H01L23/48, H01L23/544, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H01L23/562
Abstract: a method for forming a package structure is provided, which includes recessing a substrate to form a trench, disposing a first stacked die package structure over the substrate, forming an underfill layer over the first stacked die package structure and in the trench, and forming a package layer over the underfill layer and in the trench.
Inventor(s): Chuei-Tang WANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tso-Jung CHANG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Ping LIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jeng-Shien HSIEH of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Peng LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chieh-Yen CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua YU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/08
Abstract: a chip stack structure is provided. the chip stack structure includes a first chip including a first substrate and a first interconnect structure over the first substrate. the chip stack structure includes a second chip over and bonded to the first chip. the second chip has a second interconnect structure and a second substrate over the second interconnect structure. the chip stack structure includes an insulating layer over the second interconnect structure and surrounding the second substrate. the chip stack structure includes a conductive plug penetrating through the insulating layer to the second interconnect structure.
Inventor(s): Hsing-Yuan Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Szu Lee of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yi Chen Ho of Taichung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L25/065, H10B80/00
CPC Code(s): H01L24/19
Abstract: a method includes forming a conductive pad over a substrate, forming a multi-layer passivation structure on the conducive pad, patterning a top portion of the multi-layer passivation structure to form a first opening, forming a mask film on sidewall surfaces of the patterned top portion of the multi-layer passivation structure, after the forming of the mask film, performing a first etching process to remove a portion of the multi-layer passivation structure directly under the first opening to form a second opening, after the performing of the first etching process, selectively removing the mask film, performing a second etching process to remove a portion of the multi-layer passivation structure directly under the second opening, thereby forming a third opening exposing the conductive pad, and forming a bonding structure in the third opening, where an etchant of the second etching process is different than an etchant of the first etching process.
Inventor(s): Wei-Chih Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang Hu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sih-Hao Liao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/29
CPC Code(s): H01L24/19
Abstract: a die includes a substrate, a conductive pad, a connector a protection layer, and a passivation layer. the conductive pad is disposed over the substrate. the connector is disposed on the conductive pad. the connector comprises a seed layer and a conductive post on the seed layer. the protection layer laterally covers the connector. the passivation layer is disposed between the protection layer and the conductive pad. the conductive post is separated from the passivation layer and the protection layer by the seed layer.
Inventor(s): Mao-Yen Chang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chia Lai of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Shiuan Wong of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ting Hao Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Lung Pan of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Jen Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/56, H01L23/544, H01L23/58
CPC Code(s): H01L24/96
Abstract: a semiconductor structure includes a functional die, a dummy die, a conductive feature, a seal ring and an alignment mark. the dummy die is electrically isolated from the functional die. the conductive feature is electrically connected to the functional die. the seal ring is disposed aside the conductive feature. the alignment mark is disposed between the seal ring and the conductive feature, and the alignment mark is electrically isolated from the dummy die, the conductive feature and the seal ring.
Inventor(s): Hsien-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jie Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L23/00, H01L23/31, H01L23/48, H01L23/528, H01L25/00
CPC Code(s): H01L25/0657
Abstract: a package includes a first die, a second die, and an encapsulant. the first die includes a first capacitor. the second die includes a second capacitor. the second die is stacked on the first die. the first capacitor is spatially separated from the second capacitor. the first capacitor is electrically connected to the second capacitor. the encapsulant laterally encapsulates the second die.
Inventor(s): Po-Han Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang Hu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L23/00
CPC Code(s): H01L25/0657
Abstract: a semiconductor device having a redistribution structure and a method of forming the same are provided. a semiconductor device includes a semiconductor structure, a redistribution structure over and electrically coupled the semiconductor structure, and a connector over and electrically coupled to the redistribution structure. the redistribution structure includes a base via and stacked vias electrically interposed between the base via and the connector. the stacked vias are laterally spaced apart from the base via.
Inventor(s): Yung-Feng Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Bao-Ru Young of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Heng Hsieh of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Chia Hsu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, G06F30/392, H01L21/82, H01L21/8238, H01L27/092
CPC Code(s): H01L27/0248
Abstract: provided is a tap cell including a substrate, a first well, a second well, a first doped region, and the second doped region. the substrate has a first region and a second region. the first well has a first dopant type and includes a first portion disposed in the first region and a second portion extending into the second region. the second well has a second dopant type and includes a third portion disposed in the second region and a fourth portion extending into the first region. the first doped region having the first dopant type is disposed in the second portion of the first well and the third portion of the second well along the second region. the second doped region having the second dopant type is disposed in the first portion of the first well and the fourth portion of the second well along the first region.
Inventor(s): Yi-Jing LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kun-Mu LI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hua YU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsz-Mei KWOK of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234, H01L21/8238, H01L21/84, H01L27/092, H01L27/12, H01L29/06, H01L29/78
CPC Code(s): H01L27/0886
Abstract: an ic structure includes a first fin structure, a first epitaxial structure, first sidewall spacers, a second fin structure, a second epitaxial structure, and second sidewall spacers. the first epitaxial structure is on the first structure. the first sidewall spacers are respectively on opposite sidewalls of the first epitaxial structure. the second epitaxial structure is on the second fin structure. the second sidewall spacers are respectively on opposite sidewalls of the second epitaxial structure. a height difference between the second sidewall spacers is greater than a height difference between the first sidewall spacers.
Inventor(s): Fong-yuan Chang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Chen Chen of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiang Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Lee-Chung Lu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jerry Chang Jui Kao of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hsiung Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Chou Liu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/118, G06F30/398, H01L27/02
CPC Code(s): H01L27/11807
Abstract: an integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. the second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
Inventor(s): Gulbagh SINGH of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Han TSAI of Miaoli (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/12, H01L21/762, H01L21/84, H01L23/48
CPC Code(s): H01L27/1207
Abstract: a semiconductor device structure includes a first mosfet device disposed at a first region of a semiconductor substrate, the first mosfet device comprises a bulk semiconductor layer contacting the semiconductor substrate, and the bulk semiconductor layer has a first height, a first gate structure over the bulk semiconductor layer, and first s/d regions disposed in the bulk semiconductor layer on opposite sides of the first gate structure; a second mosfet device disposed at a second region of the semiconductor substrate, the second mosfet device comprises a semiconductor layer over the semiconductor substrate, and the semiconductor layer has a second height different than the first height, a second gate structure over the semiconductor layer, and second s/d regions disposed in the semiconductor layer on opposite sides of the second gate structure; an insulator disposed between and in contact with the semiconductor substrate and semiconductor layer; and a spacer layer isolating first and second mosfet devices, and a portion of the spacer layer is disposed between and in contact with the insulator layer and bulk semiconductor layer.
Inventor(s): Chun-Yuan Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Chun Wang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao-Hui Tseng of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Jhy-Jyi Sze of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Shyh-Fann Ting of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Wei Chuang Wu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ting Chiang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia Ching Liao of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Yu Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H01L29/423
CPC Code(s): H01L27/14614
Abstract: in some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. on the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. a gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. the horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. the first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. the second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.
Inventor(s): Chun-Liang LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Hao CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-En LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hao CHOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14629
Abstract: a method of making a semiconductor image sensor includes forming a photodiode in a substrate. the method further includes forming a recess in the substrate. the method further includes depositing a sacrificial material in the recess. the method further includes forming an interconnect structure over the sacrificial material. the method further includes etching a plurality of trenches in the interconnect structure. the method further includes removing the sacrificial material by passing an etchant through the plurality of trenches.
Inventor(s): Shih-Yu LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Hao HUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Hsun CHEN of TaoyuanCity (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, G01J1/44, H04N25/70
CPC Code(s): H01L27/1464
Abstract: the present disclosure describes a method for the formation of mirror micro-structures on radiation-sensing regions of image sensor devices. the method includes forming an opening within a front side surface of a substrate; forming a conformal implant layer on bottom and sidewall surfaces of the opening; growing a first epitaxial layer on the bottom and the sidewall surfaces of the opening; depositing a second epitaxial layer on the first epitaxial layer to fill the opening, where the second epitaxial layer forms a radiation-sensing region. the method further includes depositing a stack on exposed surfaces of the second epitaxial layer, where the stack includes alternating pairs of a high-refractive index material layer and a low-refractive index material layer.
Inventor(s): Jeng-Wei Yu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsz-Mei Kwok of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Hsi Yang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Wei Chou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H01L29/0649
Abstract: a method includes forming isolations extending into a semiconductor substrate, recessing the isolation regions, wherein a semiconductor region between the isolation regions forms a semiconductor fin, forming a first dielectric layer on the isolation regions and the semiconductor fin, forming a second dielectric layer over the first dielectric layer, planarizing the second dielectric layer and the first dielectric layer, and recessing the first dielectric layer. a portion of the second dielectric layer protrudes higher than remaining portions of the first dielectric layer to form a protruding dielectric fin. a portion of the semiconductor fin protrudes higher than the remaining portions of the first dielectric layer to form a protruding semiconductor fin. a portion of the protruding semiconductor fin is recessed to form a recess, from which an epitaxy semiconductor region is grown. the epitaxy semiconductor region expands laterally to contact a sidewall of the protruding dielectric fin.
Inventor(s): Li-Zhen Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh Su of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Lin-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L23/48, H01L23/532, H01L29/08, H01L29/66, H01L29/78
CPC Code(s): H01L29/0649
Abstract: a semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.
Inventor(s): Shih-Chuan Chiu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao Chang of Hsinchu City 300 (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh Su of Tianzhong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yuan Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Zhen Yu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/423
CPC Code(s): H01L29/0673
Abstract: a semiconductor device with dual side source/drain (s/d) contact structures and a method of fabricating the same are disclosed. the method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second s/d regions within the superlattice structure, forming a gate structure between the first and second s/d regions, forming first and second contact structures on first surfaces of the first and second s/d regions, and forming a third contact structure, on a second surface of the first s/d region, with a work function metal (wfm) silicide layer and a dual metal liner. the second surface is opposite to the first surface of the first s/d region and the wfm silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first s/d region.
Inventor(s): Chun-Han Chen of Changhua City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Ming Lee of Yangmei City (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Kai Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Yun Wang of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8238, H01L27/092, H01L29/40, H01L29/66, H01L29/78
CPC Code(s): H01L29/41791
Abstract: in an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ild) layers over the epitaxial source/drain region; a first source/drain contact extending through the ild layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ild layers.
Inventor(s): Chi HUANG of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Che-Chia HSU of TAOYUAN CITY (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Pin TSAO of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hong HWANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L29/06, H01L29/08, H01L29/66, H01L29/786
CPC Code(s): H01L29/42392
Abstract: semiconductor structures and methods for manufacturing the same are provided. the method includes forming a first channel structure and a second channel structure and forming a first type of source/drain structures attached to opposite sides of the first channel structure and a second type of source/drain structures attached to opposite sides of the second channel structure. the method also includes forming a first gate dielectric layer having a first portion covering the first channel structure and a second portion covering the second channel structure and driving a first metal element into the first portion of the first gate dielectric layer. the method also includes forming a cap layer over both the first portion and the second portion of the first gate dielectric layer and performing an annealing process on the first gate dielectric layer under the cap layer.
Inventor(s): Yen-Ru LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chii-Horng LI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chien-I KUO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Heng-Wen TING of Pingtung County (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Chi TAI of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Lilly SU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yang-Tai HSIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/417, H01L29/78
CPC Code(s): H01L29/66795
Abstract: a device includes a first semiconductor fin, a second semiconductor fin, a source/drain epitaxial structure, a semiconductive cap, and a contact. the first semiconductor fin and the second semiconductor fin are over a substrate. the source/drain epitaxial structure is connected to the first semiconductor fin and the second semiconductor fin. the source/drain epitaxial structure includes a first protruding portion and a second protruding portion aligned with the first semiconductor fin and the second semiconductor fin, respectively. the semiconductive cap is on and in contact with the first protruding portion and the second protruding portion. a top surface of the semiconductive cap is lower than a top surface of the first protruding portion of the source/drain epitaxial structure. the contact is electrically connected to the source/drain epitaxial structure and covers the semiconductive cap.
Inventor(s): Wan-Yi Kao of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Cheng Shiau of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chunyao Wang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Tang Peng of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Cheng Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L21/762, H01L21/8234, H01L27/092, H01L29/51, H01L29/66
CPC Code(s): H01L29/785
Abstract: a semiconductor device and method of manufacture are provided. in embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. the first liner is annealed to transform the first material to a second material. a second liner is deposited to line the recess, the second liner comprising a third material. the second liner is annealed to transform the third material to a fourth material.
Inventor(s): Chang-Yin CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Cheng CHANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Han LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L29/08, H01L29/66
CPC Code(s): H01L29/785
Abstract: a semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. the upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. the first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. the gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.
Inventor(s): Martin Christopher Holland of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Blandine Duriez of Bruxelles (BE) for taiwan semiconductor manufacturing company, ltd., Marcus Johannes Henricus van Dal of Linden (BE) for taiwan semiconductor manufacturing company, ltd., Yasutoshi Okuno of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/8234, H01L29/267, H01L29/417, H01L29/66
CPC Code(s): H01L29/7851
Abstract: in an embodiment, a device includes: a semiconductor substrate having a channel region; a gate stack over the channel region; and an epitaxial source/drain region adjacent the gate stack, the epitaxial source/drain region including: a main portion in the semiconductor substrate, the main portion including a semiconductor material doped with gallium, a first concentration of gallium in the main portion being less than the solid solubility of gallium in the semiconductor material; and a finishing portion over the main portion, the finishing portion doped with gallium, a second concentration of gallium in the finishing portion being greater than the solid solubility of gallium in the semiconductor
Inventor(s): Chen-Hao Chiang of Jhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Eugene I-Chun Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Ming Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L31/028, H01L31/0203, H01L31/103, H01L31/105, H01L31/18
CPC Code(s): H01L31/028
Abstract: various embodiments of the present disclosure are directed towards an optoelectronic device. the device includes a substrate, and a germanium photodiode region extending into an upper surface of the substrate. the germanium photodiode region has a curved upper surface that extends past the upper surface of the substrate. a silicon cap overlies the curved upper surface of the germanium photodiode region. there is an absence of oxide between the curved upper surface of the germanium photodiode region and an upper surface of the silicon cap.
Inventor(s): Yueh CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Hsuan CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Xiang LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Guang-Cheng WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K3/037, H01L21/8238, H03K3/356, H03K3/3562
CPC Code(s): H03K3/0372
Abstract: a flip-flop includes a first set of transistors of a first type being located in a first row and a second set of transistors of a second type being located in a second row. the second type being different from the first type. the first and second set of transistors include a first master latch circuit and a second master latch circuit. the first and second master latch circuit are separated from each other in the first direction by a first distance. a first output signal of the first and second master latch circuit is a first input signal of the first master latch circuit and the second master latch circuit. a second output signal of the first and second master latch circuit is a second input signal of the first and second master latch circuit.
Inventor(s): Chun-Chieh Lu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Feng Young of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yu Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, H01L21/02, H01L21/383, H01L21/425, H01L21/477, H01L29/24, H10B51/30
CPC Code(s): H10B51/20
Abstract: the present disclosure relates to an integrated chip device. the integrated chip device includes a plurality of conductive lines disposed over a substrate. the plurality of conductive lines are stacked onto one another and are separated from one another by dielectric layers interleaved between adjacent ones of the plurality of conductive lines. a ferroelectric layer is along sidewalls of the plurality of conductive lines and the dielectric layers. the ferroelectric layer separates a channel layer from the plurality of conductive lines. a species is disposed within the ferroelectric layer. the species has a concentration that decreases from the channel layer towards a surface of the ferroelectric layer that faces away from the channel layer.
Inventor(s): Chuei-Tang WANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tso-Jung CHANG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Shiang LIAO of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Jeng-Shien HSIEH of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Peng LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Ping LIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chieh-Yen CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua YU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B80/00, H01L23/00, H01L23/31, H01L23/538
CPC Code(s): H10B80/00
Abstract: a package structure and a formation method are provided. the method includes bonding a first memory-containing chip structure to a second memory-containing chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding. the method also includes bonding a logic control chip structure to the second memory-containing chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding. the logic control chip structure is formed using a more advanced technology node than the second memory-containing chip structure.
Inventor(s): Tai-Yen PENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Hsien WEI of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chih WEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Ren DAI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Min LEE of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chih LAI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Han-Ting TSAI of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/01, G11C11/16, H10B61/00, H10N50/10, H10N50/80
CPC Code(s): H10N50/01
Abstract: a memory device includes a bottom electrode contact, a magnetic tunnel junction pattern, a protection insulating layer, a first capping layer, an interlayer insulating layer, and a second capping layer. the magnetic tunnel junction pattern is over the bottom electrode contact. the protection insulating layer surrounds the magnetic tunnel junction pattern. the first capping layer surrounds the protection insulating layer. the interlayer insulating layer surrounds the first capping layer. the second capping layer is over the first capping layer and the interlayer insulating layer.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on June 20th, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- B23K26/361
- B23K26/035
- B23K26/062
- H01L21/02
- H01L21/66
- CPC B23K26/361
- Taiwan semiconductor manufacturing company, ltd.
- B32B38/18
- H01L21/48
- H01L23/00
- CPC B32B38/1858
- G01R19/165
- H02H1/00
- H02H9/02
- CPC G01R19/16519
- G02B6/12
- G02B6/122
- CPC G02B6/12002
- G02B6/124
- G02B6/136
- H01L25/00
- H01L25/065
- CPC G02B6/1245
- G03F1/36
- G03F1/78
- G03F7/20
- CPC G03F1/36
- G05F1/565
- G05F1/46
- CPC G05F1/565
- G06F1/10
- G06F30/396
- CPC G06F1/10
- G06F7/544
- G06F5/01
- CPC G06F7/5443
- G06F21/75
- G11C11/412
- G11C11/418
- G11C11/419
- H03K19/003
- H04L9/00
- H04L9/32
- CPC G06F21/755
- G06F30/392
- G06F30/398
- G06F115/08
- H01L27/02
- H01L29/423
- CPC G06F30/392
- G11C5/14
- G11C16/30
- CPC G11C5/14
- G11C11/16
- G11C11/56
- H10B53/30
- H10B61/00
- H10B63/00
- CPC G11C11/161
- G11C11/417
- H10B10/00
- CPC G11C11/417
- G11C7/12
- H03K19/013
- CPC G11C11/419
- G11C13/00
- G11C7/08
- H03K19/20
- CPC G11C13/004
- H01L21/28
- H01L29/49
- CPC H01L21/28088
- H01L21/3213
- H01L21/8238
- H01L27/092
- H01L29/51
- H01L29/66
- CPC H01L21/28247
- H01L21/321
- H01L21/306
- H01L21/8234
- CPC H01L21/3212
- H01L21/67
- H01L21/683
- H01L21/78
- CPC H01L21/67132
- H01L21/673
- C23C16/458
- C23C16/46
- CPC H01L21/67309
- H01L21/768
- H01L23/532
- CPC H01L21/76877
- H01L21/033
- H01L27/088
- CPC H01L21/823481
- H01L23/48
- H01L29/786
- CPC H01L23/481
- H01L23/498
- H01L21/56
- H01L23/31
- H01L25/10
- CPC H01L23/49827
- H01L23/535
- H01L23/528
- CPC H01L23/535
- H01L23/538
- H01L25/18
- CPC H01L23/5389
- H01L23/544
- CPC H01L23/562
- CPC H01L24/08
- H10B80/00
- CPC H01L24/19
- H01L23/29
- H01L23/58
- CPC H01L24/96
- CPC H01L25/0657
- H01L21/82
- CPC H01L27/0248
- H01L21/84
- H01L27/12
- H01L29/06
- H01L29/78
- CPC H01L27/0886
- H01L27/118
- CPC H01L27/11807
- H01L21/762
- CPC H01L27/1207
- H01L27/146
- CPC H01L27/14614
- CPC H01L27/14629
- G01J1/44
- H04N25/70
- CPC H01L27/1464
- CPC H01L29/0649
- H01L29/08
- CPC H01L29/0673
- H01L29/417
- H01L29/40
- CPC H01L29/41791
- CPC H01L29/42392
- CPC H01L29/66795
- CPC H01L29/785
- H01L29/267
- CPC H01L29/7851
- H01L31/028
- H01L31/0203
- H01L31/103
- H01L31/105
- H01L31/18
- CPC H01L31/028
- H03K3/037
- H03K3/356
- H03K3/3562
- CPC H03K3/0372
- H10B51/20
- H01L21/383
- H01L21/425
- H01L21/477
- H01L29/24
- H10B51/30
- CPC H10B51/20
- CPC H10B80/00
- H10N50/01
- H10N50/10
- H10N50/80
- CPC H10N50/01